JPH06175740A - Reference voltage circuit with positive temperature compensation - Google Patents

Abstract

PURPOSE: To generate a precise reference voltage especially for a voltage regulator. CONSTITUTION: This circuit is provided with a current source generating a desired reference voltage ref at both ends of an element string. This current source is controlled by differential amplifiers T4 to T7 and R1 receiving an input varying with a chip temp. This differential amplifier increases reference voltage when the chip temp. is raised. When a voltage regulator is used for an FET memory, the boosting of a regulator voltage caused by temp. is useful for compensating the increasing of a speed at which an FET storage cell looses an electric charge expressing data.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a circuit for forming an accurate reference voltage for a voltage regulator used in FET memories in particular.

The present invention provides an accurate reference voltage that is particularly useful for power supply voltage regulators.

[0003]

BACKGROUND OF THE INVENTION Although voltage regulators are well known, it would be useful to summarize the features of voltage regulators that apply specifically to the present invention.

Series voltage regulators typically have power transistors controlled from a differential amplifier. This regulator operates from a controlled power supply with some higher voltage. For example, a regulator that produces a 3.3 volt output may operate from a 5 volt power supply. One input of the differential amplifier receives a portion of this voltage at the regulator output and the other input receives a reference voltage that is the corresponding portion of the controlled voltage. In the regulator in which the present invention is used, the reference voltage is half the controlled voltage, for example a 1,65 volt reference for a voltage regulator that produces a 3.3 volt output.

[0005]

SUMMARY OF THE INVENTION One object of the present invention is to provide an improved reference voltage circuit for a voltage regulator.

[0006]

The reference voltage circuit includes a diode-resistor string and a FET connected to act as a current source for the string. The gate terminal of the FET is provided with a suitable voltage such that the FET drain current causes a reference voltage drop across this string.

This reference voltage changes depending on the chip temperature,
This feature is particularly convenient for voltage regulators for FET memories (the charge on the capacitors representing the data bits leaks from the storage cells faster the higher the chip temperature).

The gate voltage for the current source is controlled by a differential amplifier. Both inputs of this differential amplifier are connected to separate current source FETs
Receives a reference voltage from the string. One diode
The strings have large diodes and the other strings have small diodes. These diodes provide the two strings with different temperature characteristics and the differential amplifier controls the current source FET to increase the reference voltage in the proper ratio as the chip temperature increases.

[0009]

EXAMPLE Circuit of FET T11 P-channel FET T11 has its source terminal VDD
, And its gate terminal is supplied with an appropriate voltage (described below) to form a current source (the arrow in the figure indicates a P-channel FET).
Two resistors R3 and R4 and diode D4 are
The drain of is connected to ground. The reference voltage ref is the FET in the voltage drop across R3, R4 and D4.
It is formed at the drain terminal of T11. An FET is connected to this terminal to form a capacitor C1.

Another output voltage vbref of 1.2 volts
(Bandgap voltage) is formed at the common connection point of the resistors R3 and R4.

The other element in this figure is the FET T11.
Establishes an appropriate voltage at the gate terminal of the
ef provides a selected value of ef, which causes the gate voltage to change in response to chip temperature, thereby increasing the current in T11 and increasing the voltage ref and vbref when chip temperature increases. I am trying to increase by the amount.

The first diode reference voltage string (voltage
d3) Two diode strings and a current source provide the reference voltage d3 and CMP to the differential amplifier. Some of the elements in these circuits are understood from the circuit description of FET T10.

These diode strings provide temperature compensation. In the first reference voltage string, the diodes D5, D6 and D7 are connected in series with the resistor R2 and the FET T8. The voltage across this resistor is added to the reference voltage (lower than node CMP).

P-channel FET T8 is connected to form a current source. Its source terminal is connected to VDD and its drain terminal is connected to a resistor-diode string. As should be noted here, the gate of T8 is connected (for operation described later) to the output of the differential amplifier. The operation of T10 will be described later.

Second diode reference voltage string (signal
CMP) D1, D2, D3 and T10 are similar to the string just described, except as described hereafter. These diodes are small compared to D5-D7 and their voltage changes less with temperature than the diodes of the first string. As should be noted here, capacitor C2 is connected to node d3, while node CM
P has no corresponding capacitor. FET T9 is part of the starting circuit described later.

The voltage drop across the temperature compensating diode varies as a function of temperature, and as is well known, large diodes (D5, D6 and D7) are more temperature dependent than smaller diodes (D1, D2 and D3). . Recalling that the voltages d3 and CMP are approximately equal, and as the chip temperature changes, the difference between the voltages d3 and CMP also changes (one example given later).

The differential amplifier FETs T4, T5, T6 and T7 and the resistor R1 form a differential amplifier. N-channel FETs T6 and T7 are connected to receive inputs d3 and CMP from the first and second diode strings, respectively. P-channel FETs T4 and T5 have their lease terminals tied to VDD and their gate terminals tied together, thereby acting as a similar current source according to the voltage at the gate connections.

The gate terminals of the FETs T4 and T5 are FE
It is connected to the drain terminal of T T7. FET T
The output of the differential amplifier at the drain terminal of 6 is connected to the output pad vbs, which will be referred to by this pad name.

The operating voltages d3 and CMP in response to the inputs d3 and CMP are approximately equal and the two FETs T6 and T7 of the differential amplifier are conducting approximately equally. (Voltages d3 and CMP vary with temperature, as explained below.) At a selected temperature (typically room temperature), the FET
The voltage vbs at the drain terminal of T6 and the gate terminal of FET T11 produces a desired voltage drop across the string of elements at the drain terminal of T11 (1.65 volts in the particular circuit just described) F
Establish current level at ET T11.

Operation in Response to Temperature Changes As one example, assume that the chip temperature rises from 0 ° C to 90 ° C. More current flows in the first string, which causes a larger drop across R2 and a higher voltage CMP at the gate of FET T7. The current in the second string does not increase to a corresponding extent and the voltage d3 at the gate of the FET T6 remains relatively unchanged.

T8 and T10 are comparable in both size and gate voltage, and they supply the same current to both diode strings. At higher temperatures, the current from the large diode increases faster than the current from the small diode. Therefore, large diode strings have a smaller voltage drop across them. D
3 is greater than CMP and vbs.

In response to this change in input voltage CMP, the differential amplifier causes the drain terminal of FET T6 and T1.
It lowers the voltage vbs at the gate terminal of 1, which causes T11 to conduct more current. The degree of change in the reference voltage with temperature is a function of the diode characteristics, the gain of the differential amplifier, and the value of the resistor connected to the drain terminal of FET T11. Thus, this circuit can easily be adapted to provide a specific voltage ref and a specific correlation of this voltage with the chip temperature.

Starting circuits FETs T1, T2, T3, and T9 cooperate to start the circuit when the circuit is first powered.
The FET T9 is connected in parallel with the FET T10, and the T9 is connected to the line (START, as will be described later).
When turned on (in response to the signal above), it pulls up node d3, which turns on FET T7 in the differential amplifier. This differential amplifier then has its output voltage vbs
To turn on current source FETs T8, T10 and T11. Line START is FET T
The gate terminal of 9 is connected to the drain terminal of FET T3.

P-channel FETs T1 and T2 are each connected to produce a threshold voltage Vt between their lease and drain terminals. (FET T3
Is much smaller than T1 and T2). When the circuit first receives power, T3 turns on in response to the rising level at its gate (node d3), producing a voltage VDD-2Vt at the gate terminal of FET T9.

Other Embodiments From the description of the preferred embodiment of this reference voltage circuit and its description of operation, those skilled in the art will recognize appropriate modifications within the spirit of the invention and the intended scope of the claims.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a preferred reference voltage circuit of the present invention.

[Explanation of symbols]

 ref: reference voltage vbref: output voltage d3: reference voltage CMP: reference voltage

Claims (11)

[Claims] 1. A voltage reference circuit comprising: a FET (T11) connected as a current source; and a drain terminal of the current source FET and circuit ground so as to generate a voltage (ref) in response to a current. The elements connected in between,
A differential amplifier (T4, T5, T6, T7) connected to control conduction of the current source FET, and a first means (D5) for providing a voltage (CMP) to one input of the differential amplifier. , D6, D7) and second means (D1, D2, D) for providing a voltage (d3) to the other input of the differential amplifier.
3) and the first and second means have different temperature characteristics for varying the reference voltage as a function of chip temperature. 2. The element connected between the drain terminal and ground is a diode (D4) and a resistor (R).
3. The voltage reference circuit according to claim 1, further comprising 3). 3. The element connected between the drain terminal and ground further comprises a resistor having a value for producing a bandgap reference voltage of about 1.2 volts. Voltage reference sea route described in 2. 4. The first means is a diode (D5, D
6, D7) and a first means (T8) for supplying a current to the diode, wherein the second means supplies a current to the second string of diodes (D1, D2, D3) and the diode. Second means for supplying (T10)
3. The voltage reference circuit of claim 2 including: and the diode having a voltage that varies with temperature and varies with the diode current. 5. The diode of the first string is larger than the diodes of the second string, thereby providing a greater ratio of voltage change to temperature change than the diodes of the second string. The voltage reference circuit according to claim 4. 6. A first FET (T8) in which the first and second means for supplying current to the diode string are connected to the first string and a second FET in which the second string is connected to the second string. (T10) is included, The voltage reference circuit of Claim 5 characterized by the above-mentioned. 7. The gate terminals of the first and second FETs are connected to the output of the amplifier to increase the current through the first and second strings when the chip temperature increases. The voltage reference circuit according to claim 6. 8. The first diode string includes a resistor to further increase the voltage drop (CMP) across the string when the differential amplifier increases its output in response to increasing temperature. The voltage reference circuit according to claim 7, wherein: 9. A first differential amplifier connected to a resistor (R1) for differentially conducting in response to a voltage from one of the first and second diode strings.
(T6) and second (T7) FETs and third (T4) and fourth (T5) connected as load devices, respectively
FETs are included, the gate terminals of the third and fourth FETs are connected to the drain terminals of the first and second FETs, and the other drain terminal of the first and second FETs is connected to the gate of the current source FET. 9. The voltage reference circuit according to claim 8, wherein the voltage reference circuit is connected. 10. The voltage reference circuit of claim 8 including means for turning on the second current source (T10) when power is first applied to the circuit. 11. An FE in which the means for turning on the second current source is connected in parallel with the second current source.
11. T (T9) and means connected to the gate of the FET for turning on the second current source when power is first applied to the circuit.
The voltage reference circuit described.