JPH06169465A - Linear color charge-coupled device image sensor and its execution method - Google Patents

Linear color charge-coupled device image sensor and its execution method

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Publication number
JPH06169465A
JPH06169465A JP4054906A JP5490692A JPH06169465A JP H06169465 A JPH06169465 A JP H06169465A JP 4054906 A JP4054906 A JP 4054906A JP 5490692 A JP5490692 A JP 5490692A JP H06169465 A JPH06169465 A JP H06169465A
Authority
JP
Japan
Prior art keywords
pixel
induction
gate
transmission gate
ccd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4054906A
Other languages
Japanese (ja)
Other versions
JP2909789B2 (en
Inventor
Ryochu Go
亮 中 呉
Chaokon Sai
▲ちゃお▼ 坤 崔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HUALON MICROELECTRON CORP
KARIYUU BIDENSHI KOFUN YUUGENK
KARIYUU BIDENSHI KOFUN YUUGENKOUSHI
Original Assignee
HUALON MICROELECTRON CORP
KARIYUU BIDENSHI KOFUN YUUGENK
KARIYUU BIDENSHI KOFUN YUUGENKOUSHI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by HUALON MICROELECTRON CORP, KARIYUU BIDENSHI KOFUN YUUGENK, KARIYUU BIDENSHI KOFUN YUUGENKOUSHI filed Critical HUALON MICROELECTRON CORP
Priority to JP4054906A priority Critical patent/JP2909789B2/en
Publication of JPH06169465A publication Critical patent/JPH06169465A/en
Application granted granted Critical
Publication of JP2909789B2 publication Critical patent/JP2909789B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE: To shorten the processing time to improve a system function and to reduce the volume and the cost by arranging three induced picture elements close and reducing the distances between them to eliminate the differences in transmission times of induced signals for optical scanning. CONSTITUTION: Three induced picture elements SA0, SB0, and SC0 are arranged close, and a signal which the picture element sensed is transmitted to a CCD transmission gate CH1 by a transfer gate TA and is outputted from an output port O1 . A signal which the picture element SC0 sensed is transmitted from a transfer gate TC to a gate CH3 through vertical transmission gates CVA, CH2, and CVB and is outputted from an output port O3 . A signal which the picture element SB0 sensed is transmitted to the gate CH2 through transfer gates TB, SC0, TC, and CVA after signal transmission of SC0 and is outputted from an output port O2 . Thus, the processing time is shortened to improve the function, and the volume and the cost are reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電荷結合素子イメージセ
ンサ(チャージ カップルド デバイス イメージ セ
ンサ、以下CCDISと略する)及びその実行方法に関
し、特に線形カラー電荷結合素子イメージセンサ及びそ
の実行方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge coupled device image sensor (charge coupled device image sensor, hereinafter abbreviated as CCDIS) and a method for implementing the same, and more particularly to a linear color charge coupled device image sensor and a method for implementing the same.

【0002】[0002]

【従来の技術】図3に示す如く、従来のCCDIS構造
の中には三つの誘導画素SA,SB,SC(通常は赤,
藍、緑の三画素)を含んでおり、光の激発を受けるとそ
れぞれ誘導画素が電荷を帯び、かつ各々移転ゲートT
1,T2,T3を経て、更に各自CCD伝送ゲート
11,C12,C21,C22,C31,C32に伝送して出力さ
れるのである。しかしながら、この種CCDISの各誘
導画素は互いの間隔距離が比較的遠く、光走査の際に各
誘導画素のデータ伝送に時間のずれが見られ、そして一
つの完全なデータは三つの誘導画素のデータ総和である
ことから、使用上、一部ハードメモリを占用して各誘導
画素のデータを記憶し、然る後、対応データを選出して
一つの完全なデータに作り直さなければならないので、
メモリ容量を浪費するばかりでなく、かつソフトウェア
の処理時間がかなり長引くと共に使用装置の体積が相当
大きくなる。
2. Description of the Related Art As shown in FIG. 3, in a conventional CCDIS structure, three induction pixels SA, SB, SC (usually red,
3 pixels of indigo and green), each of the induction pixels is charged when exposed to a sudden light, and each transfer gate T
1, via the T2, T3, is being outputted and transmitted further their CCD transfer gates C 11, to C 12, C 21, C 22 , C 31, C 32. However, the inductive pixels of this type of CCDIS are relatively far apart from each other, and there is a time lag in the data transmission of each inductive pixel during optical scanning, and one complete data is equivalent to three inductive pixels. Since it is the sum of data, in use, it is necessary to occupy a part of the hard memory to store the data of each induction pixel, and after that, select the corresponding data and recreate it as one complete data.
Not only is the memory capacity wasted, but the processing time of the software is considerably lengthened and the volume of the apparatus used is considerably increased.

【0003】上記の問題を解決するため、もう一種のC
CDISが提案されるとなるが、図4に示すように、該
CCDISは、三つの誘導画素SA1,SB1,SC1
の中、二つの誘導画素SA1,SB1を近接させて排列
するのであるが、もう一つの誘導画素SC1は尚も該両
誘導画素SA1,SB1と一つの伝送ゲートC2を隔て
ているので所期するほどの効果を得られない。更に、図
5に示すような、もう一種ほかのCCDISが登場する
のであるが、該種CCDISは面状構造を呈して、図中
のS11,S12,S21,S22が誘導画素を表わし、それぞ
れ画素が光の激発を受けると電荷を帯び或る時間の積分
を経て、移転ゲートT11,T12より電荷を垂直CCD伝
送ゲートCV1 ,CV2 に送り、更に垂直に水平CCD
伝送ゲートに伝送した後、信号を出力ポートに経由させ
電圧信号を出力するのであり、この種構造における画素
と画素との間隔は己に一つの画素の大きさに縮小された
とはいえ、単位誘導画素内に移転ゲートT11と垂直CC
D伝送ゲートCV1 を含んでいることから、誘導の有効
面積は僅かに半分しか残らないため、CCDの誘導率は
大いに低下する。
In order to solve the above problems, another type of C
CDIS will be proposed, but as shown in FIG. 4, the CCDIS has three guiding pixels SA1, SB1, SC1.
Among the two induction pixels SA1 and SB1, the two induction pixels SA1 and SB1 are arranged close to each other, but the other induction pixel SC1 still separates the two induction pixels SA1 and SB1 from one transmission gate C2. Not so effective. Furthermore, another kind of CCDIS, such as that shown in FIG. 5, appears, but this kind of CCDIS has a planar structure, and S 11 , S 12 , S 21 , and S 22 in the figure are induction pixels. When each pixel receives a burst of light, it is charged, and after a certain period of integration, the charges are transferred from the transfer gates T 11 and T 12 to the vertical CCD transmission gates CV 1 and CV 2 , and then vertically to the horizontal CCD.
After transmitting to the transmission gate, the signal is output to the output port to output a voltage signal.Although the distance between pixels in this type of structure is reduced to the size of one pixel, the unit induction Transfer gate T 11 and vertical CC in pixel
Due to the inclusion of the D transmission gate CV 1 , the effective area of induction remains only half, so the induction rate of the CCD is greatly reduced.

【0004】[0004]

【発明が解決しようとする課題】上記従来の電荷結合素
子イメージセンサ及びその実行方法における問題点に鑑
み、本発明は、光誘導率が高い、ソフトウェアの処理時
間を節減してシステムの機能を向上し、且つハードウェ
アの設置コストを軽減し、並びに使用システムの体積を
縮小し得る線形カラー電荷結合素子イメージセンサ及び
その実行方法を提供することを目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned problems in the conventional charge-coupled device image sensor and the method of executing the same, the present invention improves the function of the system by reducing the software processing time, which has a high light induction rate. In addition, it is an object of the present invention to provide a linear color charge coupled device image sensor and a method of implementing the same, which can reduce the installation cost of hardware and the volume of a system used.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するた
め、本発明は、第1の誘導画素SA0と;上記第1の誘
導画素SA0片側に適当な絶縁間隔を保って近接に排列
される第2の誘導画素SB0と;上記第2の誘導画素S
B0他側に近接して排列される第3の誘導画素SC0
と;上記第1の誘導画素SA0他側に近接して設けられ
る第1の移転ゲートTAと;上記第2の誘導画素SB0
及び第3の誘導画素SC0との間に介装される第2の移
転ゲートTBと;上記第3の誘導画素SC0他側に近接
して設けられる第3の移転ゲートTCと;上記第1の移
転ゲートTA外側に設けられる第1のCCD伝送ゲート
CH1と;上記第3の移転ゲートTC外側に設けられる
第2のCCD伝送ゲートCH2と;上記第2のCCD伝
送ゲートCH2外側に設けられる第3のCCD伝送ゲー
トCH3と;上記第3の移転ゲートTCと上記第2のC
CD伝送ゲートCH2との間に設けられる第1の垂直C
CD伝送ゲートCVAと;上記第2のCCD伝送ゲート
CH2と上記第3のCCD伝送ゲートCH3との間に設
けられる第2の垂直CCD伝送ゲートCVBと;で形成
され、そして、上記第1の誘導画素SA0が光の激発を
受けて誘導した信号を、上記第1の移転ゲートTAから
上記第1のCCD伝送ゲートCH1に伝送して、更に順
に水平方向に第1の出力ポートO1 に伝送されて出力
し;上記第3の誘導画素SC0が誘導した信号を、第3
の移転ゲートTCから第1の垂直CCD伝送ゲートCV
A、第2のCCD伝送ゲートCH2、第2の垂直CCD
伝送ゲートCVBを経て第3のCCD伝送ゲートCH3
に伝送し、更に順に水平方向に第3の出力ポートO3
伝送されて出力し;上記第2の誘導画素SB0が誘導し
た信号を、上記第3の誘導画素SC0がその誘導した信
号を伝送し終わった後、上記第2の移転ゲートTBから
上記第3の誘導画素SC0、第3の移転ゲートTC、第
1の垂直CCD伝送ゲートCVAを経て第2のCCD伝
送ゲートCH2に伝送し、更に順に水平方向に第2の出
力ポートO2 に伝送されて出力する;ように構成され
る。
In order to achieve the above object, the present invention provides a first guide pixel SA0 and a first guide pixel SA0 which are arranged in close proximity to one side of the first guide pixel SA0 with an appropriate insulation distance. Second guiding pixel SB0; and the second guiding pixel S
B0 Third induction pixel SC0 arranged in the vicinity of the other side
A first transfer gate TA provided near the other side of the first guide pixel SA0, and a second guide pixel SB0
And a third transfer gate TB interposed between the third transfer pixel SC0 and the third transfer pixel SC0; a third transfer gate TC provided close to the other side of the third transfer pixel SC0; and the first transfer gate TC. A first CCD transmission gate CH1 provided outside the transfer gate TA; a second CCD transmission gate CH2 provided outside the third transfer gate TC; a third CCD provided outside the second CCD transmission gate CH2 CCD transfer gate CH3; the third transfer gate TC and the second C
The first vertical C provided between the CD transmission gate CH2
A CD transfer gate CVA; a second vertical CCD transfer gate CVB provided between the second CCD transfer gate CH2 and the third CCD transfer gate CH3; and the first lead. A signal induced by the pixel SA0 in response to the sudden emission of light is transmitted from the first transfer gate TA to the first CCD transmission gate CH1 and further horizontally in sequence to the first output port O 1. And output the signal induced by the third inductive pixel SC0.
Transfer gate TC to first vertical CCD transmission gate CV
A, second CCD transmission gate CH2, second vertical CCD
The third CCD transmission gate CH3 via the transmission gate CVB
To the third output port O 3 and then to the third output port O 3 in order to output the signal induced by the second induction pixel SB0, and the signal induced by the third induction pixel SC0. After that, the data is transmitted from the second transfer gate TB to the second CCD transfer gate CH2 via the third inductive pixel SC0, the third transfer gate TC, the first vertical CCD transfer gate CVA, and further. The data are sequentially transmitted in the horizontal direction to the second output port O 2 and output.

【0006】また、上記第2の誘導画素SB0が正孔時
において、その電子電位が第3の誘導画素SC0の電子
電位より高くなるようにし、並びに上記第2及び第3の
誘導画素SB0,SC0をPNP型に形成し、かつ製造
過程において、該第2の誘導素SB0上面のP型層の不
純物濃度を、該第3の誘導画素SC0上面のP型層の不
純物濃度より高くすれば一層好ましくなる。
When the second induction pixel SB0 has holes, the electron potential of the second induction pixel SB0 is higher than the electron potential of the third induction pixel SC0, and the second and third induction pixels SB0 and SC0. It is more preferable that the P type is formed and the impurity concentration of the P type layer on the upper surface of the second inductor SB0 is higher than the impurity concentration of the P type layer on the upper surface of the third induction pixel SC0 in the manufacturing process. Become.

【0007】[0007]

【作用】上記のように構成された、本発明は、それぞれ
CCD伝送ゲートCH1,CH2,CH3はもはや三つ
の誘導画素SA0,SB0,SC0のそれぞれ間隔空間
に介装排列されずに、三つの誘導画素SA0,SB0,
SC0は互いに緊密に排列されて、完璧な誘導面積を確
保しており、そのうち、該第1の誘導画素SA0が誘導
した信号は、第1の移転ゲートTAにより電荷を第1の
CCD伝送ゲートCH1に伝送して、更に順に水平方向
に伝送して第1の出力ポートO1 より出力する;また、
該第3の誘導画素SC0が誘導した信号は、第3の移転
ゲートTCより第1の垂直CCD伝送ゲートCVA、第
2のCCD伝送ゲートCH2、第2の垂直CCD伝送ゲ
ートCVBを経て第3のCCD伝送ゲートCH3に伝送
され、順に水平方向に伝送して第3の出力ポートO3
り出力する:更に、該第2の誘導画素SB0が誘導した
信号は、第3の誘導画素SC0がその誘導した信号を完
全送出した後、第2の移転ゲートTB、第3の誘導画素
SC0、第3の移転ゲートTC、第1の垂直伝送ゲート
CVAを経て第2のCCD伝送ゲートCH2に伝送さ
れ、更に水平方向に伝送して第2の出力ポートO2 より
出力する。
According to the present invention having the above-described structure, the CCD transmission gates CH1, CH2 and CH3 are no longer inserted and arranged in the space of the three induction pixels SA0, SB0 and SC0, respectively. Pixels SA0, SB0,
SC0s are arranged closely to each other to ensure a perfect induction area. Among them, the signal induced by the first induction pixel SA0 is charged by the first transfer gate TA to the first CCD transmission gate CH1. To the first output port O 1 and further in the horizontal direction to output from the first output port O 1 .
The signal induced by the third induction pixel SC0 is transmitted from the third transfer gate TC to the third vertical CCD transmission gate CVA, the second vertical CCD transmission gate CH2, and the second vertical CCD transmission gate CVB. is transmitted to the CCD transfer gates CH3, turn horizontally is output from the third output port O 3 by transmission: Moreover, the signal, the third induction pixels SC0 is induced its induction pixel SB0 the second-induced After being completely transmitted, the signal is transmitted to the second CCD transmission gate CH2 via the second transfer gate TB, the third inductive pixel SC0, the third transfer gate TC, the first vertical transmission gate CVA, and further. The signal is transmitted in the horizontal direction and output from the second output port O 2 .

【0008】そして、上記第2の誘導画素SB0が正孔
時において、その電子電位が第3の誘導画素SC0の電
子電位より高くなるようにし、並びに上記第2及び第3
の誘導画素SB0,SC0をPNP型に形成し、かつ製
造過程において、該第2の誘導画素SB0上面のP型層
の不純物濃度を、該第3の誘導画素SC0上面のP型層
の不純物濃度より高くしているので、第3の誘導画素S
C0が誘導した信号を伝送完了すると、第2の誘導画素
SB0が誘導した信号が該第3の誘導画素SC0により
移転伝送することができる。
Then, when the second induction pixel SB0 has a hole, the electron potential of the second induction pixel SB0 is made higher than the electron potential of the third induction pixel SC0, and the second and third pixels are provided.
Of the induction pixels SB0 and SC0 of PNP type, and in the manufacturing process, the impurity concentration of the P-type layer on the upper surface of the second induction pixel SB0 is changed to the impurity concentration of the P-type layer on the upper surface of the third induction pixel SC0. Since it is higher, the third induction pixel S
When the transmission of the signal induced by C0 is completed, the signal induced by the second induction pixel SB0 can be transferred and transmitted by the third induction pixel SC0.

【0009】この発明の上記またはその他の目的、特徴
および利点は、図面を参照して以下の実施例の詳細な説
明から一層明らかとなろう。
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

【0010】[0010]

【実施例】図1に示す如く、本発明の電荷結合素子イメ
ージセンサは、第1の誘導画素SA0、第2の誘導画素
SB0、第3の誘導画素SC0、第1の移転ゲートT
A、第2の移転ゲートTB、第3の移転ゲートTC、第
1のCCD伝送ゲートCH1、第2のCCD伝送ゲート
CH2、第3のCCD伝送ゲートCH3、第1の垂直C
CD伝送ゲートCVA、第2の垂直CCD伝送ゲートC
VBによって構成され;そのうち、該第1の誘導画素S
A0は第2の誘導画素SB0と近接に排列され、該第2
の誘導画素SB0は第3の誘導画素SC0との間に極め
て細い第2の移転ゲートTBを介装されるのみで、該第
1の誘導画素SA0はその他側に近接して第1の移転ゲ
ートTA、及び該第1の移転ゲートTAに近接して第1
のCCD伝送ゲートCH1をそれぞれ設けており、該第
1のCCD伝送ゲートCH1は第1の出力ポートO1
備え付けられる。一方、該第3の誘導画素SC0はその
他側に近接して第3の移転ゲートTC、及び該第3の移
転ゲートTCに近接して第1の垂直CCD伝送ゲートC
VA、及び該第1の垂直CCD伝送ゲートCVAに近接
して第2のCCD伝送ゲートCH2、更に順に、該第2
のCCD伝送ゲートCH2に第2の垂直CCD伝送ゲー
トCVB、該第2の垂直CCD伝送ゲートCVBに第3
のCCD伝送ゲートCH3を近接して設け、かつ該第2
のCCD伝送ゲートCH2の出力ポートO2 、該第3の
CCD伝送ゲートCH3の出力ポートO3 をそれぞれ設
ける。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, a charge coupled device image sensor of the present invention comprises a first induction pixel SA0, a second induction pixel SB0, a third induction pixel SC0 and a first transfer gate T.
A, second transfer gate TB, third transfer gate TC, first CCD transmission gate CH1, second CCD transmission gate CH2, third CCD transmission gate CH3, first vertical C
CD transmission gate CVA, second vertical CCD transmission gate C
VB; of which the first guiding pixel S
A0 is arranged in the vicinity of the second induction pixel SB0 and
The guiding pixel SB0 of the first guiding pixel SA0 is only provided with a very thin second transfer gate TB between itself and the third guiding pixel SC0. TA and a first transfer gate TA in close proximity to the first transfer gate TA
CCD transmission gates CH1 are provided respectively, and the first CCD transmission gates CH1 are equipped with a first output port O 1 . On the other hand, the third induction pixel SC0 is adjacent to the other side, and the third transfer gate TC is adjacent to the third transfer gate TC, and the first vertical CCD transmission gate C is adjacent to the third transfer gate TC.
VA and a second CCD transmission gate CH2 in the vicinity of the first vertical CCD transmission gate CVA, and further in the order of the second CCD transmission gate CH2.
To the second vertical CCD transmission gate CVB, and the third vertical CCD transmission gate CVB to the second vertical CCD transmission gate CVB.
The CCD transmission gate CH3 of the
Providing an output port O 2 of the CCD transfer gates CH2, an output port O 3 of the CCD transfer gates CH3 of the third, respectively.

【0011】上記の構造から分かるように、それぞれC
CD伝送ゲートCH1,CH2,CH3はもはや三つの
誘導画素SA0,SB0,SC0のそれぞれ間隔空間に
介装排列されないで、三つの誘導画素SA0,SB0,
SC0は互いに緊密に排列され、並びに完璧な誘導面積
を確保しており、そのうち、該第1の誘導画素SA0が
感応した信号は、第1の移転ゲートTAにより電荷を第
1のCCD伝送ゲートCH1に伝送し、更に順に水平方
向に伝送して第1の出力ポートO1 より出力する;一
方、該第3の誘導画素SC0が感応した信号は、第3の
移転ゲートTCより第1の垂直CCD伝送ゲートCV
A、第2のCCD伝送ゲートCH2、第2の垂直CCD
伝送ゲートCVBを経て第3のCCD伝送ゲートCH3
に伝送され、順に水平方向に伝送して第3の出力ポート
3 より出力する:そして、該第2の誘導画素SB0が
感応した信号は、第3の誘導画素SC0がその感応した
信号を送出したのを待ってから、第2の移転ゲートT
B、第3の誘導画素SC0、第3の移転ゲートTC、第
1の垂直伝送ゲートCVAを経て第2のCCD伝送ゲー
トCH2に伝送され、更に水平方向に伝送して第2の出
力ポートO2 より出力するのである。
As can be seen from the above structure, each C
The CD transmission gates CH1, CH2, and CH3 are no longer arranged in the space of the three guide pixels SA0, SB0, and SC0, but the three guide pixels SA0, SB0, and
SC0s are arranged closely to each other and ensure a perfect induction area. Among them, the signal sensed by the first induction pixel SA0 causes the first transfer gate TA to charge the first CCD transmission gate CH1. To the first output port O 1 and then to the first output port O 1 ; on the other hand, the signal sensed by the third inductive pixel SC0 is transmitted from the third transfer gate TC to the first vertical CCD. Transmission gate CV
A, second CCD transmission gate CH2, second vertical CCD
The third CCD transmission gate CH3 via the transmission gate CVB
It is transmitted to turn horizontally to the output from the third output port O 3 by transmission: The signal induced pixels SB0 the second is sensitive, the third induction pixels SC0 is sends the sensing signal After waiting for the second transfer gate T
B, the third inductive pixel SC0, the third transfer gate TC, the first vertical transmission gate CVA, the second CCD transmission gate CH2, and the second horizontal transmission to the second output port O 2. Output more.

【0012】このように、本発明の構造を実行させるに
最も重要なことは、如何にして第3の誘導画素SC0を
して第2の誘導画素SB0の誘導電荷を移転させるかの
点にあって、その他信号の出力処理は単なる使用システ
ムに配設されたソフトウェアであり、本発明の特徴に属
さないので説明を省き、次に本発明の特徴である実行方
法を説明する。
Thus, the most important factor in implementing the structure of the present invention is how to transfer the induced charge of the second induction pixel SB0 to the third induction pixel SC0. The output processing of other signals is simply software installed in the system used and does not belong to the feature of the present invention, so the description thereof will be omitted. Next, the execution method which is the feature of the present invention will be described.

【0013】図2に示すのは、本発明における各誘導画
素の横断面表示図で、図中の(a)に示す如く、該三つ
の誘導画素SA0,SB0,SC0の構造は皆PNP型
に構成され、かつ各感応画素の表面P型中のPA,P
B,PCとその底層P型中のPA’,PB’,PC’は
共に接地電位で、それぞれ中間層のN型中のNA
B,NC は浮動状態に接合されて誘導電荷を貯存し、
そして、電荷が伝送されると該N型層は正孔となって正
電位を帯びる。
FIG. 2 is a cross-sectional view of each of the inductive pixels according to the present invention. As shown in FIG. 2A, the three inductive pixels SA0, SB0 and SC0 are all of the PNP type. PA and P in the surface P-type of each sensitive pixel constructed
B, PC and PA ', PB', PC 'in the bottom P-type are both at ground potential, and N A in the N-type in the intermediate layer,
N B and N C are joined in a floating state to store the induced charge,
Then, when the charge is transmitted, the N-type layer becomes a hole and has a positive potential.

【0014】そして、本発明の特徴は、中央に位置する
第2の誘導画素SB0上面のP型層PBを比較的高いP
型不純物濃度(通常、二次植込みを可とす)で植込み、
そして、第3の誘導画素SC0上面のP型層PCのP型
不純物濃度を低く(通常、一次のみ植込みを可とす)し
て、正孔の際、該第2の誘導画素SB0における電子電
位が該第3の誘導画素SC0に相対して高くなるように
し、そして、該第2の誘導画素SB0と第3の誘導画素
SC0がともに光の激発を受けて、誘導電荷(図中の
(b)に示す如く)を累積し且つ電荷を伝送すると、第
3の移転ゲートTCが先ず開いて、該第3の誘導画素S
C0の誘導電荷を上記の動作方式(図中の(C)に示す
ように)のように垂直に伝送し、また、図中(d)に示
す如く、該第3の誘導画素SC0の電荷を伝送する過程
において、該第3の移転ゲートTCが再び閉鎖して、最
後に、該第3の誘導画素SC0の電荷が伝送完了される
と、該第2の移転ゲートTBと第3の移転ゲートTCが
同時に開いて、図中(e)に示す如く、第2の誘導画素
SB0の電荷が先ず電子電位低い第3の誘導画素SC0
に伝送され、更に、上記伝送方式と同様なステップをた
どって伝送され得る。
A feature of the present invention is that the P-type layer PB on the upper surface of the second induction pixel SB0 located at the center has a relatively high P.
Type impurity concentration (usually secondary implantation is possible),
Then, the P-type impurity concentration of the P-type layer PC on the upper surface of the third induction pixel SC0 is lowered (normally, only the primary implantation is allowed), and at the time of holes, the electron potential in the second induction pixel SB0. Is made relatively high with respect to the third induction pixel SC0, and the second induction pixel SB0 and the third induction pixel SC0 are both exposed to light to generate an induction charge ((b in the figure). ) And transmitting the charge, the third transfer gate TC first opens and the third inductive pixel S
The induced charge of C0 is vertically transmitted as in the above operation method (as shown in (C) in the figure), and as shown in (d) in the figure, the charge of the third induced pixel SC0 is changed. In the process of transmitting, the third transfer gate TC is closed again, and finally, when the charge of the third inductive pixel SC0 is completely transferred, the second transfer gate TB and the third transfer gate TC are transferred. TC is opened at the same time, and as shown in (e) in the figure, the charge of the second induction pixel SB0 is the third induction pixel SC0 whose electron potential is first low.
Then, the data can be transmitted by following the same steps as in the above transmission method.

【0015】[0015]

【発明の効果】上記のように構成された、本発明は、そ
れぞれCCD伝送ゲートCH1,CH2,Cは3を三つ
の誘導画素SA0,SB0,SC0のそれぞれ間隔空間
に介装排列しないで、三つの誘導画素SA0,SB0,
SC0が互いに緊密に排列し、しかも完璧な誘導面積を
確保しているので、各誘導画素の間隔距離が近く、光走
査の際、各誘導画素の誘導信号伝送に時間のずれがな
く、従って、ソフトウェアの処理時間を節減してシステ
ムの機能を向上し、且つハードウェアを増設する必要が
ないのでハードウェア設置コストを節減し、使用システ
ムの体積を縮小し得る。
According to the present invention configured as described above, the CCD transmission gates CH1, CH2 and C do not have 3 arranged in the space of the three induction pixels SA0, SB0 and SC0, respectively. One guiding pixel SA0, SB0,
Since the SC0s are arranged closely to each other and secure a perfect guide area, the distance between the guide pixels is short and there is no time lag in the guide signal transmission of each guide pixel during optical scanning. It is possible to reduce the processing time of software and improve the function of the system, and also to reduce the hardware installation cost and the volume of the system used because there is no need to add hardware.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の構造図である。FIG. 1 is a structural diagram of the present invention.

【図2】本発明における誘導電荷伝送態様の横断面表示
図である。
FIG. 2 is a cross-sectional view showing an induced charge transfer mode according to the present invention.

【図3】従来のCCDIS構造図である。FIG. 3 is a conventional CCDIS structure diagram.

【図4】他の従来のCCDIS構造図である。FIG. 4 is another conventional CCDIS structure diagram.

【図5】従来の面型CCDIS構造図である。FIG. 5 is a structure diagram of a conventional surface-type CCDIS.

【符号の説明】[Explanation of symbols]

SA0 第1の誘導画素 SB0 第2の誘導画素 SC0 第3の誘導画素 TA 第1の移転ゲート TB 第2の移転ゲート TC 第3の移転ゲート CH1 第1のCCD伝送ゲート CH2 第2のCCD伝送ゲート CH3 第3のCCD伝送ゲート CVA 第1の垂直CCD伝送ゲート CVB 第2の垂直CCD伝送ゲート O1 第1の出力ポート O2 第2の出力ポート O3 第3の出力ポートSA0 First guide pixel SB0 Second guide pixel SC0 Third guide pixel TA First transfer gate TB Second transfer gate TC Third transfer gate CH1 First CCD transmission gate CH2 Second CCD transmission gate CH3 Third CCD transmission gate CVA First vertical CCD transmission gate CVB Second vertical CCD transmission gate O 1 First output port O 2 Second output port O 3 Third output port

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 第1の誘導画素(SA0)と;上記第1
の誘導画素(SA0)片側に適当な絶縁間隔を保って近
接して排列される第2の誘導画素(SB0)と;上記第
2の誘導画素(SB0)他側に近接して排列される第3
の誘導画素(SC0)と;上記第1の誘導画素(SA
0)他側に近接して設けられる第1の移転ゲート(T
A)と;上記第2の誘導画素(SB0)及び第3の誘導
画素(SC0)との間に介装される第2の移転ゲート
(TB)と;上記第3の誘導画素(SC0)他側に近接
して設けられる第3の移転ゲート(TC)と;上記第1
の移転ゲート(TA)外側に設けられる第1のCCD伝
送ゲート(CH1)と;上記第3の移転ゲート(TC)
外側に設けられる第2のCCD伝送ゲート(CH2)
と;上記第2のCCD伝送ゲート(CH2)外側に設け
られる第3のCCD伝送ゲート(CH3)と;上記第3
の移転ゲート(TC)と上記第2のCCD伝送ゲート
(CH2)との間に設けられる第1の垂直CCD伝送ゲ
ート(CVA)と;上記第2のCCD伝送ゲート(CH
2)と上記第3のCCD伝送ゲート(CH3)との間に
設けられる第2の垂直CCD伝送ゲート(CVB)と;
で形成してなる線形カラー電荷結合素子イメージセン
サ。
1. A first guide pixel (SA0); and the first guide pixel (SA0).
Of the second guide pixel (SA0) and the second guide pixel (SB0) arranged in close proximity to one side of the second guide pixel (SA0) with an appropriate insulation interval; Three
Of the first induction pixel (SA);
0) The first transfer gate (T
A) ;; a second transfer gate (TB) interposed between the second induction pixel (SB0) and the third induction pixel (SC0); and the third induction pixel (SC0) and others. A third transfer gate (TC) provided close to the side;
A first CCD transmission gate (CH1) provided outside the transfer gate (TA) of the third transfer gate (TC);
Second CCD transmission gate (CH2) provided outside
And a third CCD transmission gate (CH3) provided outside the second CCD transmission gate (CH2);
A first vertical CCD transmission gate (CVA) provided between the transfer gate (TC) of the second CCD transmission gate (CH) and the second CCD transmission gate (CH2);
A second vertical CCD transmission gate (CVB) provided between 2) and the third CCD transmission gate (CH3);
A linear color charge-coupled device image sensor formed by.
【請求項2】 上記第1の誘導画素(SA0)の光が激
発を受けて誘導した信号を、上記第1の移転ゲート(T
A)から上記第1のCCD伝送ゲート(CH1)に伝送
して、更に順に水平方向に第1の出力ポート(O1 )に
伝送されて出力し;上記第3の誘導画素(SC0)が誘
導した信号を、第3の移転ゲート(TC)から第1の垂
直CCD伝送ゲート(CVA)、第2のCCD伝送ゲー
ト(CH2)、第2の垂直CCD伝送ゲート(CVB)
を経て第3のCCD伝送ゲート(CH3)に伝送し、更
に順に水平方向に第3の出力ポート(O3 )に伝送され
て出力し;上記第2の誘導画素(SB0)が誘導した信
号を、上記第3の誘導画素(SC0)がその誘導した信
号を伝送し終わった後、上記第2の移転ゲート(TB)
から上記第3の誘導画素(SC0)、第3の移転ゲート
(TC)、第1の垂直CCD伝送ゲート(CVA)を経
て第2のCCD伝送ゲート(CH2)に伝送し、更に順
に水平方向に第2の出力ポート(O2 )に伝送されて出
力する;ようにしてなる線形カラー電荷結合素子イメー
ジセンサ実行方法。
2. The signal transferred from the first guiding pixel (SA0) when the light is rapidly emitted and is guided to the first transfer gate (T).
A) to the first CCD transmission gate (CH1), and then horizontally in order to the first output port (O 1 ) for output; the third induction pixel (SC0) induces The transferred signal is transferred from the third transfer gate (TC) to the first vertical CCD transmission gate (CVA), the second CCD transmission gate (CH2), and the second vertical CCD transmission gate (CVB).
Said second signal derived pixel (SB0) was induced; transmitted to the third CCD transfer gates (CH3) via the further third are transmitted and outputs the output to the port (O 3) in the horizontal direction in this order , The second transfer gate (TB) after the third guiding pixel (SC0) has finished transmitting its guided signal.
From the third inductive pixel (SC0), the third transfer gate (TC), the first vertical CCD transmission gate (CVA) to the second CCD transmission gate (CH2), and further in the horizontal direction. A method of implementing a linear color charge-coupled device image sensor, comprising: transmitting to a second output port (O 2 ) for output;
【請求項3】 上記第2の誘導画素(SB0)が電子空
白時において、その電子電位が第3の誘導画素(SC
0)の電子電位より高くなるようにしてなる請求項1記
載の線形カラー電荷結合素子イメージセンサ。
3. When the second induction pixel (SB0) has an electron blank, the electron potential of the second induction pixel (SB0) is the third induction pixel (SC).
2. The linear color charge coupled device image sensor according to claim 1, wherein the electron potential is higher than the electron potential of 0).
【請求項4】 上記第2及び第3の誘導画素(SB0,
SC0)をPNP型に形成し、かつ製造過程において、
該第2の誘導画素(SB0)上面のP型層の植込み濃度
を、該第3の誘導画素(SC0)上面のP型層の植込み
濃度より高くしてなる請求項1または3記載の線形カラ
ー電荷結合素子イメージセンサ。
4. The second and third induction pixels (SB0,
SC0) is formed into PNP type, and in the manufacturing process,
The linear color according to claim 1 or 3, wherein the implantation density of the P-type layer on the upper surface of the second induction pixel (SB0) is higher than the implantation density of the P-type layer on the upper surface of the third induction pixel (SC0). Charge coupled device image sensor.
JP4054906A 1992-03-13 1992-03-13 Linear color charge coupled device image sensor and charge transfer method thereof Expired - Fee Related JP2909789B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4054906A JP2909789B2 (en) 1992-03-13 1992-03-13 Linear color charge coupled device image sensor and charge transfer method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4054906A JP2909789B2 (en) 1992-03-13 1992-03-13 Linear color charge coupled device image sensor and charge transfer method thereof

Publications (2)

Publication Number Publication Date
JPH06169465A true JPH06169465A (en) 1994-06-14
JP2909789B2 JP2909789B2 (en) 1999-06-23

Family

ID=12983650

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2909789B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63191467A (en) * 1986-12-18 1988-08-08 ゼロックス コーポレーション Sensor array for color image scanner

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63191467A (en) * 1986-12-18 1988-08-08 ゼロックス コーポレーション Sensor array for color image scanner

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