JPH0616855U - Multi CPU line sensor controller - Google Patents

Abstract

(57) [Summary] [Purpose] A line sensor that can inspect many rows of products at high speed at low cost or can inspect many inspection items of one row of products at high speed. Provide a controller. [Structure] A plurality of slave CPUs 20, 21, 22, and 23 share and process a line image generated by one line sensor camera 11. At this time, binarization is performed by using a different reference value for each slave CPU, and determination is performed by using different determination criteria. In addition, the same line image is sent to a plurality of slave CPUs, and 2 is set according to a different reference value for each CPU.
The value is converted and the judgment is made according to different judgment criteria. Accordingly, it is possible to process a plurality of inspection objects at the same time or a plurality of inspection items for one determination object at the same time.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a line sensor controller used in an apparatus for inspecting and sorting products flowing in a line.

[0002]

[Prior art]

 In a line for manufacturing a large number of products, it is often the case that one belt is divided into a plurality of rows and the products are flowed to each row or a plurality of belts to increase the production speed. When the size and appearance of products flowing through such a line are to be inspected (scratches, stains, shapes, presence or absence of products, etc.), conventionally, for example, as shown in FIG. Only the line sensor camera 11 and one controller (not shown) are used, and the CPU of the controller processes the images captured by the camera 11 serially in time, or when high speed processing is required The same number of cameras and controllers as the number of 33 (six in the example of FIG. 3) were provided, and image processing was performed completely in parallel.

Even when the product 50 does not flow in a plurality of rows in parallel as described above but the product 50 flows in a single row as shown in FIG. 5, when there are a plurality of inspection items, for example, When it is necessary to inspect scratches, stains, etc. 51, 52, 53 at the same time when inspecting, for the image taken by one line sensor camera 54, one controller is serially arranged in time for each inspection item. Image processing was performed.

[0004]

[Problems to be solved by the device]

 However, in the case of an inspection line in which products flow in multiple rows as shown in FIG. 3, the number of products is extremely large and the number of product rows 33 that flow simultaneously is increased by processing with only one camera 11 and one controller. When the number of data becomes extremely large, the amount of data processing that one CPU has to process increases by the number of columns (n times), so the processing speed becomes 1 / n, and reliable inspection must be performed. Will be difficult. Further, when high-speed processing is required, the cameras 11 and controllers for the number of columns are required, but this is often difficult in terms of cost. As shown in FIG. 5, the products 50 flow in a single row, but this is also the case when there are many inspection items, and as the number of items to be inspected increases, the moving speed of the products 50 must be reduced. The inspection process becomes a bottleneck, which significantly impedes productivity.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the cost and to inspect a large number of rows of products at high speed. An object of the present invention is to provide a line sensor controller capable of inspecting a large number of inspection items of products in one row at high speed.

[0006]

[Means for Solving the Problems]

 A multi-CPU line sensor controller according to the present invention, which is made to solve the above-mentioned problems, comprises a) one line sensor camera, and b) the address of each pixel of a line image captured by the line sensor camera. A timing circuit that generates an address signal, and c) a plurality of slave CPUs that perform image processing by capturing a specified part of the line image taken by the line sensor camera based on the address signal, and d) 1 unit Master CPU of the above, e) a video data bus connecting the line sensor camera, all slave CPUs and the master CPU, and f) a video address bus connecting the line sensor camera, timing circuit, all the slave CPUs and the master CPU, g) a control bus connecting the master CPU and all slave CPUs, and h) all slave CPUs. And a determination result signal bus for connecting the master CPU.

[0007]

Operation The line sensor camera photographs the inspection object or the like, and the generated line image data is sent to the video data bus. At the same time, the data of the address of each pixel of the line image is sent from the timing circuit to the video address bus as an address signal. Each slave CPU fetches only video data within an address range set by the master CPU (a preset value may be set for each slave CPU as described later), and performs image processing and determination. Do. The contents of this image processing and determination can be set individually by the master CPU for each slave CPU through the control bus, or can be set in advance for each slave. In each slave CPU, the judgment result is sent to the judgment result signal bus, and the master CPU inputs the judgment result to perform statistical processing and comprehensive judgment for many products.

It should be noted that the system of the present invention can be implemented in various modes other than this, which will be described in the following examples.

[0009]

【Example】

 As an embodiment of the present invention, a sorting apparatus for green beans (for example, kidney beans) will be described with reference to FIGS. 1 to 4. In this embodiment, as shown in FIG. 1, a system is constituted by n slave CPUs 20, 21, ..., 23, 24, and an image taken by one line sensor camera 11 is processed by n slave CPUs. 23, 24 are divided by the CPUs 20, 21, ..., 23, 24, and are processed in parallel. The system of this embodiment is composed of the following.

Line sensor camera 11: As shown in FIG. 3, shoots green beans 38 flowing in a plurality of rows 33 on a line. In FIG. 1, a reduction type using a lens is used, but a contact type can also be used. Timing circuit 13: Generates a clock control signal for operating the line sensor camera 11, a camera control signal such as a start signal, and a video address signal representing an address of each pixel forming a line image. Signal conditioning circuit 12: An amplifier section and an A / D conversion section for amplifying the image signal output from the line sensor camera 11 to a voltage having an appropriate amplitude. Besides, a noise filter may be provided if necessary.

Master CPU 14: Sets operation conditions and determination conditions of each slave CPU 20, 21, ..., 23, 24, and receives a determination result signal output from the slave CPUs 20, 21 ,. , Statistical processing and comprehensive judgment. In the master CPU 14, in addition to ROM and RAM, a secondary storage unit that is a battery-backed memory, a communication circuit for communicating programs and data with an external personal computer, etc., a display for displaying judgment results and data It is equipped with an external output circuit for transmitting circuits, judgment results and data to an external sequencer, etc., and outputting alarm signals to a buzzer, a lamp, etc., and an input circuit 15 for inputting an external inspection start signal, etc. . Further, the master CPU 14 is also provided with a switch for setting conditions.

Bus: a control bus 16 that connects the master CPU 14 and the slave CPUs 20, 21, ..., 23, 24, the timing circuit 13 and the signal conditioning circuit 12, and sends control signals of the master CPU 14 to each part; line sensor camera 11, a video data bus 18 for transmitting the image signal generated by 11 to each unit; a video address bus 17 for supplying a video address signal representing the address of the video data of each pixel to each unit; each slave CPU 20, 21, ..., 23, 24 Each bus of the determination result bus 19 for transmitting and receiving the determination result signal generated in 1. is provided.

Slave CPUs 20, 21, ..., 23, 24: As described above, n pieces are provided in this system. Based on the video address signal on the video address bus 17, each of the image signals from the line sensor camera 11 fetches a predetermined portion of the image signal. Then, image processing and determination are performed according to a standard set by the master CPU 14 or a standard predetermined for each slave CPU 20, 21, ..., 23, 24, and the determination result is sent to the determination result bus 19. The inside of each slave CPU 20, 21, ..., 23, 24 is as shown in FIG. 2, and is mainly composed of a central processing unit (CPU circuit) 25 for performing image processing and determination. The central processing unit 25 may be composed of individual CPU, ROM, and RAM chips, or may be a one-chip microcomputer in which these are mounted on one chip. In addition, the slave CPUs 20, 21, ..., 23, 24 receive control information (for example, operation, determination condition, etc.) from the master CPU 14, and master the operation status of the slave CPUs 20, 21 ,. The control I / F 28 for communicating with the CPU 14 compares the video address indicating the pixel position of the video data with the address range to be processed by each slave CPU 20, 21, ..., 23, 24 designated by the master CPU 14. If it is within the range, the video address comparison circuit 26 that generates a clock or the like necessary to capture the video data and the video data that is synchronized with the clock or the like generated by the video address comparison circuit 26 is binarized to change the brightness. Change point is detected, and the address of the change point is written in the video data memory 29. The video processing circuit 27 having a built-in control device function, the judgment output unit 30 for returning the judgment result to the master CPU, and the slave CPUs 20, 21, ..., 23, 24 directly exchange data with external devices. External input / output circuit 31.

In addition, the instruction of the video address and the instruction of the determination method are not the setting from the master CPU 14 but the slave CPUs 20, 21, ... It can be set by a switch provided for each 24 or can be written in advance in the ROMs of the slave CPUs 20, 21, ..., 23, 24. In such a case, the master CPU 14 may not be provided.

FIG. 3 shows a perspective view of a sorting line for the bean beans in which the sorting apparatus of this embodiment is installed. The bean 38 to be inspected is flown on a belt divided into 6 rows, one belt is finished, and above and below the gap 37 between the two belts where the bean 38 transfers to the next belt, A line sensor camera 11 and a light source 36 are provided. Instead of using the gap 37 between the belts as described above, it is possible to photograph the beans falling at the end of the belt, and a light source and a line sensor camera are provided on the upper part of one belt to reflect light. You may make it photograph a green bean by light.

As shown in FIG. 4A, the image captured by the line sensor camera 11 is generally darker in the peripheral portion than in the central portion due to the unevenness of the light source and the peripheral dimming phenomenon of the lens. If all the parts are binarized with a constant threshold value as shown by 40, an error may occur in the value of the width of the bean and the SN ratio may differ for each row. Therefore, as shown by the line 41 in FIG. 4B, by adding a shading correction that changes the threshold value for each column, the error in the width measurement value and the SN ratio variation are corrected, and the measurement condition of each column is corrected. Is corrected to correctly determine the width of each pod.

Further, there is an error due to the distortion distortion that the lens has at the peripheral portion and the central portion, and in the case of a sorting apparatus that requires accurate judgment, it is possible to perform stepwise correction by the pixel position in consideration of the distortion distortion. Although required, this calculation is very complex. Therefore, if such a correction is attempted to be processed by one CPU over the entire area of the image, it takes a very long time and it may not be possible to carry out a quick sorting process. Therefore, such correction is entrusted to each slave CPU to enable quick processing. Further, as shown in FIG. 3, when a partition plate 34 is provided between each row 33 of the belts, the image of the partition plate 34 is not necessary for the image processing of the bean beans. It must be removed in advance before image processing and judgment. Also in this case, one CPU is a heavy burden to perform such processing, but when the line image is pre-assigned to each slave CPU 20, 21, ..., 23, 24, the address setting is appropriately performed. By performing the processing, each image can be easily removed when the slave CPUs 20, 21, ..., 23, 24 read. The middle part of FIG. 4 (b) illustrates the address area 42 in each line image, which the slave CPUs 20, 21, ..., 23, 24 are in charge of. It is a part corresponding to the plate 34. In this embodiment, the data in the shaded area is not taken into any of the slave CPUs 20, 21, ..., 23, 24 when the line image is divided, and is ignored. As a result, the width of the bean in each row 33 is correctly detected as shown in the graph 43.

As another embodiment of the present invention, an inspection apparatus for a gray sheet-like product 50 will be described with reference to FIG. In this embodiment, the inspection object 50 flows in one line instead of a plurality of lines. However, three types of the external shape (including the tear 53), the whitish deposit 51 on the surface and the blackish deposit 52 are simultaneously inspected. There is a need to. In the conventional line sensor controller, when binarizing the image data, generally only one threshold value can be set, and it is speed and cost to process judgment of three kinds of brightness with one controller. It was difficult from the point. For this reason, three cameras are arranged at positions above the inspection object flowing through the line, and processing is performed by the controllers (that is, a total of three controllers) provided for each of them.

On the other hand, in the inspection apparatus according to the present embodiment, the same line image is supplied to each of the three slave CPUs (that is, the assigned video address range of each slave CPU is the same), and the three slave CPUs. The CPU performs binarization by using different threshold values, and makes a determination by using different determination criteria. That is, as shown in the graph at the top of FIG. 6, in the first slave CPU, in order to inspect the outer shape of the sheet-like inspection object having the intermediate brightness and the shape defects such as holes and tears 53, the one-dot chain line The line image is binarized depending on whether it falls within the range of the two thresholds shown in or outside the range. The second slave CPU performs binarization within or outside the two threshold values shown by the dotted line in order to inspect the dirt and the adhered matter 51 brighter than the normal surface of the inspection object. Then, the third slave CPU performs binarization within the range of two threshold values shown by the chain double-dashed line in order to inspect the dirt and the adhered matter 52 darker than the normal surface of the inspection object. In this way, since the three slave CPUs perform binarization at the same time with different standards, as shown in the lower graph of FIG. The 51 and the dark stain 52 can be surely distinguished from each other and detected, and three types of inspection can be performed simultaneously at high speed and at low cost.

[0020]

[Effect of device]

 The present invention has been described with reference to the two embodiments, but in any case, when a plurality of cameras and a controller are provided, it is necessary to perform adjustment between the cameras, a timing circuit for each controller, Hardware such as signal conditioning circuit is required. In addition, if one controller divides into multiple parts and tries to make judgments based on multiple standards, the program becomes complicated, and program development and operation (modification), etc., will increase as the number of divisions and standard number increases. It quickly becomes difficult. On the other hand, when processing is performed by a plurality of slave CPUs as in the present invention, it is only necessary to develop one program common to all slave CPUs and use it for all slave CPUs. Each slave CPU need only change the parameters given to the program. In addition, a circuit that can be configured by purely a digital IC such as a slave CPU does not require time-consuming adjustment, and the inspection process becomes very easy. Further, the slave CPU can be manufactured at low cost by using the one-chip CPU or the gate array in which the peripheral components are incorporated, and the cost of the device can be kept low even if a large number of slave CPUs are used. Note that not only the line sensor controller but also the two-dimensional video camera controller can form a multi-CPU image processing device with a plurality of slave CPUs.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a multi-CPU line sensor controller used in the first and second embodiments of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a slave CPU.

FIG. 3 is a perspective view of a bean sorting apparatus according to the first embodiment.

FIG. 4 is a graph showing processing addresses and determination criteria of each slave CPU of the first embodiment.

FIG. 5 is a perspective view of a sheet inspection apparatus according to a second embodiment.

6A and 6B are graphs showing video data, determination criteria (reference range for binarization), and determination results in a shooting example of the second embodiment.

[Explanation of symbols]

11 ... Line sensor camera 12 ... Signal conditioning circuit 13 ... Timing circuit 14 ... Master CPU 15 ... Master CPU external input / output circuit 16 ... Control bus 17 ... Video address bus 18 ... Video data bus 19 ... Judgment result bus 20, 21, 22 , 23 ... Slave CPU 25 ... Central processing unit 26 ... Video address comparison circuit 27 ... Video processing circuit 28 ... Control I /
F 29 ... Video data memory 30 ... Judgment output section 31 ... External input / output circuit 33 ... Belt row 34 ... Partition plate 36 ... Light source 37 ... Gap 38 ... Inspection object (green beans) 50 ... Inspection object 51, 52 ... Attached matter 53 ... Rupture hole of inspection object 54 ... Line sensor camera

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location H04N 7/18 B // G06F 15/62 400 9287-5L

Claims (1)

[Scope of utility model registration request] 1. A) one line sensor camera, and b) each pixel of a line image captured by the line sensor camera.
Timing times to generate address signals that represent addresses
And c) Taken with line sensor camera based on address signal
Capture a specified part of the line image and perform image processing.
Multiple slave CPUs to perform, d) One master CPU, e) Line sensor camera, all slave CPUs and master
-Video data bus connecting CPU, f) Line sensor camera, timing circuit, all slaves
Video address bar to connect CPU and master CPU
And g) a system that connects the master CPU and all slave CPUs.
The master bus, and h) the judgment to connect all slave CPUs and master CPUs
A multi-CP having a constant result signal bus
U line sensor controller.