JPH06165157A - Motion detecting circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit size of a motion detecting circuit. CONSTITUTION:The picture element data al to ak of specific blocks in a current frame and the picture element data gl to gk of respective macro blocks in the preceding frame are supplied to picture element coincidence detectors 31A to 31N and upper (h) bits judged by a comparing bit length judging part 33 out of all bits of the data al to ak, gl to gk are respectively compared in each bit. Thereby the coincidence of the picture element data is decided. The numbers of coincident picture elements detected by the detectors 31A to 31N are supplied to a motion vector detecting part 32, which detects the macro block having the largest number of coincident picture elements and the coordinates of the macro block. A motion vector (v) is calculated based upon the coordinates. Since only the detection of coincidence between the picture element data of the current frame and that of the preceding frame is executed, the necessity of an adder, a product sum circuit, etc., can be eliminated, so that the circuit size can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motion detection circuit suitable for application to a predictive coding type image compression apparatus and the like.

[0002]

2. Description of the Related Art When transmitting a moving image such as a TV phone, the moving image is compressed and transmitted in order to efficiently use a communication line. A technique using a predictive coding method is known as such a moving image compression transmission technique. The predictive coding method is a data compression method using correlation, in which a current pixel is predicted from a previously coded past pixel and the prediction error is coded. For this predictive coding, one frame is divided into a plurality of blocks,
There is a method of encoding each block.

FIG. 6 shows a so-called inter-frame predictive coding circuit 10 for predicting data in the current frame from pixel data one frame before. In the figure, an input signal to be transmitted, for example, a video signal is supplied to an input terminal 11, and this is converted into a digital signal having a predetermined number of bits by an A / D conversion and raster / block conversion circuit 12, and the raster format is converted into a block format. Is converted to. This digitized video signal a is applied to the subtracter 13
And the difference from the predicted video signal b is taken, and the video signal of this difference is used as the prediction error signal c. Since the video signal a has a correlation, the prediction error signal c, which is the difference between the signal b predicted from the surrounding pixels one frame before and the predicted signal a, has a small value.

In the above example, the prediction error signal c is supplied to the discrete cosine transform (DCT) circuit 14. The prediction error signal (DCT coefficient) d subjected to the orthogonal transformation here is quantized by the quantization circuit 15. At this time, the portion that changes abruptly is quantized by utilizing the human visual characteristic that it is not noticeable even if it is roughly quantized. The data is compressed by the non-linear quantization that widens the width of the quantization step. The quantized prediction error signal e is
For example, the output terminal 1 is encoded by the variable length encoding circuit 16.
7 and the encoded signal f is transmitted to the outside.

Further, the prediction video signal b for forming the prediction error signal c is generated as follows. That is, the quantized prediction error signal e is first transmitted to the inverse quantization circuit 2
1 is inversely transformed into a prediction error signal d ′ before being quantized, and this is further transformed into an inverse / discrete cosine transform circuit (IDC).
T) 22 and is inversely converted to have the same signal format as the output of the subtractor 13. The inversely transformed prediction error signal c ′ is added to the prediction video signal b in the adder 23 and then supplied to the delay circuit 24 for one frame.

The video signal g delayed by one frame is supplied to the motion correction circuit 25 in a predetermined order under the control of the address control unit 27, and the motion compensation is performed according to the motion vector v to obtain the predicted video signal b. Is generated.
A motion detection circuit 26 performs the above-mentioned motion compensation by the motion vector v.

As a method for detecting the motion vector v, there are roughly two types of detection methods from the prior art. One of them is called a gradient method or a gradient method, which is a method that does not require transmission of the motion vector v. This method
It is used for scanning line conversion (standard conversion) etc., but the hardware tends to be large.

The other is CCITT (International Telegraph and Telephone Advisory Committee) Recommendation H.264. This is a block matching method adopted in H.261, which performs motion detection by dividing an image into a plurality of blocks and comparing pixels of corresponding blocks of a previous frame and a subsequent frame. In this block matching method, the motion vector v must be transmitted together with the compressed image, but the hardware can be configured relatively easily.

[0009]

By the way, in the detection of the motion vector v by the block matching method described above, the motion detection search range L is set in the motion detection frame as shown in FIG. Each of the N macro blocks M1, M2, ... MN of, for example, 16 dots × 16 dots set at a plurality of positions within the motion detection search range L, and a specific macro block Q in the reference frame, in this example, the current frame. And an appropriate evaluation function D (i,
j), and the macro block Mi closest to the specific macro block Q is detected.

The positional relationship between the macroblock Mi and the macroblock Q of the previous frame is represented by a vector, which is a motion vector v. Motion detection search range L
N macro blocks M1 to MN are set at positions shifted by one pixel or by a plurality of pixels.

Conventionally, as the above-mentioned evaluation function D (i, j), as shown in Expression 1, the pixel data Sf (k, 1) of the macroblock Q of the current frame and the macroblock M1 of the previous frame corresponding thereto are expressed. ~ MN pixel data S (f-
1) There is a method in which the absolute value sum of the difference from (k + i, 1 + j) is used. Then, it is determined that the macro block Mi for which the calculated evaluation function D (i, j) is the minimum is the moved image.

[0012]

[Equation 1]

Further, as shown in Equation 2, the pixel data Sf (k, 1) of the current frame and the pixel data S of the previous frame are
There is also a method in which the sum of squares of the difference from (f-1) (k + i, 1 + j) is used as the evaluation function D (i, j) and it is determined that the macroblock Mi having the smallest value is the macroblock after the movement.

[0014]

[Equation 2]

However, the sum of the absolute values of the differences is calculated by the evaluation function D.
When (i, j) is used, an adder circuit is required to calculate the sum of absolute values, and when the difference sum of squares is used as the evaluation function D (i, j), a product sum circuit is required. However, there is a problem that the circuit scale becomes very large. Further, since the pixel data is used as it is when comparing each pixel data of the previous frame and the current frame, the motion vector v may be erroneously detected when the input signal has a lot of noise.

Therefore, the present invention solves the above-mentioned problems, and can reduce the circuit scale, and can prevent erroneous detection of a motion vector even when there is much noise. A detection circuit is proposed.

[0017]

In order to solve the above-mentioned problems, according to a first aspect of the present invention, in a motion detection circuit used in an image compression apparatus, a pixel of a specific block of a reference frame and a plurality of pixels set in the motion detection frame are set. Pixel comparison means for comparing the pixels of the block of the specific block, means for counting the number of pixels determined to match by the pixel comparison means, and a block of the specific block based on the block of the motion detection frame for which the count value of the counting means is maximum. It is characterized in that a motion vector calculating means for calculating a motion vector is provided.

According to the second aspect of the invention, in a motion detection circuit used in the image compression apparatus, a pixel comparison means for comparing pixels of a specific block of the reference frame with pixels of a plurality of blocks set in the motion detection frame. When comparing pixels by the pixel comparison means, comparison bit length determination means for determining the bit length to be compared, means for counting the number of pixels determined to match by the pixel comparison means, and the count value of the counting means are the maximum. And a motion vector calculating means for calculating a motion vector of a specific block based on the block of the motion detection frame.

[0019]

In FIG. 1, for example, pixel data a1 to ak of a specific block Q (FIG. 7) of the current frame is output from the A / D conversion and raster / block conversion circuit 12 of the interframe predictive coding circuit 10 (FIG. 6). This is the motion detection circuit 2
6 pixel coincidence detectors 31A to 31N. The pixel coincidence detectors 31A to 31N output pixel data g1 to macroblocks M1 to MN in the motion detection search range L of the previous frame output from the frame delay circuit 24.
gk is also supplied.

Then, as shown in FIG. 4, each pixel data a
Of all the bits 1 to ak and g1 to gk, the high-order h bits determined by the comparison bit length determination unit 33 (FIG. 1) are extracted by the bit length control unit 41, and the exclusive OR circuit 42a to It is compared at 42h. Here, when all the h bits match, the output of the NOR circuit 43 becomes "1", and the counter 44 is counted up.

Similarly, the remaining pixel data a2 to aN of the current frame and the remaining pixel data g2 to g of the previous frame.
The upper h bits of N are compared with each other, whereby the count value of the counter 44 indicates the number t of matched pixels.

The output signals S (t1) to S (tN) of the counter 44 of each of the pixel coincidence detectors 31A to 31N are sent to the N input selector 56 of the motion vector detector 26 as shown in FIG.
Are sequentially supplied to the comparator and selector 51 under the control of the select controller 57. Here, the maximum signal S (ti) latched by the latch circuit 52 is compared, and the larger signal S (ti) is compared.
Is selected and latched by the latch circuit 52. The comparison result SH at this time is supplied to the selector 53.

The selector 53 is sequentially supplied with the identification numbers SB of the macro blocks M1 to MN corresponding to the input signals S (t1) to S (tN) from the selector controller 56, and is latched by the latch circuit 54. The identification number SB up to that point is supplied. Here, the identification number SB (i) of the macro block Mi corresponding to the comparison result SH supplied from the comparator and selector 51 is selected.

In this way, the identification number SB (i) of the macro block Mi having the largest number of matching pixels ti is detected, and the motion vector calculator is based on the macro block Mi corresponding to this identification number SB (i). At 55, the motion vector v is calculated.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a motion detecting circuit according to the present invention will be described in detail with reference to the drawings. In addition,
The same parts as those described above are designated by the same reference numerals and detailed description thereof is omitted.

FIG. 1 shows a system of the motion detection circuit 26 according to the present invention. This motion detection circuit 26 can be applied to the inter-frame predictive coding circuit 10 (FIG. 6) described above, and the video signal a of the current frame output from the A / D conversion and raster / block conversion circuit 12 is the motion detection circuit. It is supplied to 26 pixel coincidence detectors 31A to 31N.

The pixel coincidence detectors 31A to 31N are provided in the same number as the macro blocks M1 to MN set in the motion detection search range L (FIG. 7) of the previous frame in this example. It is connected in parallel. Then, as shown in FIG. 2, these pixel coincidence detectors 31A to 31N have k pixel data set as comparison target pixels among the pixel data in the macro block Q of the reference frame, in this example, the current frame. Q (a1 to ak) is supplied. Here, the comparison target pixels can be set to all the pixels in the macroblock Q or every other pixel, for example.

Further, the pixel coincidence detectors 31A to 31N are also supplied with the motion detection frame output from the frame delay circuit 24 (FIG. 1) under the control of the address control unit 27, in this example the video signal g of the previous frame. To be done. Here, for example, for the first pixel coincidence detector 31A, the macroblock M set within the motion detection search range L of the previous frame is used.
Among the 1 to MN, the pixel data M1 (g1 to gk) in the first macro block M1 is supplied. Then, the pixel coincidence detector 31A uses the pixel data Q (a1 to ak) in the macro block Q of the current frame and the pixel data M1 (g1 to gk) in the first macro block M1 of the previous frame.
Are determined to be identical to each other.

Similarly, the other pixel coincidence detectors 31B to 31B.
Also in 31N, the pixel data Q (a1 to ak) in each macroblock Q of the current frame and the pixel data M2 (g1 to gk) to MN in the macroblocks M2 to MN of the previous frame.
(G1 to gk) are compared with each other to determine whether they match. Then, the pixel coincidence detectors 31A to 31N
From the signals S (t1) to S (t
N) is output, and this is supplied to the motion vector detection unit 32 (FIG. 1).

The motion vector detecting section 32 detects the signal S (ti) having the maximum number ti of the matching numbers t among the input signals S (t1) to S (tN). As a result, the macroblock Mi of the previous frame having the maximum number of pixels t that matches the macroblock Q of the current frame is detected, and the motion vector v of the macroblock Q of the current frame is calculated based on this macroblock Mi.

Now, referring to FIG. 1, this motion detection circuit 26
Is provided with a comparison bit length determination unit 33, which includes a transmission rate p, an average step size s when quantizing pixel data a1 to ak, g1 to gk, and noise indicating whether or not there is noise in the signal input unit. The information r is input. Then, as shown in FIG. 3, with the input data p, s, and r as parameters, the pixel coincidence detectors 31A to 31N use the pixel data g1 to gk of the previous frame and the pixel data a of the current frame.
The bit length h when comparing 1 to ak is determined.

For example, the transmission rate p = 3 (1p = 64K
bps), noise information r = 0 (no noise), and an average quantization step size s = 32, the comparison bit length h = 5 bits. The signal S (h) indicating the comparison bit length h is supplied to the pixel coincidence detectors 31A to 31N.

Then, the pixel coincidence detectors 31A to 31N input pixel data a1 to ak or pixel data g1.
Even if the bit width of ~ gk is 8 bits, for example, only the upper 5 bits of them are compared and it is determined whether or not they match. Further, here, the transmission rate p = 6
In the following, if the noise information r = 1 (with noise), the noise information r
The bit length is set to be smaller by 1 bit than that in the case of = 0 (no noise), and the influence of noise can be prevented.

Now, as shown in FIG. 4, the pixel coincidence detectors 31A to 31N of the motion detecting circuit 26 generate the pixel data a based on the signal S (h) from the comparison bit length judging section 33.
1 to ak, g1 to gk, the exclusive-OR circuits 42a to 42h for comparing each bit of the upper h bits extracted by the bit length control unit 41, which extracts the upper h bits. And these exclusive OR circuits 42
It is composed of a NOR circuit 43 which receives the output "0" or "1" of a to 42h as an input signal, and a counter 44.

In the first exclusive OR circuit 42a, first, the first bit a1 (1) of the first pixel data a1 in the supplied macroblock Q of the current frame and the supplied macroblocks M1 to MN of the previous frame. The first bit g1 (1) of the first pixel data g1 is compared. If they match, "0" is sent out, and if they do not match, "1" is sent out.

Similarly, in the exclusive OR circuits 42b to 42h, the second bit a1 of the pixel data a1 of the current frame is used.
(2) to h-th bit a1 (h) and the second bit g1 (2) to h-th bit g1 of the pixel data g1 of the previous frame
Is compared with (h), which results in "0" or "1"
Is sent.

These exclusive OR circuits 42a to 42h
Is output to the NOR circuit 43. When the outputs of the exclusive OR circuits 42a to 42h are all "0",
That is, the NOR circuit 43 outputs "1" only when the upper h bits of the pixel data a1 and the upper h bits of the pixel data g1 all match, thereby causing the counter 44 to operate.
Is incremented by "1".

Similarly, the bit length control unit 41 extracts upper h bits from the next pixel data a2 of the current frame and the next pixel data g2 of the previous frame, and each bit a2
(1) to a2 (h) and g2 (1) to g2 (h) are respectively compared by the exclusive OR circuits 42a to 42h, and when they are all the same, "1" is sent from the NOR circuit 43 and the counter 44 Is counted up. Therefore,
The count value of the counter 44 indicates the number of pixels t at which the upper h bits of the pixel data a1 to ak of the current frame and the upper h bits of the pixel data g1 to gk of the previous frame match.

The output signals S (t1) to S (tN) of the counter 44 in the pixel coincidence detectors 31A to 31N are sequentially supplied to the N input selector 56 of the motion vector detecting section 32 as shown in FIG. Select controller 5
It is sequentially supplied to the comparator and selector 51 by the identification number SB supplied from 7. Here, it is compared with the maximum signal S (ti) that has been latched by the latch circuit 52. Then, the larger signal S (ti) is selected and latched in the latch circuit 52. The comparison result SH at this time is supplied to the selector 53.

The selector 53 is sequentially supplied with the identification numbers SB of the macro blocks M1 to MN corresponding to the input signals S (t1) to S (tN) from the selector controller 56, and is latched by the latch circuit 54. The identification number SB up to that point is supplied. Then, the identification number SB (i) of the macro block Mi corresponding to the comparison result SH supplied from the comparator / selector 51 is selected and latched by the latch circuit 54.

By repeating the above-mentioned processing, the macroblock Mi having the maximum number of matching pixels ti is finally obtained.
Identification number SB (i) is detected and is supplied to the motion vector calculator 55. The motion vector calculator 55 determines the position of the macro block Mi corresponding to the identification number SB (i), and thereby calculates the motion vector v of the macro block Q of the current frame.

[0042]

As described above, according to the first aspect of the invention, the pixels in the macroblock of the reference frame are compared with the pixels in the plurality of macroblocks of the motion detection frame, and the motion detection in which the number of matching pixels is the maximum is compared. The motion vector is calculated as an image after moving the macro block of the frame.

Therefore, according to the first aspect of the invention, an adder circuit, a sum-of-products circuit or the like which is required in a conventional motion detection circuit using an absolute value sum of differences of pixel data or a square sum of differences as an evaluation function is used. Since it can be configured without any, there is an effect that the circuit scale can be significantly reduced and the processing speed can be increased.

In the second invention, when comparing pixel data, the bit length to be compared is controlled depending on the presence or absence of noise. Therefore, according to the second aspect of the invention, when there is a lot of noise, the effect of noise can be prevented by shortening the bit length to be compared, and the motion vector can be accurately detected.

[Brief description of drawings]

FIG. 1 is a system diagram of a motion detection circuit according to the present invention.

FIG. 2 is a diagram illustrating a comparison target pixel.

FIG. 3 is a diagram illustrating a method of determining a comparison bit length.

FIG. 4 is a system diagram of pixel coincidence detectors 31A to 31N.

5 is a system diagram of a motion vector detection unit 32. FIG.

FIG. 6 is a system diagram of a general interframe predictive coding circuit 10.

FIG. 7 is a diagram illustrating a procedure for detecting a motion vector v.

[Description of Codes] 12 A / D conversion and raster / block conversion circuit 24 Frame delay circuit 26 Motion detection circuit 27 Address control unit 31A to 31N Pixel coincidence detector 32 Motion detection unit 33 Comparison bit length determination unit 41 Bit length control unit 42a to 42h Exclusive OR circuit 43 NOR circuit 44 Counter 51 Comparator 52, 54 Latch circuit 53 Selector 55 Motion vector calculator 56 N input selector 57 Select controller

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[Procedure amendment]

[Submission date] March 10, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

[Equation 1]

Claims (3)

[Claims] 1. In a motion detection circuit used in an image compression apparatus, pixel comparison means for comparing pixels of a specific block of a reference frame with pixels of a plurality of blocks set in the motion detection frame, and the pixel comparison means. And a motion vector calculation means for calculating the motion vector of the specific block based on the block of the motion detection frame in which the count value of the counting means is maximum. Motion detection circuit characterized by. 2. In a motion detection circuit used in an image compression apparatus, pixel comparison means for comparing pixels of a specific block of a reference frame with pixels of a plurality of blocks set in the motion detection frame, and the pixel comparison means. When comparing pixels with each other, a comparison bit length determining means for determining a bit length to be compared, a means for counting the number of pixels determined to match by the pixel comparing means, and a count value of the counting means being the maximum A motion detection circuit comprising motion vector calculation means for calculating a motion vector of the specific block based on a block of a motion detection frame. 3. The exclusive-OR circuit, which receives the pixel data of the specific block and the pixel data of the block of the motion detection frame as inputs, and the output of the exclusive-OR circuit, as input. 3. A motion detection circuit according to claim 1, wherein the motion detection circuit is configured by a NOR circuit.