JPH06164929A - Gradation conversion processing method and device therefor - Google Patents

Abstract

PURPOSE:To apply gradation conversion to an N-value picture into an M-value picture (N<M) by generating an optimum emphasis picture from any of a contour part and an intermediate tone part in the picture. CONSTITUTION:A 1st multi-value processing circuit 11, a 2nd multi-value processing circuit 12, a 3rd multi-value processing circuit 13, a 4th multi-value processing circuit 14, and a 5th multi-value processing circuit 15 generate a multi-value processing signal from an N-value picture. Then multi-value processing signals 200-204 are used to change the emphasis at an edge emphasis circuit 17 based on a signal 205 representing a characteristic quantity from a characteristic quantity detection circuit 16 to generate emphasis picture data 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation conversion processing method and apparatus for converting an N-valued image into an M-valued image (N <M) and enhancing the image.

[0002]

2. Description of the Related Art Conventionally, fixed coefficient enhancement processing has been performed on multi-valued image data by smoothing processing (for example, Japanese Patent Laid-Open No. 62-114377).

[0003]

However, in the above-mentioned conventional configuration, the method of globally performing the enhancement process of the fixed coefficient on the image after multi-value quantization realizes the optimal enhancement process in the character region and the photo region. Can not. For example, if the degree of emphasis is increased in order to sharpen the character area, the character image quality is improved, but the emphasis processing is also applied strongly to the photo area, which impairs smoothness and deteriorates the output image. .

The present invention solves the above-mentioned conventional problems, and provides an excellent gradation conversion processing method and apparatus capable of optimum gradation conversion of an image in both the contour portion and the halftone portion in the image. The purpose is to do.

[0005]

In order to achieve this object, the gradation conversion processing method of the present invention extracts a feature amount from the input N-valued image data and uses the spatial filter to convert the N-valued image data into M-values. Value image data (N <M) is converted, and emphasized image data is generated from the output of the spatial filter while changing the emphasis coefficient according to the extracted feature amount. Further, the emphasized image data is a plurality of spaces. It is generated from the output of the filter.

Further, the gradation conversion processing apparatus uses an extraction means for extracting a feature amount in the input N-valued image data and a spatial filter to convert the N-valued image data into M-valued image data (N <
M) and a highlighting unit that generates enhanced image data from the output of the spatial filter of the transforming unit while changing the enhancement coefficient in accordance with the extracted feature amount. The converting means is composed of a plurality of spatial filters, and the enhancing means is adapted to generate enhanced image data from the outputs of the plurality of spatial filters.

Further, the gradation conversion processing apparatus converts the N-valued image data into M-valued image data (N <M) by an extracting means for extracting a feature amount in the input N-valued image data and a plurality of spatial filters. The conversion means for converting and the emphasis means for generating emphasized image data from the outputs of the plurality of spatial filters of the conversion means while changing the emphasis coefficient according to the extracted feature amount are formed on the same chip. .

[0008]

With the above configuration, the feature amount in the input N-valued image data is extracted, the N-valued image data is converted into the M-valued image data (N <M) by the spatial filter, and the extracted feature amount is determined according to the extracted feature amount. Since the emphasized image data is generated from the output of the spatial filter while changing the emphasis coefficient by
The contour area of the figure can be emphasized by increasing the emphasis degree, and the area such as a photograph area in which the density change is small can be emphasized by decreasing the emphasis degree. Furthermore, since the emphasized image data is generated from the outputs of the plurality of spatial filters, the capacity of the delay memory can be reduced.

Extraction means for extracting a feature amount in the input N-valued image data, conversion means for converting the N-valued image data into M-valued image data (N <M) by a plurality of spatial filters, and extraction Since the emphasizing means for generating the emphasized image data from the outputs of the plurality of spatial filters of the converting means while changing the emphasizing coefficient according to the feature amount are formed on the same chip, the capacity and the integration of the delay memory are increased. The number of I / O pins on the circuit chip can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A gradation conversion processing method and apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the processing arrangement of a gradation conversion processing apparatus according to an embodiment of the present invention. In FIG. 1, a 1-line memory 20, a 1-line memory 21, a 1-line memory 22, and a 1-line memory 23 are delay memories for delaying the N-value image data 100 in the sub-scanning direction i. 104 is generated. A first multi-valued circuit 11, a second multi-valued circuit 12, and a third multi-valued circuit 13, which are a plurality of spatial filters forming a conversion means,
The fourth multivalued circuit 14 and the fifth multivalued circuit 15 input the N-valued image data 100 and the sub-scanning delay data 101 to 104 in accordance with the respective processing lines, and set the pixel of interest and the pixels around it. The addition processing is performed based on the weighted coefficient or the smoothed region, and the multi-valued signals 200 to 204 are obtained.
To generate. The feature amount detection circuit 16 uses the N-valued image data 10
0 and its sub-scanning delay data 101 to 104 are input, and N
The feature amount near the pixel of interest of the value image data 100 is extracted. The edge emphasizing circuit 17 inputs the multilevel signals 200 to 204, and outputs the signal 205 output from the feature amount detecting circuit 16.
The edge enhancement amount is changed according to
Generates 0.

The operation of the gradation conversion processing device configured as described above will be described below with reference to FIGS. 1, 2, 3, 4, and 5. First, the operation of converting N-value image data into M-value image data (N <M) will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram of a third multi-value quantization circuit for converting N-valued image data into M-valued image data (N <M), and FIG. 3 is a diagram for explaining addition weighting coefficients in the addition circuit 131 in FIG. In the present embodiment, N and M are not specified. However, assuming that N = 2 and M = 256, for example, the block diagram of the third multi-value quantization circuit in FIG. 2 will be described below.

The adder circuit 131 outputs N signals 101 to 103.
The value image data is input, and the signal 300 (Sp) is generated using the weighting factors shown in FIG. The value of the pixel of interest is P
When (i, j) and the signal 300 are Sp, Sp is calculated as in Expression (1).

Sp = + 1 × P (i-1, j-1) + 2 × P (i-1, j) + P (i-1, j + 1) + 2 × P (i, j-1) + 3 × P (i , J) + 2 × P (i, j + 1) + 1 × P (i + 1, j−1) + 2 × P (i + 1, j) + 1 × P (i + 1, j + 1) ... (1) The image input in the addition circuit 131 When the number of gradations of data is N and the sum of the weighting factors of the added areas is Sx, the maximum output value Mx is as shown in equation (2).

Mx = (N-1) * Sx (2) Therefore, to normalize the signal 300 from the Mx obtained from the equation (2) into the multi-valued signal 202 in the M-value image, the equation (3) is used. Is calculated. However, if the signal 202 is Px,
Let signal 300 be Sp.

Px = Spx ((M−1) ÷ Mx) (3) Therefore, the K multiplication circuit 132 performs multiplication K = (M−1) ÷ Mx. Here, if Mx = M-1, then K
The multiplication circuit 132 may be omitted. In this example, M =
Since 256 and Mx = 15, K = 17, and the K multiplication circuit 132 multiplies the input signal 300 (Sp) by 17 to generate the multilevel signal 202 (Px).

As described above, the third multi-value quantization circuit 13, which is a spatial filter, performs conversion processing on a pixel-by-pixel basis into M-value image (N <M) data using the pixel-of-interest and N-value image data around the pixel of interest. The binarized signal 202 (Px) is generated.

The first multi-valued circuit 11, the second multi-valued circuit 12, the fourth multi-valued circuit 14 and the fifth multi-valued circuit 1 in FIG.
5 is an M-value image (N <M) in pixel units using the pixel of interest and N-valued image data around the pixel of interest by similar processing.
The data is converted into data, and the first multi-valued circuit 11 outputs the signal 200 (Ax) and the second multi-valued circuit 12 outputs the signal 201 (Ax).
(Bx), and the fourth multilevel circuit 14 outputs the signal 203 (Cx).
And the fifth multi-value quantization circuit 15 generates a signal 204 (Dx).

Next, the edge emphasis circuit 17 will be described with reference to FIG.
This will be described with reference to FIG. FIG. 4 is an explanatory diagram of a reference pixel arrangement when edge enhancement is performed. In FIG. 4, when the target pixel position is P (i, j), the edge emphasis circuit 17 has a pixel position A (i-1, j-1) and a pixel position B (i-1, j).
j + 1), pixel position C (i + 1, j-1), pixel position D
Refer to (i + 1, j + 1). Therefore, the edge emphasizing circuit 17 outputs the output signal 200 of the first multi-valued circuit 11 at the pixel position A, the output signal 201 of the second multi-valued circuit 12 at the pixel position B, and the fourth multi-valued signal at the pixel position C. With reference to the output signal 203 of the circuit 14, the output signal 204 of the fifth multi-value quantization circuit 15 at the pixel position D, and the output signal 202 of the third multi-value quantization circuit 13 at the pixel position P of the pixel of interest, a signal 205 is obtained. Accordingly, the operation of the equation (4) is performed to generate the emphasized image data 110. Here, the signal 200 is Ax, the signal 201 is Bx,
Signal 202 is Px, signal 203 is Cx, signal 204 is D
x, the signal 205 is Eg, and the emphasized image data 110 is OUT
The maximum value of Eg is Emax, and the control coefficient is EP. In addition, [] is an integerization process that rounds down the fractional part.

OUT = [((5 + W) × Px−Ax−Bx−Cx−Dx) ÷ (1 + W)] W = (1−Eg ÷ Emax) × EP (4) The control coefficient EP is a range in which the degree of emphasis is changed. The larger the change range of the emphasis degree, the smaller the change range of the emphasis degree. The coefficient EP is a parameter obtained experimentally. By setting this parameter EP, it is possible to control the amount of change in the weight coefficient W in the equation (4). The emphasis degree and the emphasized image data OUT corresponding to the weight coefficient W can be generated from the equation (4). (4)
For example, in order to obtain M-value image data in which the maximum value of OUT is 255, OUT = 255 when OUT> 255
5, when OUT <0, clip processing may be performed to OUT = 0.

Next, the feature amount detection circuit 16 will be described.
The case of calculating the edge amount in the vicinity of the pixel of interest as the feature amount will be described with reference to FIG. FIG. 5 is an explanatory diagram showing a configuration example of a filter for calculating the edge amount. For example, Wa is a filter that detects an edge component in the main scanning direction j, and Wb is a filter that detects an edge component in the sub scanning direction i. When the value of the pixel of interest is P (i, j), the edge amount at the pixel of interest is calculated based on, for example, equation (5). Here, Wb is an edge component in the sub scanning direction i, Wa is an edge component in the main scanning direction j, and Eg is a combined value. Also, ABS (Wa) is the absolute value of Wa, A
BS (Wb) is a calculation that is the absolute value of Wb. Also,
Instead of the average value processing, the difference amount may be obtained for each row and each column, and the absolute value amount may be calculated as the edge amount.

Wa = P (i-1, j-1) + 2 * P (i, j-1) + P (i + 1, j-1) -P (i-1, j + 1) -2 * P (i, j + 1) ) -P (i + 1, j + 1) Wb = P (i-1, j-1) + 2 * P (i-1, j) + P (i-1, j + 1) -P (i + 1, j-1) -2 * P (i + 1, j) -P (i + 1, j + 1) Eg = ABS (Wa) + ABS (Wb) (5) Here, when the maximum value of the edge amount Eg is set to Emax, when Eg> Emax, Eg = Clip to Emax. As a result, the weight coefficient W in the equation (4) changes from 0 to EP according to the edge amount Eg as the signal 205 of the characteristic amount. If the weighted coefficient W is used to generate the emphasized image data OUT as shown in Expression (4),
In the contour area of the character / graphic, the amount of edge detection becomes large, and the degree of emphasis is increased to perform the emphasis processing. Further, in a region such as a photographic region where the density change is small, the edge detection amount is small, and the degree of enhancement can be weakened to perform the enhancement process, and optimal enhanced image data OUT can be obtained in any case.

In the above, the case where the edge component is used as the feature amount has been described, but the feature amount is not limited to the edge component in the present invention, and a character region, a photograph region, a graphic region, a contour region, etc. can be identified. Any characteristic amount will do. Although not shown as an embodiment, for example, the difference between the maximum density level and the minimum density level in a predetermined block may be used as the feature amount using the density gradient method, and the primary feature may be used using the pattern discrimination method. May be obtained by Laplacian, binarized, and then block-formed to detect pattern information, and the degree of correlation with a predetermined reference pattern may be used as the feature amount. In addition, the combination method (maximum value-minimum value)
It is also possible to create an area distribution based on the number of inversions of the binarized pixels inside the block, and use the degree of belonging to the character area and the degree of belonging to the photograph area as the feature amount.

Further, a global identification method may be introduced, and the detected frequency distribution may be used as a feature quantity by using orthogonal transform or Hadamard transform, or the autocorrelation between pixels in a region may be obtained to determine the degree of correlation. May be used as a feature amount. Either method may be used as the feature amount. By changing the weight coefficient W of the equation (4) from this feature amount, the emphasis degree is changed.

Next, a second embodiment in which integration is performed using an integrated circuit chip will be described with reference to FIG. The first multi-valued circuit 11, the second multi-valued circuit 12, the third multi-valued circuit 13, the fourth multi-valued circuit 14, and the fifth multi-valued circuit 15 in FIG.
Multivalues the N-valued image data to obtain an M-valued image (N <M). Using the multi-valued signals 200 to 204 obtained respectively, the edge enhancement circuit 17 is operated by performing the operation represented by the equation (4) according to the signal 205 of the feature amount from the feature amount detection circuit 16.
Generates enhanced image data 110. An example in which the dotted line region 1 is formed on the same integrated circuit chip when the processing portion is the dotted line region 1 will be described. Although N and M are not specified in this embodiment, for example, N = 2 and M = 2.
The following description will be given as 56.

From N-valued image data to M-valued image data (N <
The number of delay memories used when multi-valued in M) is N =
The 1-line delay memory of 2 to 1 bit is 4 from the second embodiment.
I need one. Further, the multilevel signals 200 to 204 have M =
Although the number of signal lines is increased from 256, the first multilevel circuit 1
1, second multi-valued circuit 12, third multi-valued circuit 13, fourth multi-valued circuit 14, fifth multi-valued circuit 15, feature amount detection circuit 1
6. By forming the edge emphasis circuit 17 on the same integrated circuit chip, the number of input / output pins can be reduced.

If only the signal pin is described as the input / output pin, the input pin is the N-value image data 100 and the sub-scanning delay data 10.
Each 1 bit of 1 to 104 has 5 pins. The output pin is 8 bits because the final signal 110 is M-value image data, and 8 pins are required. Therefore, four 1-bit 1-line memories are used, and 13 I / O pins are used.
All that is required is an integrated circuit chip having pin signal pins.

On the other hand, a third embodiment for performing the same processing as in the dotted line area 1 in FIG. 1 will be described with reference to FIGS. FIG. 6 is a block diagram illustrating a processing configuration example of the third embodiment. In FIG. 6, the following description will be made assuming N = 2 and M = 256 as in the second embodiment. Further, the third multi-value quantization circuit 13, the feature amount detection circuit 16, and the edge enhancement circuit 17 use the same circuits as those in the second embodiment, and the edge enhancement circuit 17 performs the operation of the equation (4) to enhance the emphasized image data 110. To generate. Here, an example in which the dotted line region 1000 is formed on the same integrated circuit chip will be described.

The third embodiment is different from the second embodiment in that one third multivalued circuit 13 is used to enhance the emphasized image data 60.
This is the point where 0 is generated, and the N-valued image data 400 and the sub-scanning delay data 401 and 402 are input to the third multi-value quantization circuit 13, and the sub-scanning delay data 401 to 403 are input to the feature amount detection circuit 16. It

From N-valued image data to M-valued image data (N <
The number of delay memories used when multi-valued in M) is N =
A 1-line delay memory of 2 to 1 bit is used in the third embodiment according to the third embodiment.
You need one. I / O pins are only signal pins,
Input pin is N-value image data 400 and sub-scan delay data 4
One bit of each of 01 to 403 corresponds to 4 pins. The 1-line memory 42 for data delay is not necessary for the third multi-value quantization circuit 13, but the feature quantity detection circuit 16 and the edge enhancement circuit 1
It is used to align the positions of 7 pixels of interest.

Further, since the edge emphasizing circuit 17 refers to the pixel position data of the position A, the position B, the position C and the position D with respect to the target pixel position P shown in FIG. Multi-valued signal 501 of 1 line memory 50, 1
After delaying in the line memory 51, the multi-valued data 501 and the delay data 502 and 503 are input to the edge emphasizing circuit 17. Here, since the input / output pins are 8 bits for the output signal and the input signal of the multi-valued signal 501, 8 pins are required since each bit is 8 bits from M = 256. However, since the output signal and the input signal are the same signal, only 8 pins on the output signal side are required. For the delay data 502 and 503, 8 pins are required for input. Final signal 6
For 00, since it is M-value image data, it becomes 8 bits, and 8 pins are required. Therefore, in addition to the total 32 pins, an integrated circuit chip having a total of 36 input / output signal pins from 1 pin of the N-value image data 400 and 3 pins of the outputs of the 1-line memories 40, 41, 42 is required. Becomes

According to the processing configuration example of the third embodiment, the weighted image data OUT is expressed by the equation (4) using the weight coefficient W.
Is generated, the edge detection amount increases in the outline area of the character / graphic, and the emphasis degree is strengthened to perform the emphasis processing. Further, in a region such as a photographic region where the density change is small, the edge detection amount becomes small and the enhancement degree can be weakened to perform the enhancement process, and the optimal enhanced image data OUT can be obtained in any case.

Furthermore, if an integrated circuit chip is produced by the processing configuration of the second embodiment from the description of the second and third embodiments above, the total number of bits of the delay memory for delaying by one line is 4/19, The input / output signal pin becomes 13/36.
Therefore, the capacity of the delay memory and the number of input / output signal pins can be reduced.

In the second embodiment, the scale of the multi-valued circuit is five times as large as that in the third embodiment, but the processing configuration example of the second embodiment has a smaller total number of gates including the capacity of the delay memory, which is high. Integration and high-density packaging can be realized.

Further, in these embodiments, a copying machine, a printer,
By applying it to a display device or the like, the image data capacity can be reduced and high-quality output and display can be realized. When applied to color output devices and color display devices,
The image data capacity can be further reduced while maintaining the image quality.

[0036]

As described above, according to the present invention, the feature amount in the input N-valued image data is extracted, and the N-valued image data is converted into the M-valued image data (N <
M), and emphasized image data is generated from the output of the spatial filter while changing the emphasis coefficient in accordance with the extracted feature amount, so that the contour area of the character / graphic is strongly emphasized, such as a photograph area. There is an effect that the enhancement degree can be weakened and the enhancement processing can be performed in the region where the change in the density is small. Furthermore, since the emphasized image data is generated from the outputs of the plurality of spatial filters, there is an effect that the capacity of the delay memory can be reduced.

Further, an extracting means for extracting a feature amount in the input N-valued image data, a conversion means for converting the N-valued image data into M-valued image data (N <M) by a plurality of spatial filters, When the emphasizing means for generating the emphasized image data from the outputs of the plurality of spatial filters of the converting means while changing the emphasizing coefficient according to the extracted feature amount is formed on the same chip, the capacity of the delay memory and the integrated circuit chip The effect is that the number of I / O pins can be reduced.

As a result, it is possible to realize an excellent gradation conversion processing method and apparatus capable of optimal gradation conversion in both the contour portion and the halftone portion in the image and reducing the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a processing configuration of a gradation conversion processing apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a third multi-value quantization circuit in the same gradation conversion processing device.

FIG. 3 is a diagram for explaining an addition weighting coefficient of an addition circuit in the third multi-value quantization circuit.

FIG. 4 is a diagram illustrating a reference pixel arrangement of an edge enhancement circuit in the gradation conversion processing device.

FIG. 5 is a diagram illustrating a filter configuration example for calculating an edge amount in a feature amount detection circuit in the same gradation conversion processing device.

FIG. 6 is a block diagram showing a processing configuration of a gradation conversion processing apparatus according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Integrated circuit chip 11 1st multivalued circuit 12 2nd multivalued circuit 13 3rd multivalued circuit 14 4th multivalued circuit 15 5th multivalued circuit 16 Feature amount detection circuit 17 Edge emphasis circuit

Claims (11)

[Claims] 1. A feature amount in input N-valued image data is extracted, the N-valued image data is converted to M-valued image data (N <M) by a spatial filter, and enhancement is performed according to the extracted feature amount. A gradation conversion processing method, wherein enhanced image data is generated from the output of the spatial filter while changing the coefficient. 2. The gradation conversion processing method according to claim 1, wherein the spatial filter adds the target image of the N-value image data and its peripheral pixels based on the weighting coefficient or the smooth region. 3. The gradation conversion processing method according to claim 1, wherein an edge amount in the vicinity of the pixel of interest is extracted as the feature amount. 4. The gradation conversion processing method according to claim 1, wherein the emphasized image data is generated from outputs of a plurality of spatial filters. 5. Extraction means for extracting a feature amount in the input N-valued image data, conversion means for converting the N-valued image data into M-valued image data (N <M) by a spatial filter, and the extracted said A gradation conversion processing device comprising: an emphasis unit that generates emphasized image data from the output of the spatial filter of the conversion unit while changing the emphasis coefficient according to the feature amount. 6. The gradation conversion processing device according to claim 5, wherein the spatial filter adds the pixel of interest of the N-valued image data and its peripheral pixels based on a weighting coefficient or a smooth region. 7. The gradation conversion processing device according to claim 5, wherein the extraction means extracts an edge amount in the vicinity of the pixel of interest as the feature amount. 8. The gradation conversion processing apparatus according to claim 5, wherein the conversion means is composed of a plurality of spatial filters, and the emphasis means generates the emphasized image data from the outputs of the plurality of spatial filters. 9. Extraction means for extracting a feature amount in the input N-valued image data, conversion means for converting the N-valued image data into M-valued image data (N <M) by a plurality of spatial filters, and extraction A gradation conversion processing device, characterized in that the emphasizing means for generating emphasized image data from the outputs of the plurality of spatial filters of the converting means while changing the emphasizing coefficient according to the feature amount are formed on the same chip. . 10. The gradation conversion processing apparatus according to claim 9, wherein the spatial filter adds the pixel of interest of the N-valued image data and its peripheral pixels based on the weighting coefficient or the smoothing area. 11. The gradation conversion processing device according to claim 9, wherein the extraction means extracts an edge amount in the vicinity of the pixel of interest as the feature amount.