JPH06164912A - Picture reader - Google Patents

Abstract

PURPOSE:To easily and quickly discriminate a state of a function of the reader. CONSTITUTION:A changeover switch S1 is provided between a CCD 9 and a signal processing circuit 30 and when a test switch 507a of an operation display board 500 is depressed, the changeover switch S1 is thrown from the position of analog picture signals OS1, OS2 outputted from the CCD 9 to the position of test dummy reference signals OS1', OS2' outputted from a pseudo signal generating circuit 61. When a fault takes place in the reader, which of the CCD 9 and the signal processing circuit 30 is faulty is easily and quickly detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a CCD to transfer original image information
An image reading device that optically reads an image signal using a line image sensor such as a digital image sensor and performs electrical processing such as amplification and A / D conversion on the obtained image signal, and particularly determines the quality of the signal processing circuit of the device. For improvement to do.

[0002]

2. Description of the Related Art FIG. 17 shows an example of an electric circuit of a conventional image reading apparatus. This image reading apparatus includes a CCD circuit (SBU) 20 for optically reading an image and a signal processing circuit (V
PU) 30 on the CCD substrate and the signal processing substrate, respectively.

Analog output signal OS1 from CCD 9
(Odd order image signals) and OS2 (even order image signals) are amplified by the amplifier circuits 21a and 21b and the amplifier circuits 31a and 31b. This is because the output voltage of the CCD 9 is small and needs to be amplified to a voltage that is easy to process. The output signals OS1 and OS2 have a phase of 180 as shown in FIG.
Deviated. That is, CCD 9 with 2 channel output
The clock frequency is 1/2 of the pixel frequency, and a doubling frequency is obtained by performing signal processing and synthesizing OS1 and OS2 in the synthesizing circuit 38 described later.

The amplified image signal is transferred to the clamp circuit 32.
Clamped by a and b, the sample and hold circuit 33a,
The sample is held at b, 34a, and b. The sample hold circuits 33a and 33b are provided with S / H1 as shown in FIG.
The signal and the S / H2 signal are input. When these signals are at the H level, the image signal is sampled, and when the signals are at the L level, the image signal is held. The output signals from the sample and hold circuit are OUT1 and OUT2 (FIG. 19).

Next, the image signals are amplified again by the amplifier circuits 35a, 35b, 36a, 36b, and the clamp circuits 37a,
At b, the photosensor called the light shield part of the CCD 9 is clamped so that the part covered with aluminum is fixed as cellobold. This is because the output of CCD9 is DC superimposed, so it is connected from capacitors C1 and C2.
Therefore, it is necessary to determine the absolute zero volt. The CLMP signal input to the clamp circuits 37a and 37b is a signal as shown in FIG.

Next, the image signal is combined into a 1-channel signal (FIG. 19) by alternately switching the odd-order signal and the even-order signal in the combining circuit (multiplexer MPX) 38.

Next, after being amplified by the amplifiers 39 and 40 and clamped by the clamp circuit 41, the A / D converter 4
In step 2, each pixel is converted into a digital image signal with several gradations. The digital image signal is output to, for example, an image processing device or an image recording device via the interface. CC
Timing signals are input to the D circuit 20 and the signal processing circuit 30 from the timing signal generating circuit via the amplifier circuits 44 and 45, and control signals are input from the controller via the amplifier circuit 46. Note that the components 32 to 41 form an analog IC.

[0008]

As shown in the above-mentioned conventional example, the CCD and the signal processing circuit are usually formed on different substrates. However, when the output of the signal processing circuit is abnormal, there is no method for quickly and easily determining which of the CCD and the signal processing circuit has failed, and there is no choice but to inspect them individually. For example, a digital copying machine includes a CCD, a signal processing circuit, an image processing circuit (IPU), a writing processing circuit, and the like. Of these, the image processing circuit and the writing processing circuit each have a pattern generator built therein, When an abnormality check is performed, the output of the pattern generator provided for it is processed and printed out, so that it is possible to determine the abnormality of the write processing circuit, and when it is determined that the write processing circuit is normal, the output of the pattern generator provided for it is output. By performing image processing, giving it to the writing processing circuit, and printing it out, it is possible to determine the abnormality of the writing processing circuit. If the printout of the original image is abnormal even though the writing processing circuit is normal, it can be determined that the image reading device is abnormal. Either the CCD or the signal processing circuit in the image reading device can be determined. I do not know if is abnormal. This allows
This caused a problem that it took a long time to identify the location of the failure.

Therefore, an object of the present invention is to quickly and easily determine an abnormal portion in an image reading apparatus.

[0010]

The present invention relates to an image reading means (9) for optically reading image information and outputting odd-order and even-order analog image signals (OS1, OS2), and an analog image signal. (OS1, OS2) is amplified by the amplification circuit (31a, b), the image signal part is sampled by the sample hold circuit (33a, b, 34a, b), and the black dummy signal part is sampled by the clamp circuit (37a, b). After clamping, the synthesizing circuit (38) synthesizes the odd-numbered and even-numbered analog image signals (OS1, OS2), and the A / D conversion circuit (42) converts the analog image signals into digital image signals. In an image reading apparatus including image signal processing means (30), pseudo signal generating means (61 to 6) for generating pseudo reference signals (OS1 ', OS2')
5), means for inputting a test instruction (500, 507a to 507e), and a signal path inserted from the image reading means (9) to the A / D conversion circuit (42). Signal switching means (S1) that applies the pseudo reference signals (OS1 ', OS2') downstream of this insertion position with respect to the signal flow of the signal path, and provides a signal upstream of the insertion position downstream when there is no test instruction. ~ S8), are provided. The symbols in parentheses indicate corresponding elements or corresponding matters in the embodiments described later.

In a preferred embodiment of the present invention, the signal switching means (S3, S4) is inserted between the image reading means (9) and the amplifier circuit (21a, b) immediately after it.

In a preferred embodiment of the present invention, the signal switching means (S5 to S8) are provided with sample hold circuits (33a, b, 34a,
It is inserted between b) and the A / D conversion circuit (42).

[0013]

According to the present invention, when there is no test instruction, the signal switching means (S1 to S8) inserted in the signal path from the image reading means (9) to the A / D conversion circuit (42) is inserted. The device is in the normal mode to provide a signal upstream of the position downstream,
When the operator gives a test instruction, the pseudo signal generation means
Since the pseudo reference signals (OS1 ', OS2') generated from (61 to 65) are given downstream of this insertion position with respect to the signal flow of the signal path, the functional state of the image signal processing means (30) can be checked independently. You can. Therefore, for example, when a failure occurs in the device, which of the image reading means (9) and the image signal processing means (30) is detected can be quickly and easily detected, and the corresponding repair can be performed in a short time. By doing so, after-sales service can be improved.

According to the preferred embodiment of the present invention, since the signal switching means (S3, S4) is inserted between the image reading means (9) and the amplifier circuit (21a, b) immediately after it, the pseudo signal is generated. Generating means (61 ~
Even if 65) is provided in the image reading means (9), the image signal processing means (3
It may be provided in 0). In particular, when it is provided in the image signal processing means (30), it is possible to make room for the installation area of the circuit element of the image reading means (9).

In a preferred embodiment of the present invention, the signal switching means (S5) is composed of the sample and hold circuits (33a, b, 34a, b) of the image signal processing means (30) and the A / D conversion circuit (42). Since it is inserted between them, the functional state inside the image signal processing means (30) can be checked. For example, by inserting the signal switching means (S1, S2) between the image reading means (9) and the image signal processing means (30) and outputting the pseudo reference signal from the pseudo signal generating means (61), the image signal When it is determined that the processing means (30) has a failure, the sample hold circuit (33a, b, 34) of the image signal processing means (30)
By inserting the signal switching means (S5) between the a, b) and the A / D conversion circuit (42) and outputting the pseudo reference signal from the pseudo signal generating means (63), the failure point is the image signal processing means. It can be detected whether it is on the sample-hold circuit (34a, b) side of (30) or on the A / D conversion circuit (42) side. Further, by providing a plurality of signal switching means (S5 to S8) between the sample and hold circuit (34a, b) and the AD conversion circuit (42) to generate a plurality of pseudo signals, the failure location can be further specified. Can be specified.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

[0017]

FIG. 1 shows an embodiment of the present invention. The contact glass 1 on which the document to be read is placed is a light source 2
Light reflected by the image surface of the read document is imaged on the light receiving surface of the CCD image sensor 9 through the mirrors 3, 4, 5 and the lens 8. Further, the light sources 2a and 2b and the mirror 3 are mounted on a traveling body 10 that moves in the sub-scanning direction (the direction perpendicular to the CCD image sensor 9) parallel to the contact glass 1, and the mirrors 4 and 5 are mounted on the traveling body 10. It is mounted on the traveling body 11 that moves in the sub-scanning direction at a speed of 1/2 in conjunction with it, and the image surface of the read document is scanned in the sub-scanning direction by moving the optical system. Scanning in the main scanning direction (direction in which the CCD image sensors 9 are arranged) is performed by solid-state scanning of the CCD image sensor 9. In this way, the original image is two-dimensionally read by the CCD image sensor 9. An operation display board 500 is provided on the front portion of the upper surface of the image reading apparatus 100.

FIG. 2 shows a schematic configuration of an electric circuit of the image reading apparatus 100 shown in FIG. The same parts as those of the conventional example (FIG. 17) are designated by the same reference numerals and the description thereof will be omitted.

The CCD circuit 20 and the signal processing circuit 30 include a pseudo signal generating circuit 6 for generating a test pseudo signal.
1 to 66, and changeover switches S1 to S for changing the image signal output from the CCD image sensor 9 to a pseudo signal
10 are provided. Signal W for switching the switch
1 to W10 are output from the timing signal generation circuit 200 under the control of the controller (CPU) 300.
The selection of the switching signals W1 to W10 is performed by the operation display board 50 connected to the controller (CPU) 300.
It is performed by key input of 0.

FIG. 3 shows a part of the appearance of the operation display board 500. Each key and display will be described. 501
Is a reading start key for inputting a start instruction, 502 is a ten-key for inputting the number of sheets to be read, 503 is a stop / key for inputting instructions such as clearing the number of sheets to be read and interruption of reading.
Clear key, 504 is a 7-segment display of the number of readings,
Reference numeral 505 denotes a 7-segment display of the number of sheets to be read, 506 a panel for displaying the status of the apparatus, and 507a to 507e related to the present invention, a test switch for inputting an instruction to check the functional status of the apparatus. . The test switches 507a to 507e are usually switches used by a service person, and the switches 507a to 507e.
The test pattern processing is performed in response to the depression of. When the button is pressed again, the test pattern processing is canceled and the mode returns to the normal mode (state shown in FIG. 2). Regarding the result of the test pattern processing, the presence or absence of abnormality, the abnormal portion, and the abnormal state are displayed on the display panel 506 (the image reading apparatus 100 is electrically connected to the image recording apparatus, and the result of the test pattern processing is printed out. May be done). There are various keys and indicators on the operation display board 500, such as a density key for adjusting the density and a scaling key for setting the reduction or enlargement, but they are omitted here.

Referring again to FIG. Operation display board 50
When the 0 switch 507a is pressed, the timing signal generating circuit 200 outputs switching signals W1 and W2, and the switching switches S1 and S2 switch from the output end of the image signal to the output end of the pseudo signal generating circuit 61. As a result, the pseudo signal for the test pattern is input from the pseudo signal generation circuit 61 to the amplifiers 31a and 31b, so that the CCD circuit 20 and the signal processing circuit 30 can be separated to determine the functional state.

When the switch 507b is pressed, the switching signals W3 and W4 are output from the timing signal generation circuit 200, and the changeover switches S3 and S4 are switched from the output end of the image signal to the output end of the pseudo signal generation circuit 62. As a result, the pseudo signal for the test pattern is input from the pseudo signal generating circuit 62 to the amplifiers 21a and 21b, so that the CCD
The functional state can be determined by separating the image sensor 9 and the subsequent circuits including the harness.

When the switch 507c is pressed, the switching signals W5 and W6 are output from the timing signal generation circuit 200, and the switching switches S5 and S6 are switched from the output end of the image signal to the output end of the pseudo signal generation circuit 63. As a result, since the pseudo signal for the test pattern is input from the pseudo signal generating circuit 63 to the amplifiers 36a and 36b, the circuit before the amplifiers 36a and 36b and the circuit after it are separated in the signal processing circuit 30 so that the functional state is obtained. Can be determined.

When the switch 507d is pressed, the timing signal generating circuit 200 outputs the switching signal W7, and the switching switch S7 switches from the output end of the image signal to the output end of the pseudo signal generating circuit 64. As a result, the pseudo signal for the test pattern is input to the amplifier 39 from the pseudo signal generating circuit 64, so that the circuit before the amplifier 39 and the circuits after the amplifier 39 can be separated in the signal processing circuit 30 to determine the functional state. .

When the switch 507e is pressed, the switching signal W8 is output from the timing signal generating circuit 200, and the switching switch S8 switches from the output end of the image signal to the output end of the pseudo signal generating circuit 65. As a result, the pseudo signal for the test pattern from the pseudo signal generating circuit 65 is A
Since it is input to the / D converter 42, the signal processing circuit 3
At 0, the circuit before the A / D converter 42 and the circuit after it can be separated to determine the functional state.

When a failure occurs in the device, for example, the switches 507e to 507d, 50 on the downstream side of the signal path.
7c ..., 507a in order, until the display indicating the failure is displayed on the display panel 506, the CCD
Which part of the circuit 20 or the signal processing circuit 30 has failed is detected.

Further, as shown in FIG. 4, only the pseudo signal generating circuit 62 may be provided in the signal processing circuit 30 via a harness. According to this, the area of the CCD circuit 20 can be provided with a margin.

FIG. 5 shows a schematic configuration of the pseudo signal generating circuit 62, and FIG. 6 shows pseudo signals OS1 'and OS2' output from the pseudo signal generating circuit 62. Integration capacitor 7
Since 3 integrates the DC voltage, the output of the pseudo signal generating circuit 62 is monotonically amplified, but the output signal is reset because the switch 74 is closed at the input timing of the CLMP signal (FIG. 6B). As a result, a monotonically increasing sawtooth wave as shown in FIG. 6A is input to the signal processing circuit 30, so that the linearity of the signal processing circuit 30 can be evaluated.

FIG. 7 shows a pseudo signal generating circuit 62 shown in FIG.
FIG. 8 shows an outline of the configuration of a modified example 62B, which is an alternative to the above, and shows the pseudo signals OS1 'and OS2' output in FIG. The pseudo signal generating circuit 62B includes a 1 / n frequency dividing counter 75, a counter 76 having a binary output, and a D / A converter 77.
Composed of. As a result, a waveform having a flat portion as shown in FIG. 8A is input to the signal processing circuit 30, so that the S / N (variation) of the signal processing circuit 30 can be evaluated. The S / N at each level can be evaluated simultaneously by setting the flat portion to several stages. For example, the period of one main scan is 5000 clocks, and the 1 / n frequency division counter 75
When set to / 500, the counter 76 is reset by 10 and D
The output of the / A converter 77 is in the form of 10 steps at equal intervals. As shown in FIG. 8C, the S / N and linearity can be evaluated at the same time by making the stairs at equal intervals.

FIG. 9 shows a pseudo signal generating circuit 62 shown in FIG.
FIG. 10 shows pseudo signals OS1 'and OS2' outputted in FIG. This pseudo signal generating circuit 62C is a pseudo signal generating circuit 62B (FIG. 7).
A0-A between the counter 76 and the D / A converter 77 of
An 8-bit ROM 78 having an address of 3 is inserted, and the ROM 78 outputs an output corresponding to the density linear digital value shown in FIG. Output to the converter 77. That is, since a stepwise waveform having a logarithmic interval as shown in FIG. 10 is input to the signal processing circuit 30 to make the density linear, the image reading apparatus is connected to the image recording apparatus and a copy image is output to function. When determining the state, the determination becomes easy. In addition, in the reflection linear of FIG. 11, digital values are created so that the reflectances are evenly spaced from addresses 0 to 15, and in the density linear, the reflectance is logarithmized so that the density is linear, and then digital. Make a value.

FIG. 12 shows the pseudo signal generating circuit 6 shown in FIG.
2 shows an outline of the configuration of a modified example 62D in place of 2, and shows pseudo signals OS1 'and OS2' output in FIG. The pseudo signal generating circuit 62D includes a counter 79 having a binary output, a 1 / n frequency dividing counter 80, and an octal counter 8
1, a data selector 82, and an amplifier 83.
A signal whose cycle is doubled from 0 to 7 is output from the counter 79, which is selected and switched by the data selector 82. As a result, as shown in FIG. 13A, a waveform in which rectangular waves having different periods are mixed in one main scan is output. Therefore, a rectangular wave-shaped signal is pseudo-signaled by changing the period. By inputting into the processing circuit 30, the frequency response of the signal processing circuit 30 can be evaluated. That is, the same state as when the line chart was read can be reproduced and the MTF of the circuit can be reproduced.
Can be evaluated.

Further, as shown in FIG. 14, a signal obtained by combining a linearly increasing signal and an arbitrary rectangular wave (see FIG. 14).
By repeatedly inputting (a)) to the signal processing circuit 30, both linearity and MTF can be evaluated simultaneously. This waveform is similar to the waveform of FIG.
It can be generated by combining the waveforms of (a).

As shown in FIG. 15, the sawtooth wave pseudo signal OS1 '(FIG. 15 (a)) is applied to the odd-numbered inputs, and the zero-volt pseudo signal OS2' (FIG. 15 (b) is applied to the even-numbered inputs. ))give. Or, conversely, zero voltage is applied to odd-numbered inputs and a sawtooth wave is applied to even-numbered inputs. That is, by separating the odd and even signals from each other, 1
Since a signal that repeats zero and the maximum level can be generated for each pixel, the characteristics of the amplifiers 39 and 40 after the synthesizing circuit 38 can be evaluated under more severe conditions. The output waveform from the amplifier 40 at this time is as shown in FIG.

Further, as shown in FIG. 16, the pseudo signal OS
1 '(FIG. 16A) and the pseudo signal OS2' (FIG. 16A).
By using (b)) as a waveform that once falls to the zero level for each pixel like the output waveform of the CCD, the amplifiers 21a, 21b of the first stage and the sample and hold 33a, b, 34 are used.
The characteristics of a and b can be evaluated under more severe conditions.

[0035]

As described above, according to the present invention, for example, when a failure occurs in the apparatus, which one of the image reading means (9) and the image signal processing means (30) has a failure can be quickly and easily. Since it is detected, after-sales service can be improved by performing corresponding repair in a short time.

According to the preferred embodiment of the present invention, the pseudo signal generating means (61 to 65) need not be provided in the image reading means (9), so that the area of the image reading means (9) can be afforded. It is superior.

Further, according to the preferred embodiment of the present invention, the functional state inside the image signal processing means (30) can be specifically checked.

[Brief description of drawings]

FIG. 1 is a side view showing a mechanical portion of an image reading apparatus 100 according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an electric circuit of the image reading apparatus 100 shown in FIG.

3 is an enlarged plan view showing a part of the operation display unit 500 shown in FIG.

FIG. 4 is a block diagram showing a modified example of the configuration of the electric circuit shown in FIG.

5 is a block diagram showing a schematic configuration of a pseudo signal generating circuit 62 shown in FIG.

6A is a pseudo signal generation circuit 62 shown in FIG.
The pseudo signals OS1 ', OS2', (b) output from
It is a timing chart which shows a CLMP signal.

7 is a block diagram showing a modified example 62B of the configuration of the pseudo signal generation circuit 62 shown in FIG.

8A is a pseudo signal generation circuit 62 shown in FIG.
Pseudo signals OS1 ', OS2', (b) output from B
Is a CLMP signal, and (c) is a timing chart showing pseudo signals OS1 'and OS2' when the stairs are arranged at equal intervals.

9 is a block diagram showing a modified example 62C of the configuration of the pseudo signal generation circuit 62 shown in FIG.

10 is a timing chart showing pseudo signals OS1 'and OS2' at logarithmic intervals output from the pseudo signal generating circuit 62C shown in FIG.

FIG. 11 shows pseudo signals OS1 ′ and OS2 ′ shown in FIG.
It is a top view which shows the data which determine the logarithmic interval of.

12 is a block diagram showing a modification 62D of the configuration of the pseudo signal generating circuit 62 shown in FIG.

13A is a pseudo signal generation circuit 6 shown in FIG.
Pseudo signals OS1 ', OS2', output from 2D,
(B) is a timing chart showing a CLMP signal.

FIG. 14A is a pseudo signal OS1 ′, OS2 ′, which is a combination of a linearly increasing signal and an arbitrary rectangular wave.
(B) is a timing chart showing a CLMP signal.

15A is a pseudo signal OS1 ′ of a sawtooth wave input to an odd order, FIG. 15B is a pseudo signal OS2 ′ of zero volt input to an even order, and FIG. 15C is a pseudo signal OS1 and a pseudo signal OS2. 5 is a timing chart showing an output waveform of the amplifier 40 when ′ is input.

16A is a pseudo signal OS1 'approximated to the output waveform of the CCD, FIG. 16B is a pseudo signal OS2' approximated to the output waveform of the CCD, and FIG. 16C is a sample hold 33a.
S / H1 signal input to, and (d) sample and hold 3
It is a timing chart which shows the S / H2 signal inputted into 3b.

FIG. 17 is a block diagram showing a schematic configuration of an electric circuit of a conventional image reading apparatus.

18 is a timing chart showing an output signal of the CCD 9 shown in FIG.

19 is a timing chart showing the relationship between the output signal of the CCD 9 shown in FIG. 17 and the S / H signal, CLMP signal, combined signal, and the like.

[Explanation of symbols]

9: CCD image sensor 20: CCD circuit 21a, b, 31a, b: amplifier 30: signal processing circuit 33a, b, 34a, b: sample hold circuit 37a, b: clamp circuit 38: synthesis circuit 42: A / D converter 61-65, 62B-62D: Pseudo signal generating circuit S1-S8: Changeover switch 75, 80: 1 / n counter 76, 79, 81:
Counter 77: DAC 78: ROM 82: Data selector 100: Image reading device 200: Timing signal generation circuit 300: Controller (CPU) 500: Operation display board 507a to 507
e: Test switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Aihara 4-12-3 Higashi-Kashigaya, Ebina City Ricoh Electronics Co., Ltd. (72) Seiji Toji 4-12-3 Higashi-Kashigaya Ebina City Ricoh Electronic Industry Within the corporation

Claims (3)

[Claims] 1. Image reading means for optically reading image information and outputting odd-order and even-order analog image signals,
And, the analog image signal is amplified by an amplifier circuit, an image signal portion is sampled by a sample hold circuit, a black dummy signal portion is clamped by a clamp circuit, and then the odd-numbered and even-ordered analog image signals are combined by a combining circuit. A / D amplified by amplifier circuit
An image reading apparatus comprising an image signal processing means for converting into a digital image signal by a conversion circuit, a pseudo signal generating means for generating a pseudo reference signal, a means for inputting a test instruction, and an A / D from the image reading means.
The pseudo reference signal is inserted in the signal path up to the conversion circuit, and when the test instruction is given, the pseudo reference signal is provided downstream of this insertion position with respect to the signal flow of the signal path, and when there is no test instruction, the insertion position is given. An image reading apparatus, comprising: a signal switching unit that supplies a signal upstream of the signal to a signal downstream. 2. The image reading apparatus according to claim 1, wherein the signal switching means is inserted between the image reading means and an amplifier circuit immediately after the image reading means. 3. The signal switching means is inserted between the sample hold circuit and the A / D conversion circuit.
The image reading device described.