JPH06164456A - Equalizing equipment for digital communication - Google Patents

Abstract

PURPOSE:To execute equalization by detecting training data without being influenced by a bit slip, with regard to the equalizing equipment in the digital communication equipment. CONSTITUTION:The equipment is constituted by generating a base band signal by receiving and demodulating an input signal by a receiving means 1, generating digital data by A/D-converting this base band signal by an A/D converting means 2, detecting a frame synchronizing pulse obtained by correcting a bit slip from this base band signal by a frame synchronization detecting means 3, storing the digital data in order of generation in an address corresponding to a pointer in accordance with a variation of a pointer value in a memory means 4, saving an address value corresponding to the pointer value at the time when the frame synchronizing pulse is generated by an equalizing means 5, at the time of equalizing this digital data by the equalizing means 5, using the data of prescribed length determined from this address value in the memory means 4 as training data, and equalizing the digital data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer, and particularly to a digital communication device such as a digital mobile radio.
The present invention relates to an equalizer.

In a digital communication device, an adaptive equalizer is used to correct propagation distortion due to fading and delayed propagating waves on the receiving side. In such an adaptive equalizer, initial training is performed using training data. To converge the equalizer.

In an equalizer for digital communication, the influence of bit slip is less likely to occur when determining training data, and the frame utilization efficiency can be improved.
Further, it is desired that data loss is small when re-establishing frame synchronization.

[0004]

2. Description of the Related Art In digital mobile communication waves, propagation distortion occurs due to fading and delayed propagation waves based on reflection. An adaptive equalizer is used to correct the propagation distortion in the received wave on the receiving side. In the adaptive equalizer, initial training of the equalizer is performed with the training data inserted in each time slot for frame synchronization, and after the equalizer is converged, adaptive equalization is started. Then, after the data is equalized, its identification is performed.

In this case, in the conventional training method,
Data is input to the equalizer in synchronization with the frame pulse detected and confirmed one time slot before, and training is performed assuming that the training data is input to a fixed address in the memory, and adaptive equalization is performed. Was going to do.

[0006]

In the conventional training method, the training data is determined from the received data with reference to the frame pulse established one frame before. Therefore, if a bit slip occurs in the received wave, the training data cannot be correctly determined, and as a result, there is a problem that the equalization ability is reduced.

[0007] In digital mobile communication, since a base station which is a communication partner is switched at the time of handoff for shifting from a cell to another cell, it is necessary to resynchronize. In such a case, at least one time slot is required. There was a problem that the data of will be lost.

The present invention is intended to solve such a problem of the prior art. Since the position of the training data can be determined by following the correction of the bit slip of the frame synchronization circuit in real time, the bit slip Improving frame utilization efficiency by making data that is less affected and always present at least after the training data temporally during the time slot in which the first synchronization detection is performed by making it available. In addition, for the same reason, if the frame synchronization is re-established due to frame synchronization loss or handoff, etc.,
It is an object of the present invention to provide an equalizer for digital communication, which can reduce the amount of lost data.

[0009]

(1) An equalizer for digital communication according to the present invention comprises a receiving means 1 for receiving and demodulating an input signal to generate a baseband signal, and an A / D signal for the baseband signal. A / D that converts and generates digital data
The conversion means 2, the frame synchronization detection means 3 for detecting a frame synchronization pulse in which the bit slip is corrected from the baseband signal, and the digital data from the A / D conversion means 2 correspond to the pointer according to the change of the pointer value. Means 4 for storing in the order of occurrence or reverse order
And an equalizing means 5 for equalizing the digital data from the A / D converting means 2, the equalizing means 5 saves the address value corresponding to the pointer value when the frame synchronization pulse is generated, and the memory means 4 Using a fixed length of data determined from this address value in
The digital data from the D conversion means 2 is equalized.

(2) Further, in the present invention according to (1), when the frame synchronization detection means 3 detects a free running counter 38 which generates a pulse having a cycle equal to the frame synchronization pulse and training data is detected in the received data, , A pulse selection circuit 41 for selecting an output pulse of the free-running counter 38 when the pulse determined by this is not detected and the training data is not detected, and the pulse selected by the pulse selection circuit 41 is a frame synchronization pulse. Is output as.

[0011]

FIG. 1 shows the principle of the present invention. In FIG. 1, reference numeral 1 is a receiving means for receiving an input signal, which includes a demodulator. Reference numeral 2 is an analog / digital (A / D) conversion means for converting the received data into digital data. Reference numeral 3 is a frame sync detecting means for detecting a frame sync pulse from the received data. Four
Is memory means for storing the digital data from the A / D conversion means 2. 5 is an equalizing means, which is an A / D
Equalize the digital data from the conversion means 2. An antenna 6 receives an input signal.

The signal input from the antenna 6 is subjected to processing such as amplification, filtering and demodulation in the receiving means 1. The demodulated data is converted from analog data to digital data in the A / D conversion means 2. When the input signal is a quadrature modulated wave and the demodulated data of the receiving means 1 is composed of I and Q components, the A / D conversion means 2
Are A / D converters 2 ₁ and A / D corresponding to the I and Q components.
It is composed of a D converter 2 ₂ and each output is multiplexed by a time division multiplexer (MUX) 2 ₃ to create digital data.

The frame sync detecting means 3 detects the training data in the received data and generates a frame sync pulse. At this time, even if the received data has a bit slip, it is always corrected, Generates a frame sync pulse with corrected bitslip.

Digital data from the A / D conversion means 2 is input to the equalization means 5. The equalizing means 5 sequentially writes the input digital data in the memory means 4 in the order of occurrence or in the reverse order while changing the address for each data.

FIG. 2 explains the writing of digital data. In the memory means 4, I-component digital data I1, I2 ,. Component digital data Q
It is shown that 1, Q2, ... Are written alternately.

A value indicating an address (generally a register having an address value as data) when writing data in a specific memory is called a pointer. First, address N
If the writing of data is started from, the pointer holds the value of N before the first writing, and then changes to the value of N + M. (M is an integer excluding 0 and may be a positive number or a negative number, but "+1" is generally selected.)

When the next data is input, the address N +
This input data is written in M. Data is stored in the memory means 4 by sequentially repeating this operation.

When an interrupt is given to the equalizer 5 by the detection of the frame sync pulse from the frame sync detector 3, the equalizer 5 starts the interrupt process. In the interrupt process, the address value indicated by the pointer at that time is preset to be saved in an arbitrary memory. The equalizing means 5 returns to the normal processing at the end of this interrupt processing.

FIG. 3 shows the flow of processing when an interrupt occurs. The equalizing means 5 saves the address pointed to by the pointer in the memory when the interrupt processing starts, and when the interrupt processing ends, the main processing proceeds. Shown to return to routine.

In the normal process after the end of the interrupt, the equalizing means 5 inputs the data to the memory means 4, calculates the start address and the end address of the time slot at that time, and the A / D converting means. When the data from 2 is written to the end address, the equalization process is started. As input data at this time, data having a maximum length of 1 time slot + α (α is a margin for occurrence of bit slip) is used.

The equalizing means 5 performs equalization processing on the above-mentioned input data by using, as training data, data of a fixed length determined by the saved address from the data stored in the memory means 4.

According to the present invention, while the digital data generated by the A / D conversion is stored in the memory means, the frame synchronization is detected, the training data is detected based on the obtained frame synchronization pulse, and the equalization is performed. Since the processing is performed, it is possible to prevent the equalization ability from being deteriorated due to the influence of the bit slip.

[0023]

FIG. 4 shows an embodiment of the present invention, in which 11 is an antenna, 12 is a receiver (RX) for receiving a high frequency (RF) digital signal from the antenna 11,
Reference numeral 13 is a demodulator for demodulating the received signal to extract a demodulated signal composed of I and Q components, and 14 and 15 are analog-to-digital converters (A) for digitizing the demodulated signals of I and Q components composed of analog data, respectively. / D), 16 is a time division multiplexer (MUX) that multiplexes the respective digital data from the A / D 14, 15, 17 is a microprocessor (MPU), and 18 is a random access memory (RAM).

Further, 19 is a bit timing recovery (BTR) for reproducing a timing signal from the demodulated signal, 20,
Reference numeral 21 is a discriminator for discriminating the I component and Q component demodulated signals, 22 is a decoder for decoding the discrimination data of the discriminators 20 and 21, and 23 is a frame synchronization detector for generating a frame synchronization signal from the decoded signals. Is.

The quadrature-modulated RF digital signal is received by the RX 12 via the antenna 11 and subjected to processing such as band limitation, amplification and frequency conversion to generate a reception signal. The received signal is subjected to quadrature detection and demodulation in the demodulator 13, the I component and the Q component are extracted, and converted into digital data in the A / Ds 14 and 15, respectively. The respective digital data outputs of the A / Ds 14 and 15 are multiplexed in the MUX 16 and input to the RAM 18 via the MPU 17. In addition, MPU17
May be a digital signal processor (DSP).

On the other hand, the demodulated signal of I component or Q component from the demodulator 13 is input to the BTR 19. BTR19
Extracts the timing of the input data from this, and
Operation clocks CLK1 and CLK2 that determine sample timings in D14 and 15 and discriminators 20 and 21
And the operation clock CLK3 in the MUX 16 are supplied.

The demodulated signals of the I component and the Q component from the demodulator 13 are added to the discriminators 20 and 21. Discriminator 2
0 and 21 are clocks C generated by the BTR 19.
I component and Q from the demodulator 13 using LK1 and CLK2
Identify the demodulated signal of the component. The identified data is differentially encoded in decoder 22 to produce an encoded signal.

The frame sync detector 23 establishes frame sync by detecting training data from the coded signal and generates a frame sync signal. The frame synchronization signal is given to the interrupt terminal as an interrupt signal (IRQ) to the MPU 17.

The MPU 17 is set to input the multiplexed data from the MUX 16 in the normal processing. The start address of the area where the input data is to be stored is set in the pointer register as an initial value, and the value of the pointer register is incremented by 1 each time data is written.

In the interrupt processing, the value of the pointer register is saved in the dedicated address, and the interrupt ends. After the interruption, in the normal process, while inputting the data, the start address of the own time slot data and the end address are calculated, the data from the MUX 16 is written to the end address, and the detected training data is detected. To start the equalization process. As input data, data of a maximum length of 1 time slot + α (α is a margin for a case where a bit slip occurs) is stored.

FIG. 5 shows an example of the structure of the frame synchronization detector, in which 31 is a register, 32 is a shift register, 33 _1, 33 _2, 33 _3, 33 ₄ are exclusive OR circuits (EOR). ), 34 are parallel-to-serial converters (P /
S), 35 is a counter, 36 is a magnitude comparator (MC) for comparing the magnitude of the input and the set value, 3
Reference numeral 7 is a reference oscillator, 38 is a free-running counter, 39 is an AND circuit, 40 is an aperture gate signal generator that generates an aperture gate signal of a predetermined width according to a trigger signal, and 41 is a pulse selection circuit.

An inverted pattern of training data is set in the register 31. The input data is input to the shift register 32. EOR33 _1, 33 _2, 33 _3, 3
By 3 _4, by comparing the input pattern of setting pattern and the shift register 32 of the register 31, the output of the comparison result of each EOR, and converted into serial data by P / S34, and outputs.

This serial data is counted by the counter 35, and the count value is M. A high level pulse is generated when the counter value is larger than the set value as compared with the preset value in C36. The output signal of the reference oscillator 37 is counted by the free-running counter 38, and when the count value reaches a certain value, a high level pulse is output.

In the AND circuit 39, the M.M. A pulse obtained by gating the output of C36 with the aperture gate signal is output. This signal and the output pulse of the free-running counter 38 are input to the pulse selection circuit 41. Since the high-level output of the AND circuit 39 indicates the detection of a normal frame synchronization pulse, the pulse selection circuit 41 selects this pulse when the output pulse of the AND circuit 39 is generated, and the AND circuit 39 outputs the selected pulse. When no output pulse is generated, the output pulse of the free-running counter 38 is selected and the frame pulse is output.

The aperture gate signal generator 40 outputs a pulse of a certain time width as an aperture gate signal at the position where the generation of the next frame sync pulse is predicted from the generation of the frame pulse. Pulse selection circuit 4
1 is the AND circuit 39 after the end of the aperture gate signal.
Since the presence or absence of the output pulse is determined and the selection of the input is switched, the output of the frame pulse from the pulse selection circuit 41 has a certain delay. The free-running counter 38 is reset by a frame pulse and generates an output pulse having a cycle equal to that of the frame sync pulse, but its timing is set to the same timing as the regular frame sync pulse in consideration of the delay in the pulse selection circuit 41. Is determined to be.

Therefore, according to the frame synchronization detector shown in FIG. 5, when the normal frame synchronization pulse is not output due to the occurrence of the bit slip, the output of the free-running counter 38 is output as the frame pulse. , It is possible to output a frame pulse with corrected bit slip. This frame pulse is used as an interrupt signal for the MPU 17 described above.

FIG. 6 is a diagram for explaining the occurrence of a bit slip. (A) shows the output data of the demodulator, (b) shows the regular sample clock signal, and (c) shows the sample clock signal by the BTR output. Shown respectively.

As mentioned above, in the BTR 19, A /
The sample timings of D14, 15 and the discriminators 20, 21 are reproduced. At this time, since the output clock frequency of the BTR 19 is determined from the zero cross point of the demodulated signal, B
The frequency of the sample timing signal output from TR19 may gradually shift compared to the normal case shown in (b).

In FIG. 6C, therefore, it is shown that the demodulated data should be sampled once, but should be sampled a plurality of times or 0 times. In such a case, the output data may have extra data, or the required data may be lacking. Figure 6
In (c), A indicates the occurrence of bit slip, and shows the case where the frequency is higher than that in (b).

Further, when the next frame synchronization is taken with the BTR frequency kept as such, the sampling timing of the BTR output gradually shifts, so that there is a shift between the frame pulse by the free-running counter and the detected frame pulse. Will occur.

In the method of the present invention, even if such a bit slip occurs, the frame sync pulse can be correctly generated from the frame sync detection circuit, so that the training data can be correctly detected without being affected by the bit slip. Then, the equalization process can be performed.

[0042]

As described above, according to the present invention, the position of the training data can be determined by generating the frame synchronization pulse in real time following the correction of the bit slip in the frame synchronization circuit. It is possible to improve the equalization ability without being affected by the bit slip.

Further, according to the present invention, data existing at least after the training data temporally in the time slot in which the first synchronization detection is performed is always available, so that the frame utilization efficiency is improved. Therefore, the data required at the time of rising can be received earlier.

For the same reason, it is possible to reduce the amount of data lost when frame synchronization is re-established due to frame synchronization loss or handoff.
At the time of handoff, if the frame synchronization between the base stations matches to some extent, it is possible to reduce the lost data to zero.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram illustrating writing of digital data.

FIG. 3 is a diagram showing a flow of processing when an interrupt occurs.

FIG. 4 is a diagram showing an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example of a frame synchronization detector.

FIG. 6 is a diagram illustrating the occurrence of bit slip,
(A) shows the output data of the demodulator, (b) shows the regular sample signal, and (c) shows the sample signal by the BTR output.

[Explanation of symbols]

 1 receiving means 2 A / D converting means 3 frame synchronization detecting means 4 memory means 5 equalizing means

Claims (2)

[Claims] 1. A receiving means (1) for receiving and demodulating an input signal to generate a baseband signal, and an A / D converting means (2) for A / D converting the baseband signal to generate digital data. And frame synchronization detecting means (3) for detecting a frame synchronization pulse whose bit slip is corrected from the baseband signal.
A memory means (4) for storing the digital data at an address corresponding to the pointer according to a change in the pointer value in the generation order or the reverse order, and an equalization means (5) for equalizing the digital data. The equalizing means (5) saves the address value corresponding to the pointer value at the time of generating the frame synchronization pulse, and uses the data of a fixed length determined from the address value in the memory means (4) as training data. An equalizer for digital communication, which equalizes the digital data. 2. A free-running counter (38) for generating a pulse having a period equal to that of a frame-synchronization pulse, and a pulse determined by the training data when the training data is detected in the received data. And a pulse selection circuit (41) for selecting an output pulse of the free-running counter (38) when the training data is not detected, and outputs the selected pulse as a frame synchronization pulse. The equalizer for digital communication according to claim 1, wherein: