JPH06164260A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To eliminate the effect of the base current of a transistor TR to the compensation for the base current of a current mirror by reducing the base current. CONSTITUTION:The emitters of the 1st and 2nd PNP TRs 1 and 2 are connected to a high potential power supply 5, and the bases of both TRs 1 and 2 are connected to the drain of an N-channel MOS FET 4. Then the collector of the TR 1, the gate of a TR 4, and an input terminal 11 are connected to the high potential side of a constant voltage source 6. The low potential side of the source 6 and the source of the TR 4 are connected to a low potential power supply 10. Then the collector of the TR 2 is connected to an output terminal 7. Under such conditions, no current flows to the gate of the TR 4. Thus the conventional current difference that is caused when the electrical characteristics are equal to each other between both TRs 1 and 2 is substantially set at zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mirror circuit, and more particularly to a current mirror circuit integrated into a semiconductor.

[0002]

2. Description of the Related Art As a conventional current mirror circuit, a circuit as shown in FIG. 5 is generally used. 5, in the conventional current mirror circuit, the emitters of the PNP type transistors 1 and 2 are connected to the high-potential-side power source 5, and the bases are commonly connected to the collector of the NPN type transistor 3 so that the PNP transistor 1 Collector and above N
The base of the PN transistor 3 together with the input terminal 11
It is connected to the high potential side of the constant voltage source 6, the low potential side of the constant voltage source 6 and the emitter of the NPN type transistor 3 are connected to the low potential side power source 10, and the collector of the PNP type transistor 2 is connected to the output terminal 7. It is connected.

[0003]

In the conventional current mirror circuit, a difference occurs between the current I6 flowing through the constant voltage source 6 and the current I7 flowing through the output terminal 7. Now, assuming that the electrical characteristics of the PNP transistors 1 and 2 are equal, the base current of the transistor 1 is IB, the collector current is IC, the forward current amplification factor is hFE, and these are equal to the transistor 2. When the base current of the NPN transistor 3 is IB ', the collector current is IC', and the forward current amplification factor is hFE ', the following equations (1) to (4) are obtained.

IB = IC / hFE = I7 / hFE (1) IB ′ = IC ′ / hFE ′ (2) IC ′ = 2 · IB (3) I7 = I6 + IB ′ (4) The above (4) By transforming the equation, the above (2), (3),
By substituting the equation (1) in order, the following equation (5) is obtained.

I7−I6 = IB ′ = 2 · IC / hFE ′ · hFE = 2 · I7 / hFE ′ · hFE (5) Therefore, only 2 · I7 = hFE ′ · hFE, and I6 is I7
Fewer. It is desirable that there is no difference in design. It is an object of the present invention to provide a current mirror circuit in which such a difference does not occur.

[0006]

According to a first configuration of a current mirror circuit of the present invention, the bases of first and second transistors are commonly connected, and the emitters thereof are both connected to a first constant potential source. The collector of the second transistor serves as an output terminal, the collector of the first transistor serves as an input terminal, a constant voltage source is connected between the input terminal and a second constant potential source, and a drain or a source is provided. Is provided at a common connection point between the bases, and a field effect transistor having a gate connected to the input terminal and a source or a drain connected to the second constant potential source is provided.

A second configuration of the current mirror circuit of the present invention is the current mirror circuit described above, wherein the emitters of the first and second transistors are respectively connected to the first constant potential source via resistors. It is characterized by having done.

[0008]

The present invention will be described below with reference to the drawings. 1 is a circuit diagram showing a current mirror circuit according to a first embodiment of the present invention.

Referring to FIG. 1, in the current mirror circuit of this embodiment, the emitters of the first and second PNP type transistors 1 and 2 are connected to a high potential side power source 5, and the bases of the transistors 1 and 2 are both N-channel. It is connected to the drain of the MOS field effect transistor 4, the collector of the transistor 1, the gate of the transistor 4 and the input terminal 11 are connected to the high potential side of the constant voltage source 6, and the low potential side of the constant voltage source 6 and the transistor 4 are connected. The source of is connected to the power supply 10 on the low potential side,
The collector of the transistor 2 is connected to the output terminal 7.

Since no current flows into the gate of the MOS transistor 4, when the electric characteristics of the first and second PNP transistors 1 and 2 are the same, the constant voltage source 6 and the output terminal 7 which have been generated in the conventional example are connected. Difference of the currents flowing through IB '=
2 · I7 / hFE′hFE (Equation (5)) becomes almost zero.

FIG. 2 is a circuit diagram showing a current mirror circuit according to the second embodiment of the present invention. In FIG. 2, the operation of the current mirror circuit of this embodiment is similar to that of the first embodiment, but in the second embodiment, the high potential side and high potential side power supply of the NPN bipolar transistors 1 and 2 are used. And resistors 8 and 9 are respectively connected between and. This has the effect of making the current mirror circuit stronger against noise.

FIG. 3 is a circuit diagram showing a current mirror circuit according to a third embodiment of the present invention. In FIG. 3, the present embodiment has a circuit configuration in which the PNP transistors 1 and 2 of FIG. 1 are NPN transistors 1'and 2'and the N-channel MOS transistor 4 is a P-channel MOS transistor 4 '. This operation is similar to that of FIG.

FIG. 4 is a circuit diagram showing a current mirror circuit according to a fourth embodiment of the present invention. In FIG. 4, the present embodiment has a circuit configuration in which the PNP type transistors 1 and 2 in the circuit of FIG. 2 are NPN type transistors 1'and 2'and the N channel type is a P channel type MOS transistor 4 '. is there. This operation is similar to that of FIG.

[0014]

As described above, the present invention has the effect of eliminating the influence of the base current of the transistor for compensating the base current of the current mirror by using the structure for reducing the base current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a current mirror circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional current mirror circuit.

[Explanation of symbols]

 1, 2 PNP type transistor 1 ′, 2 ′ NPN type transistor 3 NPN type transistor 4 NMOS transistor 4 ′ PMOS transistor 5 High potential side power source 6 Constant voltage source 7 Output terminal 8, 9 Resistor 10 Low potential side power source 11 Input terminal

Claims (4)

[Claims] 1. The bases of the first and second transistors are commonly connected to each other, the emitters thereof are both connected to a first constant potential source, and the collector of the second transistor serves as an output terminal. A collector of the transistor is used as an input terminal, a constant voltage source is connected between the input terminal and a second constant potential source, a drain or a source is a common connection point between the bases, and a gate is the input terminal. A current mirror circuit comprising field effect transistors each having a source or a drain connected to the second constant potential source. 2. The current mirror circuit according to claim 1, wherein the emitters of the first and second transistors are respectively connected to the first constant potential source via resistors. Current mirror circuit. 3. The current mirror circuit according to claim 1, wherein the first and second transistors are PNP type, and the field effect transistor is an N channel type. 4. The current mirror circuit according to claim 1, wherein the first and second transistors are NPN type and the field effect transistors are P channel type.