JPH06162798A - Dynamic ram - Google Patents

Abstract

PURPOSE:To quickly perform the test without increasing the external terminals by discriminating a required combination of external control signals to set the test mode and detecting coincidence/discordance of a read signal consisting of plural bits. CONSTITUTION:An FF is set by a timing generating circuit TG, which lets a column address strobe signal CAS and a write enable signal WE be at a low level at the falling timing of a row address strobe signal RAS, to let a test mode signal TE be H. Test circuits included in a data input circuit DIB and a data output circuit DOB respectively are made to be in the operating state, and coincidence/discordance at each bit for 4-bit data read out from a memory cell array (x4) M-ARY is detected by the test circuit of the circuit DOB; and if discordance of even one bit is detected, the corresponding output signal is sent to an external terminal DOUT. By this constitution, it is unnecessary to increase the external terminals, and the test speed is improved in the unit of plural bits.

Description

Detailed Description of the Invention

[0001]

This invention relates to a dynamic RA
About M (random access memory), for example, about 4
The present invention relates to a technique effectively used for a device having a large storage capacity such as M bits.

[0002]

2. Description of the Related Art With the progress of semiconductor technology, a dynamic RAM having a large storage capacity of about 1 Mbit has been developed. The test time increases as the storage capacity increases. Therefore, a test circuit is provided inside the RAM, the same signal is written in the memory array in units of x4 bits, and even if any one of the x4 bit signals read from the memory array is used, If there is a mismatch, the output terminal is put in a high impedance state. If all of the x4 bit read signals are high level or low level, a high level or low level signal is output from the output terminal (Mitsubishi Electric Corporation, 1985, "Mitsubishi Technique").
See Vol.59, No.9).

[0003]

In the above test method, one empty pin of the 18-pin package is used to distinguish between the normal mode and the test mode, and the test circuit is set to the operating state. To do. Therefore, if a dynamic RAM having a large storage capacity of about 4 Mbits is mounted on the 18-pin package, the empty pins will be used as address terminals. Therefore, the test method is used. Can not.

An object of the present invention is to provide a dynamic RAM which can shorten the test time without increasing the number of external terminals.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, it is determined that the column address strobe signal and the write enable signal are at the low level at the falling timing of the row address strobe signal, and the test mode is set.

[0007]

According to the above-mentioned means, by the combination of the external control signals required in the normal access,
Since the test mode can be set, the test time can be shortened without increasing the number of external terminals.

[0008]

FIG. 2 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied.

In this embodiment, although not particularly limited, the memory array M-ARY consists of x4. Each memory array has a storage capacity of about 1 Mbit. Therefore, the RAM of this embodiment has a large storage capacity of about 4 Mbits in total.
The column system (data line) signal line of the memory array M-ARY is composed of a pair of complementary data lines arranged in parallel, and is not particularly limited, but four pairs of complementary data lines corresponding to the four memory arrays are one. In the same figure, they are configured as a set and are configured by a two-intersection method (folded bit line or digit line method) arranged so as to extend in the lateral direction. 4 above
The pair of complementary data lines are four pairs of common complementary data lines CDLB0, CDLB1, CD which run in parallel in the vertical direction through a column switch circuit CSW which receives a column selection signal described later.
It is bound to LB2 and CDLB3. In the figure,
Non-inverted common data line CD0 and inverted common data line CDUB
Together with 0, they are represented as a common complementary data line CD0.

The column decoder C-DCR decodes internal complementary address signals ay0 to ayn _{- 1} which will be described later, and in synchronization with a data line selection timing signal (not shown), four pairs of complementary data lines corresponding to the above four pairs. Common data line CDLB0
~ Form a column select signal to be coupled to CDLB3.
The internal complementary address signals ay0 to ayn _-1 are
It comprises a non-inverted address signal having the same phase as the address signal supplied from the external terminal and an inverted address signal having the opposite phase. This also applies to the internal address signal in the following description and drawings.

Row related address selection lines (word lines, dummy word lines) are arranged in the respective memory arrays M-ARY so as to extend in the vertical direction. The sense amplifier SA is
At the time of write / read operation and refresh operation,
A minute read voltage from a memory cell which is activated by a sense amplifier timing signal (not shown) and is coupled to one data line by a word line selection operation is coupled to the other data line by a dummy word line selection operation. The complementary data line is amplified to a high level / low level with reference to the reference voltage from the dummy cell.

The row address buffer R-ADB receives the address signal AX supplied in synchronization with the row address strobe signal RASUB, and receives the internal complementary address signal ax.
0 to axn are formed. The complementary address signals ax0 to ax0
A specific bit of axn, for example, the most significant bit ax
The complementary address signals ax0 to ax _n-1 excluding n are sent to the next row address decoder R-DCR. The row address decoder R-DCR receives the complementary address signal a.
Decoding x0 to ax _n-1 forms a selection signal for one word line and a dummy word line in synchronization with a word line selection timing signal (not shown).

The column address buffer C-ADB receives the address signal AY supplied in synchronization with the column address strobe signal CASSUB and forms internal complementary address signals ay0 to ayn. The complementary address signal ay
Among the 0 to ayn, the complementary address signals ay0 to ayn _-1 excluding a specific bit, for example, the most significant bit ayn are
It is sent to the column address decoder C-DCR.

Address signal axn of each of the most significant bits
And ayn are supplied to the decoder circuit DEC. The decoder circuit DEC forms a selection signal to be supplied to a multiplexer MPX provided in each of an input circuit and an output circuit of a signal described later.

The column switch CSW receives the selection signal formed by the column address decoder C-DCR, and receives the selection signal formed by the column address decoder C-DCR and the four pairs of common complementary data lines CDLB corresponding to the four pairs of complementary data lines in the memory array M-ARY.
0, CDLB1, CDLB2 and CDLB3 respectively.

The common complementary data lines CDLB0 to CDL
B3 is coupled to the input terminals of main amplifiers MA0-MA3, respectively. These main amplifiers MA0 to MA3
Is activated by a main amplifier timing signal (not shown) to amplify the signals on the common complementary data lines CDLB0 to CDLB3. These main amplifiers MA0 to MA3
Of the output signal is alternately transmitted to the input terminal of the data output circuit DOB through the multiplexer MPX controlled by the selection signal formed by the decoder circuit DEC. The data output circuit DOB is activated by a timing signal generated during the read operation in which the write enable signal WEUB is set to the high level, amplifies the input signal and sends it to the external terminal D _OUT . As a result, the read operation is performed in units of × 1 bit.

The common complementary data lines CDLB0 to CDL
B3 is coupled to the output terminal of the data input circuit DIB via the multiplexer MPX. This multiplexer M
PX is controlled by a selection signal formed by the decoder circuit DEC, and the common complementary data lines CDLB0 to CDLB0 to which the output signal of the data input circuit DIB selectively corresponds.
Tell CDLB3. The data input circuit DIB is activated by a timing signal generated later than the operation timing signal of the main amplifier MA in the write operation of the write enable signal WEUB at a low level, but is not particularly limited, and is supplied from the external terminal D _in. The write signal thus generated is transmitted via the multiplexer MPX to the pair of common complementary data lines CDLB0 to CDLB.
Tell 3. As a result, the write operation is performed in units of × 1 bit.

The timing generation circuit TG has three external control signals RASUB (row address strobe signal) and C.
ASUB (column address strobe signal) and WEU
Upon receiving B (write enable signal), the above various timing signals necessary for the memory operation are formed and transmitted.

In this embodiment, in order to shorten the test time of the dynamic RAM having a large storage capacity as described above, the data input circuit DIB and the data output circuit D are used.
A test circuit is built in the OB. When the test circuit included in the data input circuit DIB is in the operating state, all the multiplexers MPX are in the selected state and the write signal supplied from the external terminal D _in is transmitted to the common complementary data lines CDLB0 to CDLB3. This brings the memory array M-ARY into the selected state.
The same signal is simultaneously written in two memory cells.
That is, in the test mode, it is apparently performed in a unit of × 4 bits. The test circuit included in the data output circuit DOB is not particularly limited, but a circuit that receives the output signals of the main amplifiers MA0 to MA3 and detects the match / mismatch of the read signal of 4 bits, and the detection output A corresponding output signal is formed and the external terminal D _out
To be sent to. As a result, the read operation can be performed in the unit of apparent × 4 bits. Although not particularly limited, the test circuit forms a high-level or low-level output signal when the read signals of 4 bits match at high level or low level. If even one bit of the read signal consisting of 4 bits does not match, as described above, the output terminal D
_{Set out} to high impedance. Instead of such a high impedance, as the output signal in the case of the above disagreement, a signal at an intermediate level between the read high level and the low level may be output.

The activation and cancellation of the test circuit as described above are
The operation mode identification output included in the timing generation circuit TG is controlled by the test signal TE obtained from the output of the latch circuit FF which is set / reset. For example, if the test signal TE is at high level, the test circuits included in the data input circuit DIB and the data output circuit DOB are activated, and if the test signal TE is at low level, the test circuits are deactivated. It As a result, switching between the test mode and the normal mode is performed, and activation / cancellation of the test mode will be described below with reference to the timing chart shown in FIG.

At the timing when the row address strobe signal RASUB falls from the high level to the row address strobe signal, the column address strobe signal CASUB and the write enable signal WEUB are set to the low level. The timing generation circuit TG identifies this and supplies a one-shot pulse to the latch circuit FF. As a result, the latch circuit FF is set and the test signal is set to the high level. That is, only the test mode is set in this memory cycle. For example, when the dynamic RAM has an internal refresh circuit of the CAS Bifower RAS refresh system, the refresh operation is performed in parallel with the setting of the test mode because of the relationship between the address strobe signals RASUB and CASUB. If inconvenience occurs due to the setting of the test mode and the refresh mode being performed in parallel, the write enable signal WEUB
The refresh mode may be prohibited depending on the low level. The write / read operation for the actual test is performed by the signals RASUB and CASU.
Although not shown, the row address strobe signal RASUB is set to the low level, the row address signal AX is taken in, and then the column address strobe signal CASUB is set to the low level, although not shown, after the B is once set to the high level to reset the RAM. This is performed by taking in the column address signal AY. At this time, when the write enable signal WEUB is set to the low level, the test circuit is brought into the operating state as described above by the high level of the test signal TE, so that it is apparently × 4.
Writing is done in bit units. Further, when the write enable signal WEUB is set to the high level, the test circuit is put into the operating state as described above by the high level of the test signal TE, so that the reading is apparently performed in the unit of × 4 bits.

The latch circuit FF, which is not particularly limited, uses a master / slave flip-flop circuit,
It is composed of a binary counter circuit. In this case, the row address strobe signal RAS is again generated as shown in FIG.
At the timing when UB falls from the high level to the row address strobe signal, the column address strobe signal CASSUB and the write enable signal WEUB are set to the low level, and a one-shot pulse is supplied from the timing generation circuit TG to reset the latch circuit FF. Be seen. As a result, the test signal TE can be set to the low level, and the subsequent operation can be set to the normal mode.

Further, as shown by a dotted line in the figure, the test control circuit TC is provided to supply a signal from the address terminal. The test control circuit TC sets the column address strobe signal CASUB and the write enable signal WEUB to the low level at the timing when the row address strobe signal RASUB falls from the high level to the row address strobe signal, and the timing generation circuit TG.
When a one-shot pulse is sent from the device, the signal from the specific address terminal at that time is fetched. For example,
If the signal supplied from the address terminal is at high level, the test circuit is activated, and if it is at low level, it is released. In addition to such activation / cancellation of the test mode, for example, in a test circuit included in the data output circuit DOB, a mismatched output signal is provided with two output functions of high impedance and intermediate level,
It may be made to select it according to the address signal. By adding the selection function of the above output functions, it is possible to switch the mismatch output signals according to the tester used. Further, when the dynamic RAM is mounted on the memory board, the output terminal D _out is connected by a data bus on the board in a wired OR configuration. Since the signal in the previous operation cycle remains on this data bus, it is difficult to identify if the mismatch output is sent by the output high impedance. Therefore, in the test of the dynamic RAM on the memory board, switching to the intermediate level output may be performed.

The operational effects obtained from the above embodiment are as follows. That is, (1) the combination of the row address strobe signal, the column address strobe signal, and the write enable signal, which is not in the normal mode, can activate / cancel the test mode without increasing the number of external control signals. can get.

(2) By the above (1), a dynamic RAM having a large storage capacity of about 4 Mbits can be accommodated in an 18-pin package. by this,
The effect that the compatibility with the dynamic RAM having a storage capacity of 1 Mbit can be achieved while adding the test function is obtained.

(3) Combining the address signal with the row address strobe signal, the column address strobe signal, and the write enable signal makes it possible to easily activate / cancel the test mode and add a test function having a plurality of modes. The effect of being able to be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
A dynamic RAM to which the present invention is applied has a nibble mode function of serially outputting a signal read in parallel from the memory array in units of a plurality of bits by a signal changed in synchronization with a column address strobe signal. It may be one. In this case,
The address signal supplied to the decoder circuit DEC may be changed by the shift register or the address counter circuit. Further, the specific configuration of the memory array M-ARY is such that the number of memory cells coupled to the word line and / or the data line is reduced to increase the speed and secure a level margin of a read signal from the memory cell. Therefore, the memory mat may be composed of a plurality of memory mats.

The number of memory cells selected by the addressing of the memory array, in other words, the number of common complementary data lines is 8 bits in addition to the above 4 bits.
Any number of bits may be used, such as 16 bits. Furthermore, the present invention may be applied to a dynamic RAM having a storage capacity of about 1 Mbit or 256 kbit, and when a vacant pin occurs, it is used for another operation mode. The present invention is directed to the address-type dynamic RAM having a built-in test circuit.
Widely available to.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the combination of the row address strobe signal, the column address strobe signal, and the write enable signal, which is not in the normal mode, is used to activate the test mode without increasing the number of external control signals.
It will be possible to cancel.

[Brief description of drawings]

FIG. 1 is a timing chart for explaining an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

[Explanation of symbols]

M-ARY ... Memory array, SA ... Sense amplifier, C
SW ... Column switch circuit, R, C-ADB ... Address buffer, R-DCR ... Row address decoder, C
-DCR ... column address decoder, DEC ... decoder, MA0-MA3 ... main amplifier, MPX ... multiplexer, DOB ... data output circuit, DIB ... data input circuit, TG ... Timing generation circuit, FF ... Latch circuit, TC ... Test control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsutaka Kimura 1-280, Higashi-Kengikubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] 1. A memory array having a plurality of memory cells, an address selecting circuit for selecting the plurality of memory cells, and one memory cell among the plurality of memory cells selected in the normal mode. And the input / output circuit for selectively transmitting and receiving data, and writing the same data to the plurality of memory cells in the test mode, detecting the match / mismatch of the stored information of the plurality of memory cells and detecting it from one output terminal. And a test output circuit for outputting, wherein the test mode is set by identifying that the column address strobe signal and the write enable signal are at a low level at the falling timing of the row address strobe signal. Dynamic RAM.