JPH06162774A - Multiport ram - Google Patents

Abstract

PURPOSE:To output a warning at the time of simultaneous data write from different write ports to the same memory cell. CONSTITUTION:Transistors(TRs)12 and 13 are provided which have gates connected to first and second word lines WWL1 and WWL2 and are connected in series between a node 15 and an earth 11. A TR 14 connected between the node 15 and a power source 10 is provided to pull up the potential of the node 15. An inverter 16 whose input terminal is connected to the node 15 is provided to invert and output the potential of the node 15. Thus, the potential of the input terminal of the inverter 16 is set to the low level by TRs 12 and 13 and the output of the inverter 16 is changed from the low level to the high level when first and second word lines WWLI and WWL2 are simultaneously activated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiport RAM having a plurality of write ports, and more particularly to protection of data written from a plurality of ports.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a memory cell for 1 bit in a conventional multiport RAM having two ports for writing and two ports for reading. In the figure, reference numerals 1 and 2 denote inverters, and the inverters 1 and 2 connect an output terminal and an input terminal to each other to form a data latch. Reference numeral 3 is an inverter for connecting the output terminal of the inverter 1 to read the data held in the data latch. Reference numeral 4 is for connecting one electrode to the output terminal of the inverter 3 and the other electrode for the first reading. An N-channel MOS transistor 5 connected to the bit line RBL1 and having a gate electrode connected to the first read word line RWL1 to operate as a read access gate has one electrode connected to the output terminal of the inverter 3 and the other electrode connected to the first electrode. Two
, An N-channel MOS transistor connected to the read bit line RBL2 and having its gate electrode connected to the second read word line RWL2 to operate as a read access gate. 6 has one electrode connected to the input end of the inverter 1 and the other An N-channel MOS transistor having an electrode connected to the first write bit line WBL1 and a gate electrode connected to the first write word line WWL1 to operate as a write access gate. Reference numeral 7 has one electrode having an input terminal of the inverter 1. To the second write bit line W.
It is an N-channel MOS transistor which is connected to BL2 and whose gate electrode is connected to the second write word line WWL2 to operate as a write access gate. The inverters 1 to 3 and the transistors 4 and 5 form one memory cell MC.

FIG. 4 is a diagram showing a memory cell of a multi-port RAM with four ports disclosed in Japanese Patent Laid-Open No. 03-263687. This figure shows a multi-port RAM to which a column selection transistor is applied. Two memory cells are shown. 4, MCa and MCb are left column side memory cells and right column side memory cells configured similarly to the memory cell shown in FIG. 3, and RBL1a and RBL2a are first read bit lines of the left column side memory cells. And second read bit lines RBL1b and RBL2b are the first read bit line and the second read bit line of the memory cell on the right column side, and 8a is one electrode of the transistor 6 and the inverter of the memory cell MCa. 1. An N-channel MOS transistor for column selection, which is inserted between the input terminal of 1 and is connected in series and whose gate electrode is connected to the column selection signal line CWE1a,
8b is an N-channel MOS transistor inserted between one electrode of the transistor 6 and the input terminal of the inverter 1 of the memory cell MCb, connected in series, and having a gate electrode connected to the column selection signal line CWE1b, and 9a is one of the transistors 7. An N channel MOS transistor inserted between the electrode and the input terminal of the inverter 1 of the memory cell MCa, connected in series, and having a gate electrode connected to the column selection signal line CWE2a, 9b is one electrode of the transistor 7 and the memory cell MC
It is an N-channel MOS transistor which is inserted between the input terminal of the inverter 1 and the input terminal of the inverter 1 and connected in series, and the column selection signal line CWE2b is connected to the gate electrode.

First, in writing data to the memory cell MC shown in FIG. 3, the first write word line WWL1 is used.
Is set to an H level potential to turn on the transistor 6 and the write is performed through the first write bit line WBL1. Similarly, the second write word line WWL
It is also possible to write data to the memory cell MC through the second write bit line WBL2 by turning on the transistor 7 by setting 2 to the H level potential.

Next, the data held in the memory cell is read by activating each word line of the read port. That is, when the first or second read word line RW1, RW2 is set to the H level potential, the transistor 4 or the transistor 5
Is turned on and is read out through the first or second read bit line.

Next, in the multi-port RAM shown in FIG. 4, first, in writing data to the memory cell MCa on the left column side, the first write word line WWL1 is set to the H level potential and the column select signal line CWE1a. Is set to the H level potential, the transistors 6 and 8a are simultaneously turned on, and this can be performed through the first write bit line WBL1.

Similarly, the data writing to the memory cell MCa is also performed by setting the second write word line WWL2 and the column selection signal line CWE2a to the H level potential at the same time to turn on the transistors 7 and 9a. This can be done through two write bit lines WBL2.

Data is written to the memory cell MCb on the right column side by simultaneously setting the first word line WWL1 and the column selection signal line CWE1b to the H level potential and simultaneously turning on the transistors 6 and 8b. This can be performed through the first write bit line WBL1.

Similarly, for writing data to the memory cell MCb, the second word line WWL1 and the column selection signal line CW are used.
E2b is set to H level potential at the same time, and transistors 7 and 9 are connected.
It can also be performed through the second write bit line WBL2 by simultaneously turning on b.

The read operation can be performed in the same manner as the multiport RAM shown in FIG. In the memory cell MCa on the left column side, the first or second read word line RWL1, RWL2 is activated to activate the first or second read bit line RBL1a, RB.
Read data through L2a. Right column memory cell M
In Cb, the first or second read word line RWL1, RWL2 is activated and data is read through the first or second read bit line RBL1b, RBL2b.

[0011]

[Problems to be Solved by the Invention] Conventional multi-port R
Since the AM is configured as described above, the first and second
Even if the word lines WWL1 and WWL2 are simultaneously activated and the data is written to the same memory cell at the same time and the data in the memory cell cannot be written normally, the abnormal state cannot be detected. There is a problem that data is destroyed, such as erroneous data being held and read from the memory cell.

The present invention has been made to solve the above problems, and an object thereof is to detect the same memory cell when writing is simultaneously performed from a plurality of ports, The purpose is to avoid using corrupted data by using the detected results.

[0013]

A multiport RAM according to a first aspect of the present invention is a multiport RAM having a plurality of write ports, which are provided corresponding to a plurality of the write ports, respectively. A write signal is simultaneously applied to a plurality of word lines connected to respective control terminals of a plurality of gates for selecting a memory cell and at least two word lines connected to the plurality of word lines and connected to the word lines. Simultaneous writing warning means for outputting a signal for warning simultaneous writing when transmitted is configured.

The multiport RAM according to the second invention is
A multi-port RAM having a plurality of write ports, the plurality of word lines provided corresponding to the plurality of write ports and connected to respective control terminals of a plurality of gates for selecting the same memory cell. And a column for selecting a memory cell of a specific column to write data from among memory cells of a plurality of columns in a row selected by the corresponding word line. A write signal is simultaneously transmitted to a plurality of column address signal lines for transmitting an address signal, the plurality of word lines and the plurality of column address selection lines, and at least two of the connected word lines simultaneously have the word lines. Is
And at least two of which the write signals are simultaneously transmitted
When a column address signal for selecting the same column is transmitted to a column address signal line corresponding to the word line of the book, a simultaneous write warning means for outputting a signal for warning simultaneous write is provided.

[0015]

The simultaneous writing warning means in the first invention is
Write signals are simultaneously transmitted to the word lines of multiple gates connected to the same memory cell, and simultaneous write is performed when simultaneous data write such that simultaneous write is performed from multiple ports to the same memory cell occurs. Since the warning signal is output, it is possible to know from the signal output from the simultaneous writing warning means that the simultaneous writing of data has occurred.

The simultaneous write warning means in the second aspect of the present invention simultaneously accesses the same memory cell from a plurality of ports by the word lines and the column address signal lines of the plurality of gates connected to the same memory cell, thereby simultaneously accessing the same memory cell. If there is, a signal for warning simultaneous writing is output, so that it is possible to know that simultaneous writing of data has occurred by the signal output by the simultaneous writing warning means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A multiport RAM according to a first embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1
Reference numeral 0 indicates a power supply, 11 indicates grounding, 14 is an N-channel MOS transistor for pulling up in which the drain electrode and the gate electrode are connected to the power supply 10, 13 is the source electrode and the gate electrode is the second word line WWL2. N-channel MOS transistor for simultaneous write detection connected to 1
Reference numeral 2 denotes a source electrode connected to the drain electrode of the transistor 13, a node 15 connected to the drain electrode of the transistor 14 and a gate electrode of the first word line WWL1.
An N-channel MOS transistor for simultaneous write detection connected to the reference numeral 16 is an inverter for simultaneous write detection whose input end is connected to the other electrode of the transistor 14, and the same reference numerals as those in FIG. Indicates.

The read and write operations of the multiport RAM shown in FIG. 1 are performed by the multiport RA shown in FIG.
The same as M. And the transistors 12-14
The simultaneous write warning means composed of the inverter 16 outputs an output signal according to the potentials of the first and second word lines WWL1 and WWL2. If either one of the first and second word lines WWL1 and WWL2 is at the L level potential, the transistor 12 or the transistor 13 is turned off, and the potential of the node 15 is kept at the H level potential by the pull-up transistor 14, so that the inverter 1
6 outputs an L level potential.

However, the first and second word lines WWL1 and WWL2 belonging to different write ports are both at the H level potential, the transistors 6 and 7 are simultaneously turned on, and the first and second bit lines WBL1 and WBL1. W
When writing is possible from BL2, the transistors 12 and 13 are turned on at the same time, and the potential of the node 15 is changed to L
The output signal of the inverter 16 to H
Set to level potential. The inverter 16 outputs an H level potential, that is, a simultaneous write warning signal. When the simultaneous write warning signal is output, the data can be protected by, for example, rewriting the correct data.

The logical threshold value of the inverter 16 is
The potential of the node 15 when the N-channel MOS transistors 12 and 13 are conducting is set to the L level, and the N-channel M
It is necessary to set the potential of the node 15 as H level when either one of the OS transistors 12 and 13 is not conducting.

A multiport RAM according to the second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a circuit diagram showing a memory cell for 2 bits in a multiport RAM to which a column selecting transistor is applied. Figure 2
In, 14 is a power source for the drain electrode and the gate electrode
N-channel MOS transistor for pull-up connected to 0, 13 is an N-channel MOS transistor for simultaneous write detection in which the source electrode is grounded and the gate electrode is connected to the second word line WWL2. 12 is the source electrode of the transistor 13. An N-channel MOS transistor for simultaneous write detection, which is connected to the drain electrode, the drain electrode is connected to the source electrode of the transistor 14 at the node 15, and the gate electrode is connected to the first word line WWL1, 17 is one input terminal of the transistor 14 NOR connected to the drain electrode
A gate 18 is an exclusive OR gate having one and other input terminals connected to the column address signal lines Y1 and Y2 and an output terminal connected to the other input terminal of the NOR gate 17, 19 and 2
Reference numeral 1 is an inverter whose input end is connected to the column address signal line Y1, 20 is an inverter whose input end is connected to the output end of the inverter 19, and 22 is one input end connected to the output end of the inverter 20 and write enable is enabled at the other input end. AN in which the signal WE1 is input and the output end is connected to the column selection signal line CWE1a
An AND gate having one input end connected to the output end of the inverter 21 and the other input end inputting the write enable signal WE1 and the output end connected to the column selection signal line CWE2a
Gates, 24 and 25 are inverters whose input ends are connected to the column address signal line Y2, 26 is an inverter whose input ends are connected to the output ends of the inverter 24, and 27 is one input end connected to the output ends of the inverter 26 and the other input The write enable signal WE2 is input to the end and the output end is the column selection signal line CWE2.
The AND gate connected to a has one input terminal connected to the output terminal of the inverter 25, the other input terminal to which the write enable signal WE2 is input, and the output terminal connected to the column selection signal line CWE2b.
Is an AND gate connected to.

Data write and read operations to and from the memory cells MCa and MCb of the multi-port RAM shown in FIG. 2 are the same as those of the multi-port RAM shown in FIG.

In the multiport RAM of FIG. 2, first, the first and second bit lines WBL1, WBL1,
When data is simultaneously written through the WBL2, the transistors 6 and 7 and the transistors 8a and 9a
Is when all of them are turned on at the same time. That is, when the first and second word lines WWL1 and WWL2 become H level potentials, the column address signal lines Y1 and Y2 become H level potentials, and the write enable signals WE1 and WE2 become H level potentials, It becomes the state of. At this time, the outputs of the inverter 19 and the inverter 24 are L level, and the outputs thereof receive the inverter 20 and the inverter 26.
Output becomes H level, and AND gate 22 and AND
The potentials of the two input terminals of the gate 27 become H level, and the respective outputs become H level potential.

Therefore, in such a state, the input terminals of the exclusive OR gate are both at the H level and the output of the exclusive OR gate is at the L level. Also at this time,
Since both the transistors 12 and 13 are turned on, the potential of the node 15 becomes L level. Since both input terminals of the NOR gate 17 are at the L level, the NOR gate 17 outputs the H level potential as the simultaneous write warning signal.

In this way, when the simultaneous write warning signal is output, it is possible to rewrite the correct data and re-store the destroyed data.

If there is no possibility of simultaneously writing data to the memory cell MCa through the first and second bit lines WBL1 and WBL2, either one of the transistors 6 and 7 and the transistors 8a and 9a is turned off. Has become. Therefore, at this time, the first and second word lines WWL1 and WWL2 and the column address selection signal line Y
Any one of 1 and Y2 becomes the L level potential. In this case, the output of the exclusive OR gate 18 is at the H level, or either of the transistors 12 and 13 is turned off to bring the potential of the node 15 to the H level, and the output of the NOR gate 17 is brought to the L level potential. To be kept.

In the multiport RAM of FIG. 2, the first and second bit lines WBL1 and WB are provided in the memory cell MCb.
When data is simultaneously written through L2, it is when the transistors 6 and 7 and the transistors 8b and 9b are all turned on at the same time. That is, when the first and second word lines WWL1 and WWL2 are at H level potential, the column address signal lines Y1 and Y2 are at L level potential, and the write enable signals WE1 and WE2 are at H level potential, It becomes the state of. At this time, the outputs of the inverter 21 and the inverter 25 become the H level, the potentials of the two input terminals of the AND gate 23 and the AND gate 28 become the H level, and the respective outputs become the H level potential.

Therefore, in such a state, the input terminals of the exclusive OR gate 18 are both at the L level, and the output of the exclusive OR gate is at the L level. At this time, the transistors 12 and 13 are both turned on, so that the potential of the node 15 becomes L level. Since the input terminals of the NOR gate 17 are both at the L level, the NOR gate 1
An H level potential is output from 7 as a simultaneous write warning signal.

When the simultaneous write warning signal is output in this manner, correct data can be rewritten to prevent erroneous data from being stored.

If data is not simultaneously written to the memory cell MCb through the first and second bit lines WBL1 and WBL2, one of the transistors 6 and 7 and the transistors 8b and 9b is turned off. There is. Therefore, at this time, the first and second word lines WWL
1, WWL2 or one of the column address selection signal lines Y1 and Y2 has an L level potential. In this case, the output of the exclusive OR gate 18 is at the H level, or either of the transistors 12 and 13 is turned off to bring the potential of the node 15 to the H level, and the output of the NOR gate 17 is brought to the L level potential. To be kept.

The column address signal Y1, when the write port is two in the multi-port RAM of FIG.
Although the case where one Y2 is provided for each port has been described, two or more column address signal lines may be provided for each port, and the same effect as that of the above-described embodiment is obtained. In that case, an exclusive OR gate is provided for each column address signal line, and the output of the logical product of all the outputs of these exclusive OR gates is input to one input end of the NOR gate 17.

[0032]

As described above, according to the multiport RAM of the first aspect, a write signal is transmitted to a plurality of word lines, and a write signal is simultaneously transmitted to at least two of the connected word lines. In this case, since the simultaneous write warning means for outputting a signal for warning the simultaneous write is provided, the warning signal can be output when the same memory cell may be accessed from different write ports. Therefore, there is an effect that the data in the memory cell can be protected.

According to the multiport RAM of the second aspect, the write signal is transmitted to the plurality of word lines and the plurality of column address selection lines, and the write signal is simultaneously transmitted to at least two word lines of the connected word lines. And a simultaneous write warning that outputs a signal to warn simultaneous write when a column address signal for selecting the same column is transmitted to the column address signal lines corresponding to at least two word lines to which the write signals are simultaneously transmitted. Since it is configured to include the means, it is possible to output a warning signal when the same memory cell is accessed from different write ports, and it is possible to protect the data in the memory cell.

[Brief description of drawings]

FIG. 1 is a multiport RA according to a first embodiment of the present invention.
It is a circuit diagram which shows the structure of the memory cell of M, and a simultaneous write warning means.

FIG. 2 is a multiport RA according to a second embodiment of the present invention.
It is a circuit diagram which shows the structure of the memory cell of M, and a simultaneous write warning means.

FIG. 3 is a circuit diagram showing a configuration of a memory cell of a conventional multiport RAM.

FIG. 4 is a circuit diagram showing a configuration of a memory cell of a conventional multiport RAM.

[Explanation of symbols]

 1 to 3 inverters 4 to 7 and 12 to 14 N channel MOS transistor 17 NOR gate 18 exclusive OR gate 22 AND gate Y1, Y2 column address signal line

Claims (2)

[Claims] 1. A multi-port RAM having a plurality of write ports, wherein a plurality of gates are provided corresponding to the plurality of write ports and connected to respective control terminals of a plurality of gates for selecting the same memory cell. And a plurality of word lines, and a simultaneous write warning that outputs a signal to warn simultaneous write when a write signal is simultaneously transmitted to at least two of the word lines connected to the plurality of word lines. A multiport RAM comprising: 2. A multi-port RAM having a plurality of write ports, wherein a plurality of gates are provided corresponding to the plurality of write ports and connected to respective control terminals of a plurality of gates for selecting the same memory cell. And a plurality of columns of memory cells that are provided corresponding to the plurality of word lines and are selected by the corresponding word lines, and select a memory cell of a specific column to which data is to be written. A plurality of column address signal lines for transmitting a column address signal for writing, and simultaneously writing to at least two of the word lines connected to the plurality of word lines and the plurality of column address selection lines. The same column is connected to the column address signal line corresponding to at least two of the word lines to which the signal is transmitted and the write signal is simultaneously transmitted. And a simultaneous write warning means for outputting a signal for warning simultaneous writing when a column address signal to be selected is transmitted.