JPH06162767A - Electronic computer - Google Patents

Abstract

PURPOSE:To reduce the power consumption of an electronic computer having a large storage capacity by using a dynamic random access memory as the storage part. CONSTITUTION:Normally, a refresh address is given from a refresh address counter 109 to a dynamic random access memory 102 to maintain its storage. When the operation of a CPU 101 or the like will be practically stopped, the address counter 109 is stopped, and the dynamic random access memory 102 is switched to the mode where refresh is performed without an external refresh address. Consequently, power is not consumed by the wiring capacity from the address counter 109 to the dynamic random access memory 102, and contents of the dynamic random access memory 102 are held for a long time by a battery 117.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer using a battery as a power source.

[0002]

2. Description of the Related Art Generally, an electronic computer, as shown in FIG. 2, has a central processing unit (hereinafter abbreviated as CPU) 201, a random access memory (temporary storage for temporarily storing programs and operation data for controlling the CPU). (Hereinafter abbreviated as RAM) 202, a language processing program that is regularly used,
A read-only memory (hereinafter referred to as RO
Abbreviated as M) 203, an input device 204 such as a keyboard for inputting control data of the calculation procedure to the CPU, an output device 20 such as a printer or a display device for outputting the calculation result.
5, an external storage device 206 and the like.

The electronic computer having such a configuration is generally used as follows. That is, the external storage device 20
6 to load the user program and data into the RAM 202 by the program on the ROM 203, and then the RA
The program on the M202 is executed and the result is displayed on the display device, printed by a printer if necessary, or saved in the external storage device 206 and reused. In addition, when not using the electronic computer, the power of each element is turned off,
The data in AM 202 is lost. In order to make an electronic computer with such a configuration battery-powered and to be small, lightweight, and portable, it is necessary to reduce the power consumption of the entire system and to use a large-sized and high-power consumption device such as a magnetic storage device as an external storage device. It should not be used or should be used less frequently.

As shown in FIG. 3, a conventional portable electronic computer capable of operating a battery has the following configuration. That is, a low power consumption device such as a complementary MOS integrated circuit (hereinafter abbreviated as CMOS / IC) is used as a circuit element for controlling the CPU 301, the RAM 302, the ROM 303 and the input / output devices 304 and 305, and a display device is used. , Low power consumption and thin liquid crystal displays are widely used.
However, as the external storage device 306, there is no device with low power consumption and small size. Therefore, the conventional portable electronic computer generally takes the following method. That is,
Power is supplied to the RAM 302 even when the power switch of the computer is turned off (when the computer is not used) so that the information once stored is not lost even when the computer is not used. By doing so, in the computer using the general commercial power supply shown in FIG. 2, the program and data are loaded every time the power switch is turned on, but access to the external storage device can be extremely reduced.

Actually, the portable computer loads the program or data from the host computer through the communication interface 307, or takes the portable computer to a place where the external storage device is and loads the program or data. The data once loaded in the RAM 302 is used in a field where it is used carefully without being erased. In addition, as a portable external storage device, a cassette tape recorder for audio may be substituted, but in this case as well, in order to cover the long access time and low reliability of the cassette tape recorder, etc. And R
Power is constantly supplied to the AM 302 in order to save data carefully.

In the portable electronic computer, the programs and data are always stored in the RAM 302, and it has been described how important they are.
Power consumption is required to be very small while AM holds information, and all conventional portable computers use C
Static RAM by MOS / IC (hereinafter referred to as SRAM
Abbreviated) is used. SRAM of CMOS / IC
Does not require any particular electric power for retaining information, so almost all of the energy of the power supply battery is spent for computer operation, which is efficient.

[0007]

The drawbacks of the conventional portable electronic computer will be described below. (1) The storage capacity of the RAM 302 cannot be sufficient. This has a very important meaning. That is, since the RAM 302 plays a part of the role of the external storage device, the larger the capacity, the better. However, since the RAM 302 is portable, the mounting space is not sufficient and the required storage capacity of the SRAM is large. It is not possible to mount as many chips as can realize

(2) It is expensive. An SRAM with a CMOS / IC uses 4 to 6 transistors for each memory cell, and therefore a dynamic RAM (hereinafter referred to as DR) using one transistor and one capacitor for each memory cell.
This is because the integration degree is about 1/4 compared to AM).

(3) It is not functionally sufficient. This is related to the above (1) and (2), and since the RAM having a sufficient memory capacity cannot be used in terms of price and space, the storage capacity may be insufficient.

The present invention eliminates such drawbacks of the conventional portable electronic computer, and an object thereof is to realize a portable electronic computer which is comparable in function and price to a general electronic computer using a commercial power source. To do.

[0011]

The electronic computer of the present invention comprises:
In the electronic computer having at least one central processing unit, a storage unit for storing a program executed by the central processing unit or data accessed by the central processing unit, and an input / output unit for the central processing unit, the storage A dynamic random access memory having a mode of performing refresh without using an external refresh address is used for at least a part of the unit, and an external refresh address is given to the dynamic random access memory at a desired timing. When substantially stopping the operations of the refreshing means, the battery for supplying electric power to the storage section, and the central processing unit or the input / output means, the external refreshing means is stopped and the power source from the battery is stopped. In addition to excluding from the target of supply, A refresh mode switching means for switching the Na Mick random access memory to said mode, characterized in that the provided.

[0012]

In the electronic computer having such a configuration, the refresh address is normally given from the external refresh means to the dynamic random access memory at a desired timing to maintain the storage in the storage section. In the case of substantially stopping the operation of the above, the refresh mode switching means stops the operation of the external refresh means to exclude it from the target of the power supply from the battery, and at the same time, the dynamic random access forming at least a part of the storage section. The memory is switched to a mode in which refresh is performed without using an external refresh address. Therefore, power consumption is eliminated due to the wiring capacity from the external refresh means to the dynamic random access memory, and the contents of the dynamic random access memory by the battery can be retained for a long period of time.

[0013]

FIG. 1 is a diagram showing an embodiment of the present invention.
Reference numeral 101 is a CMOS CPU, 103 is a ROM, 104 is an input device such as a keyboard and a circuit for controlling the input device, 105
Is an output device such as a display device, and normally uses a liquid crystal display that consumes less power. Reference numeral 106 is an external storage device, and 107 is a communication interface circuit.

The above is basically the same as the configuration of the conventional battery-operated electronic computer shown in FIG. 3, but in order to reduce the power consumption of the device as much as possible when each element is not used, an element with a large idle current is used. , Electronically controllable switches 120, 121, 122 are provided in the power supply line. These switches are controlled by the slave CPU 110. The slave CPU 110 has the RA described below according to the contents programmed in advance in the built-in ROM.
Manage M's controls and operating modes in the system,
For example, in the operation mode using the ROM 103, the switch 120 is turned on.

Reference numeral 102 denotes a DRAM, which is an external storage device 106.
Programs and data are transferred and stored from the communication interface 107 and the ROM 103. CPU 101
Performs arithmetic operation according to the program and data on the RAM 102. CMOS ROM as the ROM 103
Since the power consumption is small, it is possible to directly cause the CPU 101 to perform the arithmetic operation according to the program and data on the ROM 103 without transferring to the RAM 102. In order to make the lever device applicable, the ROM 103 is frequently replaced. Alternatively, the maker prepares various kinds of ROMs and selects the ROM 103 according to the customer's request. Therefore, even if the power consumption of the ROM 103 is large, an inexpensive one is required. In this case, it is better to start the operation of the CPU 101 after transferring the contents of the ROM 103 to the RAM 102 as in this embodiment. ROM1
No. 03 is because power need only be supplied when transferring data or programs.

In this embodiment, the DRA is used as the RAM 102.
M is used. This DRAM 102 incorporates a refresh address counter that performs the same operation as the refresh address counter 109 in the same chip by the same semiconductor process, and uses an external refresh address counter or an internal refresh address counter to refresh the stored contents. A control terminal for selecting whether to use a counter is provided. This control terminal is the slave CPU 110
It is connected to the.

External refresh address counter 10
The normal refresh mode using 9 is called a last-on refresh, and the refresh mode using an internal address counter is called a pulse refresh, an auto refresh, and a self refresh. In the latter operation mode (hereinafter referred to as the auto refresh mode), it is not necessary to charge and discharge the wiring capacity of the bus line, so that the power consumption of the DRAM 102 can be made extremely small. The current consumption due to the capacitive component of the bus line will be discussed in detail later.

The slave CPU 110 has a temperature sensor 11
3 and the power supply voltage of the RAM 102 are AD-converted by the AD converter 112 to know the temperature and the power supply voltage of the RAM 102, and the state of the power switch 123, C
The entire system is controlled by the operating state of the PU, and the refresh mode and refresh interval of the RAM 102 are controlled. A refresh address counter 109 counts refresh addresses of the DRAM 102. A multiplexer 108 switches between a system address and a refresh address. When the address of the DRAM 102 is divided into rows and columns, row and column addresses are also multiplexed.

A timer 111 sends a signal to the slave CPU at regular intervals. The slave CPU 110 activates the AD converter 112 or RA based on this signal.
Define a refresh interval for M102.

The operation of the slave CPU 110 will be described in sequence from the power-on based on the flowchart of FIG. RAM 102, refresh address counter 10
9, the slave CPU 110, and the timer 111 are always supplied with power source energy from the dry battery 114 to operate.
The slave CPU 110 constantly monitors the power switch 123, and when the switch is closed or when the signal from the timer 111 is counted and a certain time is reached (step S1), the boost stabilizing power circuit 115 is powered. In order to supply the power, the switch 116 is closed, the input device 104 and the output device 105 are operated, and at the same time, the oscillation circuit 117 is activated and the CPU 101 is operated (step S2).

Since the CPU 101 is made of CMOS, it consumes no energy unless the clock is supplied. Therefore, there is no switch between the dry battery 114 and the CPU 101. CPU 101 DRAM 10 at rest
The second refresh mode is an auto refresh mode as described later. C is supplied with clock
When the processing of the PU 101 becomes possible, the slave CPU 11
When 0, the refresh mode of the DRAM 102 is switched to the last-on refresh mode. This determines that the system has been activated (step S
3) Based on the situation when the system was inactivated last time (stored in the DRAM 102) (step S4), the slave CPU 110 stores the information on the RAM 102 stored before the system was inactivated last time. The execution start address of the CPU 101 is set by the initial program in the slave CPU 110 (step S5). Alternatively, after supplying power to the ROM 103 and transferring the program to the RAM 102, the ROM 1
Then, the power source of 03 is cut off, and the execution start address on the RAM 102 is designated (step S6).

After that, the slave CPU 110 operates the switches 120, 121, 122 according to the instruction of the CPU 101, and puts a circuit in which a large amount of battery energy is consumed, such as an input / output device, in an idle state and is in a stopped state (a state in which no power is consumed). (Step S7). With the above, the system startup is completed, and thereafter the slave CPU 110
The system operation processing routine shown in is executed.

First, the slave CPU 110 detects the temperature and power supply voltage of the DRAM 102 at regular time intervals (step S10) (step S11), and sets the refresh interval based on them (step S12).
The multiplexer 108 is activated at this interval until the timing for setting the refresh interval is reached, and DR
The address of the AM 102 is brought down to the refresh address counter 109 side, and the DRAM 102 is refreshed (steps S13, 14).

Generally, a DRAM consumes a large amount of power when strobes of row and column addresses, when charging a pulley, and when refreshing. Therefore, if these operations are minimized, the power of the system can be reduced. Also D
As the power supply voltage of the RAM is higher and the temperature of the RAM is higher, the stored information is more likely to disappear, and it is necessary to refresh the RAM at short intervals. Conventionally, the refresh interval is set to an extremely short period so that the stored contents are not lost even under the worst conditions of temperature and power supply voltage, and the refresh interval is fixed. In the present invention, the DRAM 10 is used at each temperature and power supply voltage.
The slave CPU is programmed so that 2 can select the longest refresh interval that can hold the stored contents.

The CPU 101 is an input device 1 such as a keyboard.
When the slave CPU 110 detects that it is in an idle state such as 04 or waiting for the input of the communication interface 107 (step S15), it controls the oscillation circuit 117 to C
The PU 101 is stopped (step S16) to save power consumption.

When the CPU 101 wants to turn off the power of the system by the program, the slave CPU 110
Send a signal to. When the slave CPU 110 detects this signal (step S20), the slave CPU 110 executes a series of processing for stopping the system, such as turning off the power supply of the boosted and stabilized power supply circuit 115 and stopping the oscillation circuit 117 (step S20). Step S21).

When the slave CPU 110 detects the disconnection of the switch 123 (when the user turns off the power), the AD
The converter 112 detects the decrease of the battery voltage and detects the battery 114
When it is determined that it becomes difficult to retain the information in the RAM 102 when the remaining capacity of the CPU continues to operate further (step S30), when the CPU 101 is next turned on or the battery 114 is charged. Then, the system is operated to a re-executable state (step S31), and then a series of processing for turning off the power of the system is performed (step S21).

Thereafter, a signal is sent to the control terminal for switching the refresh mode of the DRAM 102 to switch the refresh mode to the auto refresh mode (step S40). CP if the system is inactive
Power is supplied to the DRAM 102 in addition to U110, and during this time, the DRAM 102 operates in the auto refresh mode in which power consumption is low.

If the CPU 101 is not in an idle state or the like and it is not necessary to stop the operation (steps S15, 2)
0, 30), the slave CPU 110 returns to the processing of step S10 and repeats the above-described processing until another processing request is made.

Even when the system power is turned off when the battery voltage drops as described above, the time until the battery is replaced,
Alternatively, as for the time until recharging, if the amount of electricity sufficient to retain the contents of the RAM 102 remains in the battery is detected, the contents stored in the RAM 102 will not be lost forever.

In the above-described embodiment, the CPU 10 is used by using the DRAM 102 having a built-in refresh address counter.
DR in auto refresh mode while 1 is idle
Although the AM 102 is refreshed to reduce the current consumption of the DRAM 102, it is possible to use a DRAM that does not include a refresh address counter, or to use the DRAM even if it does not. In this case, DRAM1
It is desirable that the refresh interval be continuously determined based on the temperature of 02 and the power supply voltage to minimize the current consumption associated with the refresh.

In this embodiment, even if the refresh address counter built in the DRAM is not used, the DR
The power consumption of AM is considerably reduced from the conventional one. This is from the refresh address counter 109 to the DRAM
This is achieved by shortening the wiring distance to 102. That is, the electric charge charged and discharged to the wiring capacity of the wiring also consumes considerable power. For example, the address bus 118 and the data bus 119 are connected to input / output terminals of many elements, and usually have a load capacity of about 100 PF. In an 8-bit CPU, the number of bus lines is 20 or more. For example, if 20 bus lines have an average load capacity of 100 PF and a change of 5 V _PP at an average of 500 KHz, these power lines can be used to The current charged / discharged to the capacity is 100 × 10 ^-18 (F) × 20 (pieces) × 5 (V) × 5
00 × 10 ³ (Hz) = 5 mA, which means that the current is consumed only by driving the bus line in the normal operating state.

Now, the refresh address counter 10
Since 9 is forced to operate even when the system is inactive, it is necessary to reduce the load capacitance of the output line here as much as possible. In the embodiment according to the present invention shown in FIG. 1, since the path from the refresh address counter 109 to the RAM 102 is short, the current when the RAM is refreshed can be reduced. If the built-in refresh address counter is used when the CPU 101 is idle as in the present embodiment, this wiring capacity can be regarded as almost 0, so that the current consumption when the CPU 101 is idle can be reduced reliably and significantly.

Although the refresh mode of the DRAM 102 is switched in the present embodiment, the refresh interval may be set longer than that during operation when the CPU 101 is idle. If you just want to hold the data in the DRAM,
This is because the refresh interval may be longer than that for accessing the data in DRAM.

It has been explained that the latter refresh mode should be used when the system is active by comparing the time when the system is active with the time when the system is active.
Since 2 is frequently accessed, the refresh address and the address at the time of access need to be accessed quite frequently. This switching becomes quite complicated due to the restriction of the number of input / output terminals to the semiconductor chip. Therefore, when the system is active, the method shown in FIG. Can simplify the circuit. When the refresh mode is selected according to the operating state of the CPU 101, the slave CPU 110 also makes the selection.

Further, in the embodiment of the present invention, the case of detecting both the temperature and the voltage is described, but the power consumption of the RAM 102 can be considerably reduced by only one of them.

[0037]

As described above, according to the present invention, D
The power consumption of RAM can be reduced by about 3 to 4 digits, and D
The RAM can also constitute a dry-cell operated computer. Further, if the stored contents are always held in the RAM as in the present invention, it is not necessary to boot the programs and data one by one at the time of starting the electronic computer, and it is possible to perform a quick operation. Further, there is no possibility of accidentally deleting the contents of RAM in an instant by turning off the system power supply due to an erroneous operation, and an extremely easy-to-use electronic computer can be supplied at a low price.

The present invention can be applied to low power consumption of a file device or the like which uses a large amount of RAM. In addition, it is useful for reducing power consumption and improving system reliability in electronic computers that use commercial power sources.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional electronic computer.

FIG. 3 is a block diagram showing a conventional electronic computer using a dry battery as a power source.

FIG. 4 is a flowchart showing a startup processing routine executed by the slave CPU 110 in the embodiment.

FIG. 5 is a flowchart showing a processing routine during system operation.

[Explanation of Codes] 101 ... CPU 102 ... DRAM 110 ... Slave CPU 112 ... AD Converter 113 ... Temperature Sensor 114 ... Battery 103 ... ROM

[Procedure amendment]

[Submission date] September 8, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

The electronic computer of the present invention comprises:
In the electronic computer having at least one central processing unit, a storage unit for storing a program executed by the central processing unit or data accessed by the central processing unit, and an input / output unit for the central processing unit, the storage At least a part of the
It is composed of a semiconductor memory that requires a
Refresh giving refresh address for boot
Address assigning means on the semiconductor memory or
Installed near the mounting position to supply power to the entire device.
And the power supply capacity of the battery is below a specified value
In case of decrease in
To the storage unit while substantially stopping the operation of the force means.
Is provided with a power supply control means for continuing the power supply .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

[0012]

[Operation] The electronic computer having such a configuration is a power supply controller.
Batteries in stages supply power to the entire device
However, if the battery power capacity drops below a specified value,
Substantially stops the operation of the central processing unit or the input / output means.
While at least part of it stores data
In order to store the data, it is necessary to use semiconductor memory that requires refreshing.
The power supply to the created storage unit is continued. This semiconductor memory
A reflector provided on or near the mounting position.
The address assigning means
Give the address. Therefore, the refresh address
Power consumption due to the wiring capacity of the signal line
It

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

[0037]

As described above, according to the present invention, according to the present invention, Li
Memory consumption using semiconductor memory that requires freshness
Power consumption can be significantly reduced and refreshing is required
Even if a semiconductor memory is used, a battery-operated computer can be constructed.
Can be made. Moreover, the power capacity of the battery is
If it falls below a certain level, the central processing unit or input / output means
Power is supplied to the storage unit while the operation is substantially stopped.
When the battery's remaining capacity decreases, the electronic
Even if the computer operation is stopped, the stored contents of the storage unit will be stored for a long time.
It can be held over.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

Therefore, the program loaded in the storage unit and
The data is saved, so when you start the computer,
No need to boot programs and data,
It can also be used to start operation immediately after turning on the power.
Noh. In addition, the present invention is usually used in a commercial power source,
After commercial power is cut off, back up the storage unit with the battery.
It can be applied to a system such as
It can be used for electric power and high reliability of the system.

Claims (1)

[Claims] 1. An electronic device having at least one central processing unit, a storage unit for storing a program executed by the central processing unit or data accessed by the central processing unit, and an input / output unit for the central processing unit. In the computer, a dynamic random access memory having a mode of performing refresh without using a refresh address from the outside is used for at least a part of the storage unit, and the dynamic random access memory is refreshed from the outside at a desired timing. External refresh means for giving an address, a battery for supplying power to the storage unit, and when substantially stopping the operation of the central processing unit or the input / output means, stop the external refresh means, Exclude from the target of power supply from the battery Together, the electronic computer, characterized in that a, a refresh mode switching means for switching said dynamic random access memory to the mode.