JPH06162414A - Magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain the write after read even when the number of channels are switched in a magnetic recording and reproducing device for editing the audio signal of multichannel by using e. g. a digital audio tape recorder. CONSTITUTION:The audio data are delayed by a memory circuit 18 time base compressing and/or expanding in a multichannel mode so as to record the regenerative audio data on the same place on a magnetic tape in 2-channel mode for magnetic heads 4A, 4B for recording arranged behind by a prescribed pitch for the magnetic heads 6A, 6B for reproducing.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 5) Action (FIGS. 1 and 5) Embodiment (1) Overall Configuration of Embodiment (FIG. 1) ) (2) Operation mode (2-1) Normal operation mode (Fig. 1) (2-2) 32 [kHz] 4 channel mode (Figs. 1 to 3) (2-3) 44.1 [kHz] 4 channel mode (Figs. 1, 4 and 5) (2-4) 48 [kHz] 4 channel mode (Figs. 1, 6)
And Fig. 7) (2-5) 32 [kHz] 8 channel mode (Figs. 1 and 8
And FIG. 9) (3) Control of memory circuit (FIGS. 10 to 16) (4) Effects of the embodiment (5) Other embodiments Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording / reproducing apparatus and can be applied to the case of editing a multi-channel audio signal using a digital audio tape recorder, for example.

[0003]

2. Description of the Related Art Conventionally, in a digital audio tape recorder, a digital audio signal is recorded and reproduced by using a rotary drum so that a high quality audio signal can be recorded and reproduced.

[0004]

By the way, in a digital audio tape recorder of this kind, if it is possible to record and reproduce an audio signal of a plurality of channels other than the stereo system like a normal audio tape recorder for recording and reproducing an analog signal. It is thought that the usability of the digital audio tape recorder can be improved.

Further, at this time, if a digital audio signal can be recorded / reproduced between channels, a single magnetic tape can be used to perform edit processing, mixing processing, etc., if necessary, thereby improving usability.

For this purpose, for example, as proposed in Japanese Patent Laid-Open No. 3-203864, magnetic heads for reproduction and recording are arranged on a rotary drum, and a digital audio signal reproduced by the magnetic head for reproduction is edited. After processing, mixing, etc., a method of re-recording with a subsequent recording magnetic head is conceivable (that is, a write-after-read method). At this time, audio data of a plurality of channels can be recorded / reproduced by compressing and multiplexing the audio data of a plurality of channels on the time axis, whereby this kind of function can be realized for the audio data of a plurality of channels.

As described above, it is considered convenient if the multi-channel digital audio tape recorder can also edit the two-channel audio signals in the same manner.

However, when the time axis compression and time axis expansion are performed in this way, it takes time to reproduce and record the audio data, and therefore, when the audio data of two channels is simply edited, the reproduced audio data is recorded as the original recording. In the multi-channel digital audio tape recorder, there is a problem that the write-after read cannot be performed when the number of channels is changed.

The present invention has been made in consideration of the above points, and an object of the present invention is to propose a magnetic recording / reproducing apparatus for multi-channel magnetic recording / reproducing apparatus capable of performing write-after read even when the number of channels is switched. Is.

[0010]

In order to solve such a problem, in the present invention, a pair of recording tracks having positive and negative azimuth angles are sequentially formed on a magnetic tape in order to record audio data D1A to D1H. In the magnetic recording / reproducing apparatus 1, the reproducing signal SPB output from the reproducing magnetic heads 6A and 6B arranged on the rotary drum 2 is processed to obtain reproduced data DADT, and the reproducing magnetic head 6A and
6B performs error correction processing on the reproduction data DADT in a cycle of scanning a pair of recording tracks, and then performs deinterleaving processing in a cycle of reproducing magnetic heads 6A and 6B scanning a pair of recording tracks. Playback means for outputting 2-channel playback audio data DADT, and audio data output circuit 18, 2 for sequentially storing and outputting 2-channel playback audio data DADT
2, 32 and audio data output circuits 18, 22, 3
2 to output audio data D2A to D2H sequentially to record 2 channels of recorded audio data ADD
Audio data input circuit 16, 18, 2 for outputting T
6 and the recording magnetic heads 4A and 4B arranged on the trailing side of the reproducing magnetic heads 6A and 6B on the rotary drum 2, so that the recording magnetic heads 4A and 4B form a pair of recording tracks. After the recording audio data ADDT of 2 channels is interleaved in units of cycles, an error correction code is generated in units of cycles in which the recording magnetic heads 4A and 4B form a pair of recording tracks. A recording signal generating circuit 24 for recording the recording audio data ADDT of two channels and the error correction code on the magnetic tape via the heads 4A, 4B is provided, and the audio data output circuits 18, 22, 32 are reproduced in the multi-channel mode. By sequentially storing and outputting the audio data DADT, the reproducing magnetic head 6
The audio data D of 4 channels or more is reproduced by expanding the reproduction audio data DADT in the time axis in units of the cycle in which A and 6B scan a pair of recording tracks.
2A to D2H demodulated, audio data input circuit 1
6, 18, and 26 are audio data output circuits 18, 2
Audio data D2A to D2 output from 2, 32
By storing H sequentially and outputting recording audio data ADDT of 2 channels, the recording magnetic head 4
The audio data D2A to D2H of the M channel is set in units of the cycle in which A and 4B form a pair of recording tracks.
Are time-axis-compressed and multiplexed to generate 2-channel recording audio data ADDT, and the recording magnetic head 4A,
In the multi-channel mode, the reference numeral 4B is a predetermined value for the reproducing magnetic heads 6A and 6B so that the reproducing audio data DADT reproduced through the reproducing magnetic heads 6A and 6B can be recorded at the same location on the magnetic tape. Only the track pitch is arranged on the trailing side, and the audio data output circuits 18, 22, 32 and / or the audio data input circuits 16, 18, 26 are in the 2 channel mode.
The audio data output from the reproduction audio data DADT and / or the audio data output circuits 18, 22 and 32 so that the reproduction audio data DADT reproduced via the reproduction magnetic heads 6A and 6B is recorded at the same location on the magnetic tape. The data D2A and D2B are delayed and output for a predetermined period.

[0011]

In the multi-channel mode, the reproducing audio data DADT reproduced via the reproducing magnetic heads 6A and 6B can be recorded at the same position on the magnetic tape so that the reproducing audio data DADT can be recorded at the same position. Magnetic head 4A for recording with only the track pitch arranged on the trailing side,
In contrast to 4B, in the 2-channel mode, the audio data output circuits 18, 22, 32 and so on to record the reproduced audio data DADT reproduced through the reproducing magnetic heads 6A, 6B at the same location on the magnetic tape. Alternatively, the audio data input circuit 16, 18, 26 delays the reproduced audio data DADT and / or the audio data D2A, D2B output from the audio data output circuit 18, 22, 32 for a predetermined period and outputs the delayed audio data D2A, D2B. Even after switching the operation mode between the two channel modes, the write-after read can be performed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Structure of Embodiment In FIG. 1, reference numeral 1 denotes a digital audio tape recorder as a whole, which is mounted on a rotary drum 2 having a diameter of 30 mm.
The magnetic heads 4A and 4B for recording are mounted and rotated at an angular interval of 80 degrees.

In this state, in the digital audio tape recorder 1, the magnetic tape is wound around the rotary drum 2 at a winding angle of 90 degrees, and the magnetic tape is run at a predetermined speed. Recording tracks having negative azimuth angles can be sequentially formed.

With respect to the recording magnetic heads 4A and 4B, the digital audio tape recorder 1 is provided with a predetermined step so that the reproducing magnetic heads 6A and 6B are mounted on the rotary drum 2, whereby the reproducing mode is set. In this case, the reproduction signal SPB obtained from the reproduction magnetic heads 6A and 6B can be processed to reproduce the digital audio signal, and the digital audio signal reproduced in the edit mode can be processed and then the magnetic heads 4A and 4 can be processed again.
It can be recorded via B.

At the rotational speed of the rotary drum 2 and the running speed of the magnetic tape, a servo circuit (not shown) is used according to the operation mode of the digital audio tape recorder 1 based on the control data output from the system control circuit 10. ), The digital audio tape recorder 1 can be operated in various operation modes by switching the drive conditions of the magnetic tape running system as required.

That is, in the digital audio tape recorder 1, in a normal operation mode, an audio signal of 2 channels is recorded in a recording mode of a standard time mode or a long time recording mode in accordance with the format standardized for the digital audio tape recorder. On the other hand, in the multi-channel mode, the audio signal of 4 channels or 8 channels can be recorded and reproduced.

For this reason, the digital audio tape recorder 1 can input and output an audio signal of a maximum of 8 channels. That is, in the digital audio tape recorder 1, the analog digital conversion circuit (A / D) 12 can input a maximum of 8 channels of audio signals S1A to S1H, and the audio signals are converted into digital audio signals of a predetermined sampling frequency. .

At this time, the analog digital conversion circuit 12
, The sampling frequency is switched based on the control data output from the system control circuit 10, and the sampling frequency is 32 [kHz] in the normal operation mode.
, 44.1 [kHz] or 48 [kHz], the two-channel audio signals S1A and S1B are converted into digital audio signals D1A and D1B.

On the other hand, in the multi-channel mode, the analog digital conversion circuit 12 records a sampling frequency of 32 [kHz], 44.1 [kHz] or 48 [kH when recording the 4-channel audio signals S1A to S1D.
z] is used to convert the audio signals S1A to S1D into digital audio signals D1A to D1D and record an 8-channel audio signal, a sampling frequency of 32
The audio signals S1A to S1H are converted into digital audio signals D1A to D1H at [kHz].

As a result, the analog digital conversion circuit 1
2 is a digital audio signal D1A for converting the audio signals S1A to S1H in the recording mode and the editing mode.
To D1H, the data is output to the random access memory circuit (RAM) 18 via the mixer (MIX) 14 and the data latch circuit (L) 16.

Here, in the random access memory circuit 18, from the data latch circuits 16 and 22 in accordance with the address data AD output from the timing generator (TG) 20 and the identification data O / E output from the system control circuit 10. The output audio data are sequentially stored and output in a predetermined order.

At this time, in the normal operation mode, the data latch circuit 16 outputs the 2-channel digital audio signals D1A and D1B which are sequentially input as they are, and the random access memory circuit 18 similarly outputs the 2-channel signals in the order of input. The digital audio signal ADDT (D1A, D1B) is output. On the other hand, in the multi-channel mode, in the digital audio tape recorder 1, the data latch circuit 16 sequentially latches 4-channel or 8-channel audio data, and sequentially and cyclically fetches them into the random access memory circuit 18 every 2 channels. By
4 channels or 8 channels of audio data are time-division multiplexed to form 2 channels. The random access memory circuit 18 rearranges the two channels of audio data and outputs them in a predetermined order (hereinafter referred to as interleaving processing of the random access memory circuit). At the time of reproduction, the two channels of audio data are reversed. ADDTs are rearranged and output (hereinafter referred to as deinterleave processing of the random access memory circuit).

Thus, in the digital audio tape recorder 1, when the digital audio signal is recorded on the magnetic tape in the recording mode and the editing mode, the audio signals S1A to S1H of each channel can be sequentially recorded on a predetermined recording track. In the reproduction mode and the edit mode, the audio data ADDT reproduced in this rearranged order is rearranged into the original arrangement. Further, by rearranging the data array and switching the sampling frequency in this way, in the data latch circuit 16 and the random access memory circuit 18, the audio data is time-axis compressed and multiplexed when recording in the multi-channel mode. On the other hand, during reproduction in the multi-channel mode, the data latch circuit 30 and the random access memory circuit 18
However, the reproduction data compressed on the time axis is expanded on the time axis and reproduced on the original channel.

The recording signal generating circuit 24 is a signal processing circuit for directly inputting a 2-channel digital audio signal ADDT and generating a recording signal in accordance with a format standardized for a digital audio tape recorder. In the case of this embodiment. By switching the operating frequency, in addition to the standardized format for digital audio tape recorders, audio data in multichannel mode can be processed.

That is, the recording signal generating circuit 24 is connected to the random access memory circuit 1 via the data latch circuit 26.
The two-channel audio data ADDT interleaved in 8 are sequentially input, and this audio data ADDT is blocked at the rotation cycle of the rotary drum 2 (that is, the frame cycle).

Further, the recording signal generation circuit 24 interleaves the block audio data in block units according to the standard of the digital audio tape recorder, adds an error correction code, a sub code, etc., and then records it. It is converted into a signal and output to the recording magnetic heads 4A and 4B. As a result, in the digital audio tape recorder 1, in the recording mode and the editing mode, the digital audio signals D1A and D1B converted into digital signals by the analog digital conversion circuit 12 in the normal operation mode are recorded in the same order as the recording signal generation circuit 24. The digital audio signals D1A and D1B can be sequentially recorded on the magnetic tape in accordance with the standardized format.

On the other hand, in the multi-channel mode, the digital audio tape recorder 1 operates in the recording mode and the editing mode in the random access memory circuit 1.
By performing interleave processing by the 8 and the recording signal generation circuit 24, a 4-channel or 8-channel digital audio signal can be sequentially recorded on a preset recording track. The reproduction signal processing circuit 30 is a signal processing circuit which processes the reproduction signal SPB in accordance with the format standardized for the digital audio tape recorder, like the recording signal generation circuit 24. In the case of this embodiment, the operating frequency is switched. Thus, in addition to the format standardized for the digital audio tape recorder, the multi-channel mode audio data ADDT can be processed.

That is, the reproduction signal processing circuit 30 demodulates the reproduction signal SPB, performs error correction processing, and then performs deinterleave processing, thereby reproducing the 2-channel audio data ADDT. As a result, in the digital audio tape recorder 1, when reproducing a magnetic tape recorded in a normal operation mode, the 2-channel audio data ADDT output from the reproduction signal processing circuit 30 is output in the same order as the data latch circuit 2.
2. By outputting through the random access memory circuit 18 and the data latch circuit 32, the 2-channel digital audio signals D2A and D2B can be reproduced.

On the other hand, in the multi-channel mode, the digital audio tape recorder 1 de-interleaves the reproduction data in the reproduction signal processing circuit 30, then de-interleaves it in the random access memory circuit 18, and extends the time axis. , 4 channels or 8 channels of digital audio signals D2A to D2H which are recorded by being assigned to a predetermined recording track can be reproduced.

Digital analog conversion circuit (D / A) 3
6 is a digital audio signal D2A to D2 having a maximum of 8 channels corresponding to the analog digital conversion circuit 12.
H is converted into analog signals S2A to S2H and output.

At the time of outputting the audio signals S2A to S2H, the digital analog conversion circuit 36
A digital audio signal can be input through a selector (SEL) 38. In the selector 38, the digital audio signals D2A to D2H output from the data latch circuit 32 and the digital audio signal output from the analog digital conversion circuit 12 are input. D1
A to D1H and the digital audio signals D1A to D1H output from the mixer 14 can be selectively output. As a result, the digital audio tape recorder 1 can switch the types of digital audio signals that can be monitored as needed.
The usability is improved accordingly.

That is, in the recording mode, the audio signals S1A to S1H to be recorded can be monitored by selecting the digital audio signals D1A to D1H output from the analog digital conversion circuit 12, whereas in the reproducing mode, the data latch can be monitored. The reproduction signal can be monitored by selecting the digital audio signals D2A to D2H output from the circuit 32.

On the other hand, in the edit mode, the mixer 14 outputs the digital audio signals D1A to D1H output from the analog digital conversion circuit 12 and the digital audio signal D2A output from the data latch circuit 32 between the channels selected by the user. .About.D2H are combined and output, whereby the digital audio tape recorder 1 can be applied with a so-called write-after-read method to repeatedly perform editing processing by using one magnetic tape. By selectively outputting the digital audio signal output from the mixer 14 in the edit mode by the selector 38,
It is designed so that you can check the editing work.

The system control circuit 10 switches the entire operation in response to a user's operation and based on the sub-code data output from the reproduction signal processing circuit 30. Thereby, the entire digital audio tape recorder 1 is required. It is designed to operate in various operating modes. At this time, in the system control circuit 10, the identification data O / is stored in the random access memory circuit 18 based on the frame address reproduced by the reproduction signal processing circuit 30.
E is output, which causes the random access memory circuit 1
8 operation is controlled.

Further, in the system control circuit 10,
A digital signal processing circuit (DSP) 40 is driven, so that the digital signal processing circuit 40 moves to the rotary drum 40.
It outputs the reference signal EXSY synchronized with the rotation cycle of, the bit clock BCK, and the like. The timing generator 20 receives the reference signal EXSY and the bit clock BCK.
The address data of the random access memory circuit 18 is output on the basis of, and the operation reference clock CL,
Outputs LRCK, etc.

(2) Operation mode (2-1) Normal operation mode In the normal operation mode, the digital audio tape recorder 1 operates in accordance with the format standardized for this kind of digital audio tape recorder.
Record and reproduce channel audio signals.

Therefore, in the system control circuit 10, the operation of the digital signal processing circuit 40 is switched, and the reference signal EX is respectively set in the standard time mode and the long time mode.
The SY cycle is set to 30 [msec] and 60 [msec]. As a result, in the system control circuit 10, the formation cycle of a pair of recording tracks (that is, one frame cycle F) in the standard time mode and the long time mode is 30 [ms] each.
ec] and 60 [msec], and the recording signal generating circuit 24 sequentially interleaves and error-corrects the 2-channel audio data ADDT in units of this cycle during recording.

On the other hand, in the random access memory circuit 18, during recording, the two-channel digital audio signals which are sequentially input are held in the input order for a predetermined time and output. Further, in the analog digital conversion circuit 12, the sampling frequency is 32 [kHz], 44.1 [kHz] or 48 [kH] by sampling the 2-channel audio signal with reference to the clock signal CK.
z]] to generate a digital audio signal.

As a result, in the digital audio tape recorder 1, a pair of recording tracks are formed at a period of 30 [msec] and 60 [msec] in the standard time mode and the long time mode, respectively, and a digital audio signal D1A of 2 channels is sequentially formed. , D1B can be recorded.

On the other hand, at the time of reproduction, in the servo circuit, the rotary drum 2 is rotationally driven so as to be synchronized with the reference signal EXSY, and the capstan motor is subjected to tracking control. In 30, the reproduction signal SPB which is sequentially reproduced in synchronization with the reference signal EXSY is processed and the 2-channel audio data DADT is output.

In the random access memory circuit 18, the 2-channel audio data DADT that is sequentially input as in the recording is sequentially output as it is,
In the digital-analog conversion circuit 36, the audio data of the two channels are sequentially converted into the analog signal S2.
A and S2B are converted and output. As a result, the digital audio tape recorder 1 can sequentially reproduce the two-channel audio signals S2A and S2B recorded in the standardized format of the digital audio tape recorder 1 of this type.

On the other hand, in the edit mode, the digital audio tape recorder 1 causes the recording signal generation circuit 24 and the reproduction signal processing circuit 30 to operate in the same manner as in the recording and reproduction mode, respectively, and causes the random access memory circuit 18 to operate the audio data. ADDT and DADT are time-divisionally processed. Further, in the digital audio tape recorder 1, in this state, the data latch circuit 32
The audio data D2A and D2B output from the mixer are edited by the mixer circuit 14 and output to the random access memory circuit 18, whereby the two-channel audio recorded in a standardized format for a digital audio tape recorder of this type. A signal can be read after write.

(2-2) 32 [kHz] 4 channel mode In the digital audio tape recorder 1, if the user sets the number of channels to 4 channels and then sets the sampling frequency to 32 [kHz], 32 [kHz]
The mode is switched to the 4-channel mode, and the digital audio signal is recorded and reproduced in accordance with the format standardized for the 32 [kHz] 4-channel mode.

That is, in this mode, since one frame period is 30 [msec], the system control circuit 10 sets the period of the reference signal EXSY in the same manner as when the standard time mode of the normal mode is selected. Then
As a result, a pair of recording tracks can be formed at a period of 30 [msec].

On the other hand, in the analog digital conversion circuit 12, in the recording mode and the editing mode,
4 channel audio signals S1A to S1D at sampling frequency 32 [kHz] are converted to digital audio signal D.
1A to D1D are converted and output. On the other hand, as shown in FIG. 2, in the data latch circuit 16 and the random access memory circuit 18, in the recording mode and the editing mode, the arrangement of the audio data which is sequentially input is switched, whereby the sampling frequency of 32 [kHz] is 4
The channel audio data D1A to D1H are converted into 2-channel audio data DADT having a sampling frequency of 64 [kHz] and output.

Here, in FIG. 2, the reference signal EXSY is used.
Data input / output of the random access memory circuit 18 is represented with reference to FIG. 2 (A), and at the time of recording (represented by the symbol REC (FIG. 2 (C))), the audio of the first and second channels is sequentially displayed. Data (denoted by numeral 0), audio data for the third and fourth channels (denoted by numeral 1),
The audio data of the first and second channels (represented by numeral 3), ..., which are continuously input in the order of, are sequentially input in the order of input as shown by the numerals 0, 1, 2, 3 ,. Store.

Further, at the time of recording, in the random access memory circuit 18, the stored audio data corresponds to the numbers 0, 1, 2, 3, ..., 3839 at the time of storage, and the numbers 0, 2 ,. 1, 3, ..., 3839, the audio data of the first and second channels (represented by numeral 0), the audio data of the first and second channels (represented by numeral 2) ,. The audio data of the third and fourth channels (represented by numeral 1), the audio data of the third and fourth channels (represented by numeral 3), and so on are output in this order.

As a result, the reference signal E is similarly obtained in FIG.
As shown with reference to XSY (FIG. 3 (A)), in the digital audio tape recorder 1, the recording signal generation circuit 24 again performs the interleave processing to generate the recording signal S1 (FIG. 3 (B)). After first recording audio data of the first and second channels (denoted by symbols A and B) for a pair of recording tracks,
Next, after the third and fourth channel audio data (denoted by symbols C and D) are recorded to form the first recording track, the third and fourth channel audio data, the first and the second audio data are subsequently recorded. 2 Channel audio data is recorded to form a subsequent recording track.

Therefore, the random access memory circuit 18
In the above, by rearranging the data as described above, the audio data of 4 channels (Fig. 3 (D))
Regarding, regarding the first half and second half of one frame period, two-channel audio data ADDT is generated so that the first and second channel audio data and the third and fourth channel audio data are continuous ( FIG. 3C).

In response to this, in the recording signal generating circuit 24, the audio data ADDT is operated at twice the operating speed as compared with the normal sampling frequency 32 [kHz] mode.
Is converted into a recording signal S1, so that the digital audio tape recorder 1 can record digital audio signals D1A to D1H of 32 [kHz] 4 channels in accordance with the standard.

On the other hand, at the time of reproduction, in the digital audio tape recorder 1, the reproduction signal processing circuit 30 is operated at an operating speed twice as high as that of the normal sampling frequency 32 [kHz] mode. The audio data DADT in which the audio data of the first and second channels, the audio data of the third and fourth channels, the audio data of the third and fourth channels, and the audio data of the first and second channels are sequentially consecutive
(FIG. 3C) is reproduced.

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
, 3838, 1, 3, ..., 3839, the audio data of the first and second channels (represented by numeral 0),
Audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), Audio data of the third and fourth channels (represented by numeral 4), After storing this audio data DADT in the order of ..., the numbers 0, 1, 2,
3, ... As shown in 3839, audio data of the first and second channels (represented by numeral 0), audio data of the third and fourth channels (represented by numeral 1), audio data of the first and second channels (Represented by the number 3), ...
Are output in this order, and the audio data at the time of recording is reproduced via the data latch circuit 32.

The 4-channel digital audio signals D2A to D2D thus reproduced are converted into analog signals by the digital-analog conversion circuit 36 and output, whereby the 4-channel audio signals S2A to S2.
It is possible to reproduce D. Thus, in the digital audio tape recorder 1, the recording signal generating circuit 24 and the reproduction signal processing circuit 30 which are applied to the normal digital audio tape recorder 1 are operated at a double frequency, and 32 [kH
z] Digital audio signals of 4 channels can be recorded and reproduced.

On the other hand, in the edit mode, the recording signal generation circuit 24 and the reproduction signal processing circuit 30 are operated in the same manner as during recording and reproduction, and the mixer 14 performs the editing process.
As a result, the digital audio tape recorder 1 can perform write-after read even in the 32 [kHz] 4 channel mode.

(2-3) 44.1 [kHz] 4 channel mode On the other hand, when the user sets the number of channels to 4 channels and then sets the sampling frequency to 44.1 [kHz], in the digital audio tape recorder 1, Switch to 44.1 [kHz] 4 channel mode.

As shown in FIG. 4A with reference to the reference signal EXSY, in this mode, the digital audio tape recorder 1 sets the frame period F to 15 [mse].
c) so that a pair of recording tracks are formed with a period of 15 [msec] which is 1/2 of that in the case of a normal 44.1 [kHz] format.

Further, in the analog digital conversion circuit 12, in the recording mode, the sampling frequency 4
Audio signal S1A of 4 channels at 4.1 [kHz]
S1D is converted into digital audio signals D1A to D1D and output, and in the data latch circuit 16 and the random access memory circuit 18, the arrangement of the sequentially input audio data is switched and multiplexed in the recording mode and the editing mode. Converts audio data of sampling frequency 44.1 [kHz] 4 channels to audio data DADT of sampling channel 88.2 [kHz] and 2 channels.

At this time, the random access memory circuit 18
In the above, the audio data that is sequentially input is interleaved in units of two frames, whereby the cycle of forming a pair of recording tracks is set to each audio data D1.
Even if it is not held at an integral multiple of the sampling period of A to D1H, the recording signal generating circuit 24 and the reproduction signal processing circuit 30 are operated at a double operating speed to obtain a 4-channel sampling frequency of 44.1 [kHz]. The audio data D1A to D1D can be recorded and reproduced.

That is, if the audio data D1A to D1D sequentially input in units of two frames are interleaved, the audio data is processed in 30 [msec] to obtain the following equation.

[Equation 1] It is found that the audio data D1A to D1D sequentially input can be assigned to each recording track and recorded.

At the time of this recording, in the digital audio tape recorder 1, of the pair of recording tracks,
The random access memory circuit 18 performs interleave processing so that the first and second recording tracks are assigned the audio data of the first and second channels and the audio data of the third and fourth channels, respectively.

That is, the random access memory circuit 18
In the recording mode, the audio data of the first and second channels (represented by numeral 0), the audio data of the third and fourth channels (represented by numeral 1), the audio data of the first and second channels ( Numbers 0, 1, 2, 3, ... for audio data ADDT that are input continuously in this order.
, 5290 and 5291 are sequentially stored in the order of input (FIG. 4C).

Further, in the random access memory circuit 18, in the recording mode, the stored audio data ADDT are stored in the numbers 0, 1, 2, 3 ,.
Numbers 0, 2, 4 ..., 5290, 1, corresponding to 5290, 5291
As shown in 3, ..., 5291, the audio data of the first and second channels (represented by numeral 0), the audio data of the first and second channels (represented by numeral 2), the first and second channels of Audio data (represented by numeral 4)
.., the third and fourth channels of audio data (represented by numeral 1), the third and fourth channels of audio data (represented by numeral 3), ... The first and second channels of audio data are assigned to the first half of the two frames to be interleaved in step 1, and the third and fourth channels of audio data are assigned to the subsequent second half of the frame.

In FIG. 5, the reference signal EXSY (FIG.
As shown on the basis of (A)), in the recording signal generating circuit 24 corresponding to the audio data ADDT (FIG. 5C), the normal sampling frequency is 44.1 [kHz].
] The audio data ADDT is converted into the recording signal S1 at an operating speed twice as fast as that of the mode (FIG. 5C).
As a result, the audio data of the first and second channels are allocated and recorded in the pair of recording tracks formed in the first half frame, and the audio tracks of the third and fourth channels are recorded in the pair of recording tracks formed in the subsequent second half frame. Data is allocated and recorded (FIGS. 5B and 5D).

On the other hand, at the time of reproduction, in the digital audio tape recorder 1, the reproduction signal processing circuit 30 is operated at twice the operating speed as compared with the normal mode of the sampling frequency of 44.1 [kHz]. First in sequence
After the audio data of the second and second channels continues for one frame period, the audio data DADT (FIG. 5C) in which the audio data of the third and fourth channels continues for one frame period is reproduced.

In the digital audio tape recorder 1, the recording signal generation circuit 24 and the reproduction signal processing circuit 30 perform interleave processing, error correction processing, and the like on a frame-by-frame basis, so that audio data AD
The recording signal S for the DT and the reproduction signal SPB, respectively.
1 and audio data DADT are output after being delayed by a predetermined frame period.

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
..., 5290, 1, 3, ..., 5291, as shown by 5291, audio data of the first and second channels (represented by numeral 0),
Audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), Audio data of the third and fourth channels (represented by numeral 4), After storing the reproduced audio data DADT in the order of ……, the numbers 0, 1,
2, 3, ... 5290, 5291 as shown in the first and second channel audio data (represented by numeral 0), the third and fourth channel audio data (represented by numeral 1),
The audio data of the first and second channels (represented by numeral 3) are output in the order of ..., By this, the audio data at the time of recording is reproduced through the data latch circuit 32.

Thus, the random access memory circuit 18
The recording signal generation circuit 24 and the reproduction signal processing circuit 3 applied to the normal digital audio tape recorder 1 by performing interleaving processing at a cycle of 2 frames.
It is also possible to record and reproduce 44.1 [kHz] 4 channel digital audio signals by operating 0 at twice the frequency.

By the way, in this way, the audio data of the first and second channels are allocated and recorded in a pair of recording tracks formed in the first half one frame in units of two frames, and the pair of recording formed in the subsequent second half frame. When allocating and recording audio data of the third and fourth channels to the track, it is necessary to identify and process the first half frame and the second half frame during reproduction.

That is, if one frame in the first half and the latter half is erroneously processed, the audio signals S1A and S1B assigned to the first and second channels and recorded and the audio signals S1C and S assigned to the third and fourth channels are recorded.
1D is reproduced as audio signals S2C and S2D of the third and fourth channels, and audio signals S2A and S2B of the first and second channels, respectively. Therefore, in this embodiment, the system control circuit 10 detects the frame address of the reproduced audio data and determines the lowest bit of this frame address as the identification data O / E.
Is output to the random access memory circuit 18 to correctly demodulate the channel.

In practice, in this type of digital audio tape recorder 1, frame data whose values are cyclically changed in one frame cycle within a value range of 0 to 16 is recorded as a subcode. . As a result, the digital audio tape recorder 1 can reliably reproduce the multichannel audio data with reference to the subcode frame data.

On the other hand, in the edit mode, the digital audio tape recorder 1 has the recording signal generating circuit 2
4. The reproduction signal processing circuit 30 is operated in the same manner as at the time of recording / reproduction, and editing processing is performed by the mixer 14, whereby 44.1
[KHz] In the 4 channel mode, write-after read is also possible.

(2-4) 48 [kHz] 4 channel mode On the other hand, when the user sets the number of channels to 4 channels and then sets the sampling frequency to 48 [kHz], in the digital audio tape recorder 1, Switch to 48 [kHz] 4 channel mode.

As shown in FIG. 6 with reference to the reference signal EXSY (FIG. 6 (A)), in this mode, the digital audio tape recorder 1 sets one frame period F.
It is set to 15 [msec], so that a pair of recording tracks is formed with a period of 15 [msec] which is 1/2 of that in the case of a normal 48 [kHz] format.

Further, in the analog digital conversion circuit 12, in the recording mode, the sampling frequency 48
4kHz audio signals S1A-S1 at [kHz]
D is converted into digital audio signals D1A to D1D and output, and in the data latch circuit 16 and the random access memory circuit 18, the array of sequentially input audio data is switched and multiplexed in the recording mode and the edit mode. Sampling frequency 48
The 4-channel audio data of [kHz] is converted into the 2-channel audio data ADDT of sampling frequency 96 [kHz].

At this time, the random access memory circuit 18
In the same manner as in the case of 44.1 [kHz] 4 channel mode, the audio data sequentially input is interleaved in units of 2 frames, thereby doubling the recording signal generation circuit 24 and the reproduction signal processing circuit 30. By operating at an operating speed, it is possible to record and reproduce 4-channel audio data having a sampling frequency of 48 [kHz].

That is, in the case of the sampling frequency of 48 [kHz], the period for forming a pair of recording tracks is held at an integral multiple of the sampling period of each audio data, so that in the case of the 32 [kHz] 4-channel mode. Similarly, even if the audio data is processed on a frame-by-frame basis, the 4-channel audio signal can be recorded and reproduced.

However, if this is done, 44.1 [kHz] 4
It is necessary to switch the processing procedure of the random access memory circuit 18 between the case of the channel mode.

On the other hand, in the 32 [kHz] mode, the recording time is extended by 12-bit non-linear quantization of audio data, while it is 44.1 [kHz].
] In both the mode and the 48 [kHz] mode, 16-bit linear quantization of audio data is processed.

Therefore, in the digital audio tape recorder 1, it is necessary to switch the processing of audio data between the 32 [kHz] mode, the 44.1 [kHz] mode and the 48 [kHz] mode. In this case, 44.1 [kHz] 4
If the processing is switched between the channel mode and the 48 [kHz] 4 channel mode, there is a drawback that the entire configuration becomes complicated accordingly.

Therefore, in this embodiment, 48 [kHz
] In 4 channel mode, the audio data is processed in the same way as in 44.1 [kHz] 4 channel mode,
As a result, the overall structure can be simplified. By doing this, as if the 48 [kHz] 4 channel mode was set for the 48 [kHz] 2 channel mode, 32 [kHz] for the 32 [kHz] 4 channel mode.
8 channel mode can be set, which can further improve usability.

That is, the random access memory circuit 18
In the same way as in the 44.1 [kHz] 4 channel mode, in the recording mode, the audio data of the first and second channels (represented by the number 0), the audio data of the third and the fourth channel (in the number 1) , 0, 1, 2, 3, ..., 5758, for the audio data ADDT to be continuously input in the order of), first and second channels of audio data (represented by numeral 3), ....
Sequentially stored in input order as indicated by 5759 (Fig. 6
(C)). In this case, the sampling frequency is 44.1
The number of samples in 2 frame units is larger than that in the case of FIG. 4 because of the difference from the case of the [kHz] 4 channel mode.

Further, in the random access memory circuit 18, in the recording mode, the stored audio data ADDT are stored in the numbers 0, 1, 2, 3 ,.
Numbers 0, 2, 4 ..., 5758, 1, corresponding to 5758, 5759
3, ..., As shown by 5759, the audio data of the first and second channels (represented by numeral 0), the audio data of the first and second channels (represented by numeral 2), the first and second channels of Audio data (represented by numeral 4)
.., the third and fourth channels of audio data (represented by numeral 1), the third and fourth channels of audio data (represented by numeral 3), ... The first and second channels of audio data are assigned to the first half of the two frames to be interleaved in step 1, and the third and fourth channels of audio data are assigned to the subsequent second half of the frame.

As a result, the reference signal EXSY in FIG.
As shown with reference to FIG. 7A, the recording signal generating circuit 24 corresponding to the audio data ADDT (FIG. 7C) has a normal sampling frequency of 48.
The audio data ADDT is converted into a recording signal at an operation speed twice as high as that of the [kHz] mode, so that the audio data of the first and second channels is recorded in the pair of recording tracks formed in the first half frame. The data is allocated and recorded, and the audio data of the third and fourth channels is allocated and recorded to the pair of recording tracks formed in the subsequent one frame (FIGS. 7B and 7D).

On the other hand, at the time of reproduction, in the digital audio tape recorder 1, the reproduction signal processing circuit 30 is operated at a speed twice as high as that of the normal sampling frequency 48 [kHz] mode. The audio data D in which the audio data of the first and second channels are sequentially continuous for one frame period and then the audio data of the third and fourth channels are continuously for one frame period
The ADT (FIG. 6C) is reproduced.

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
..., 5758, 1, 3, ..., as shown by 5759, audio data of the first and second channels (represented by numeral 0),
Audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), Audio data of the third and fourth channels (represented by numeral 4), After storing the reproduced audio data ADDT in the order of ..., the numbers 0, 1,
2, 3, ..., 5758 and 5759, the first and second channel audio data (represented by numeral 0), the third and fourth channel audio data (represented by numeral 1), the first and second The two-channel audio data (represented by numeral 3) is output in the order of ..., By this, the audio data at the time of recording is reproduced through the data latch circuit 32.

Thus, the audio data is processed in the same manner as in the case of the 44.1 [kHz] 4 channel mode to obtain 48 [kHz].
] It is also possible to record / reproduce and perform write-after-read also with respect to a 4-channel digital audio signal.

(2-5) 32 [kHz] 8 channel mode On the other hand, when the user sets the number of channels to 8 channels, the digital audio tape recorder 1 switches to the 32 [kHz] 8 channel mode, as shown in FIG. As shown with reference to the reference signal EXSY (FIG. 8A), one frame period F is set to 15 [msec].

In the recording mode, the analog digital conversion circuit 12 has a sampling frequency of 32 [kHz
], The 8-channel audio signals S1A to S1H are converted into digital audio signals D1A to D1H and output, and in the data latch circuit 16 and the random access memory circuit 18, the audio data sequentially input in the recording mode and the editing mode is input. The array is switched and multiplexed, so that the sampling frequency is 32 [kHz
] 8 channels of audio data are converted into 2 channels of audio data ADDT of sampling frequency 128 [kHz] and output.

At this time, the random access memory circuit 18
In, 44.1 [kHz] 4 channel mode and 48
As in the case of the [kHz] 4 channel mode, the audio data that is sequentially input is interleaved in units of 2 frames, whereby the recording signal generation circuit 24 and the reproduction signal processing circuit 30 are operated at the normal 32 [kHz] 4 The digital audio signals D1A to D1H having a sampling frequency of 32 [kHz] 8 channels can be recorded and reproduced by operating at twice the operating speed of the channel mode.

That is, the random access memory circuit 18
In the above, the audio data is sequentially and cyclically fetched from the data latch circuit 16 so that the audio data of the first and second channels, the audio data of the third and fourth channels, the audio data of the fifth and sixth channels, and the seventh audio data. And the 8th channel audio data, the 1st and 2nd channel audio data ... in sequence, input the audio data ADDT, as shown by the numbers 0, 1, 2, 3, ..., 7678, 7679. Are sequentially stored in the input order (FIG. 8C).

In this case, the sampling frequency is 32
Since the number of channels in [kHz] is 8 channels, the number of samples in 2 frame units becomes 7679 samples.

Further, in the random access memory circuit 18, in the recording mode, the stored audio data ADDT are stored in the numbers 0, 1, 2, 3 ,.
The numbers 0, 4 ..., 7676, 1, 5, corresponding to 7678, 7679
..., 7677, 2, 6, ..., 7678, 3, 7, ..., 7679
As shown in, after the audio data of the first and second channels continues for 1/2 frame period, the audio data of
And the audio data of the fourth channel continues for 1/2 frame period, and the audio data of the fifth and sixth channels and the audio data of the seventh and eighth channels continue for 1/2 frame period, respectively.
Output audio data.

As a result, the reference signal EXSY in FIG.
As shown with reference to FIG. 9A, the sampling frequency 32 [kHz] is applied to the recording signal generation circuit 24 in correspondence with the audio data ADDT (FIG. 9C).
The audio data ADDT is converted into a recording signal S1 at a double operation speed in the case of the 4-channel mode, whereby the first half 1 frame is further divided into the first half and the second half, and the audio data of the first and second channels respectively. The audio data of the third and fourth channels are assigned and recorded, and the subsequent one frame is further divided into the first half and the second half, and the audio data of the fifth and sixth channels and the audio data of the seventh and eighth channels, respectively. Are assigned and recorded (FIGS. 9B and 9D).

On the other hand, during reproduction, the digital audio tape recorder 1 has a sampling frequency of 32.
[KHz] The reproduction signal processing circuit 30 is operated at twice the operating speed of the 4 channel mode, whereby the audio data of the first and second channels, the audio data of the 3rd and 4th channels, and the 5th and 6th channels are sequentially operated. The audio data DADT (FIG. 6 (C)) in which the audio data of the channels and the audio data of the seventh and eighth channels are consecutive in a 1/2 frame period are reproduced.

The random access memory circuit 18 is shown in FIG.
As shown in (B), numbers 0, 4, ..., 7676, 1,
5, ..., 7677,2,6, ..., 7678,3,7, ...,
7679, the audio data of the first and second channels, the audio data of the third and fourth channels, the audio data of the fifth and sixth channels, the seventh
And 8th channel audio data are 1 / each
Audio data DADT consecutive in two frame periods are sequentially stored, and as shown by numerals 0, 1, 2, 3, ... 7678, 7679, audio data of the first and second channels,
Output the audio data of the 3rd and 4th channels, the audio data of the 5th and 6th channels, the audio data of the 7th and 8th channels, the audio data of the 1st and 2nd channels, and so on. The audio data at the time of recording is reproduced via the data latch circuit 32.

Thus, as in the case of the 44.1 [kHz] 4-channel mode, the audio data can be interleaved in units of 2 frame periods to record and reproduce the digital audio signal of 32 [kHz] 8 channels. , You can also read after write.

(3) Control of Memory Circuit In the digital audio tape recorder 1, the recording magnetic head 4A, 6A, 6B is arranged so that the recording magnetic head 4A, 6B is scanned backward by a predetermined number of tracks. 4B is arranged. Thus, in the digital audio tape recorder 1, after demodulating the audio data reproduced by the reproducing magnetic heads 6A, 6B, the desired channel can be edited and recorded by the recording magnetic heads 4A, 4B. It is designed so that write / read-after can be performed.

Therefore, in the system control circuit 10, in the edit mode, the reproduction signal processing circuit 30 and the recording signal generation circuit 24 are activated, and the reproduction signal S output from the reproduction magnetic heads 6A and 6B is thereby activated.
PB is processed in sequence and audio data ADDT
Can be sequentially recorded.

That is, in the digital audio tape recorder 1, the 2-channel audio data DADT output from the reproduction signal processing circuit 30 is input to the random access memory circuit 18, and in the multi-channel mode, the original plural channels are reproduced. Reproduce. Further, in the digital audio tape recorder 1, the audio data of a plurality of channels thus reproduced are output to the mixer 14, where the channels desired by the user are edited and output from the analog digital conversion circuit 12. Mixing with audio data.

Further, in the digital audio tape recorder 1, the audio data output from the mixer 14 via the random access memory circuit 18 is transferred to the digital audio tape recorder 2.
It is converted into channel audio data ADDT, and this audio data ADD is passed through the recording signal generation circuit 30.
Record T.

At this time, in the system control circuit 10, by switching the operation of the timing generator 20, the operation of the random access memory circuit 18 is switched in a time division manner between the recording system and the reproducing system, whereby the recording system and the reproducing system are reproduced. In the system, a memory circuit required for time axis expansion / compression, interleaving and deinterleaving processing is shared so that the overall configuration can be simplified.

By the way, in this type of digital audio tape recorder, in the normal operation mode,
The magnetic head can perform interleave processing, error correction processing, and the like in units of the cycle of forming a pair of recording tracks. Therefore, as shown in FIG. 10, when the audio data recorded in the pair of recording tracks represented by the symbols a and b is reproduced (FIG. 10A), the reproducing magnetic heads 6A and 6B are used in the first one frame period. The reproduction signal SPB is obtained from the recording tracks a and b (represented by the symbol PB), and the reproduced data is subjected to error correction processing in the subsequent one frame period (represented by the symbol ECC).

Further, the digital audio tape recorder 1 deinterleaves and outputs the error-corrected audio data in the subsequent one frame period (represented by symbol OUT). On the other hand, when the output audio data is directly input to the recording signal generating circuit 24 without being processed (FIG. 10).
(B)) In the digital audio tape recorder 1, this audio data is input to the recording system and interleaved at one frame cycle of deinterleave processing and output (indicated by symbol IN), and the subsequent one frame. An error correction code is generated in a cycle (denoted by the symbol OUT).

Further, in this case, in the digital audio tape recorder 1, the audio data is converted into the recording signal S1 together with the error correction code, the subcode, etc. in the subsequent one frame period and is output to the recording magnetic heads 4A, 4B (symbol. Expressed as REC). As a result, in the edit mode in which the audio data reproduced by the reproduction signal processing circuit 30 is directly input to the recording signal generating circuit 24 without any processing and recorded, only 8.5 track pitch TP is applied to the reproducing magnetic heads 6A and 6B. It is understood that the reproduced audio data can be re-recorded on the same recording track by arranging the recording magnetic heads 4A and 4B afterward.

As a result, in this type of digital audio tape recorder 1, when performing a write-after read of a 2-channel audio signal in the normal operation mode, at least 8. for the reproducing magnetic heads 6A, 6B.
5 Track head TP only trailing magnetic head 4
It is necessary to arrange A and 4B.

On the other hand, when the random access memory circuit 18 expands the time axis of the audio data output from the reproduction signal processing circuit 30, the recording / reproducing system requires processing time accordingly.

That is, the random access memory circuit 18
For audio data to be time-axis compressed and multiplexed in 1 frame units (FIG. 10 (C)), the audio data DAD output from the reproduction signal processing circuit 30
R is a random access memory circuit 18 in one frame cycle.
(Represented by symbol 4chOUT), and then demodulated into 4-channel audio data and output (represented by symbol 4chOUT) in the subsequent one frame period. Further, in the edit mode, this 4-channel audio data is input to the random access memory circuit 18 (symbol 4
chIN), the time axis is compressed in the subsequent one frame period, and the result is output to the recording signal generation circuit 24 (symbol 4 chO).
UT).

As a result, the time axis compression is performed in units of one frame,
The audio data to be multiplexed can be re-recorded on the same track by arranging the recording magnetic heads 4A and 4B after the reproducing magnetic heads 6A and 6B by 12.5 track pitch TP.

As a result, in this type of digital audio tape recorder 1, when performing write-after-read in the 32 [kHz] 4 channel mode, at least 12.5 track pitch T for the reproducing magnetic heads 6A, 6B.
It is necessary to arrange the magnetic heads 4A and 4B for recording after P.

On the other hand, regarding audio data to be time-axis compressed and multiplexed in units of two frames (see FIG.
0 (D)), after inputting the audio data DADT output from the reproduction signal processing circuit 30 to the random access memory circuit 18 at a 2-frame cycle (represented by a symbol 8chIN), 4 channels or 8 channels at a subsequent 2-frame cycle. Demodulate to audio data and output (symbol 8c
hOUT). Further, in the edit mode, the 4-channel or 8-channel audio data is input to the random access memory circuit 18 (symbol 8 ch).
IN), followed by time-axis compression in the subsequent two frame periods and output to the recording signal generation circuit 24 (symbol 8chOUT).
Represents).

As a result, the time base compression is performed in units of 2 frames,
In the audio data to be multiplexed, the reproduced audio data is recorded on the same track by arranging the recording magnetic heads 4A and 4B after the reproducing magnetic heads 6A and 6B by 16.5 track pitch TP. It can be fixed.

Thus, in this type of digital audio tape recorder 1, 44.1 [kHz] 4 channel mode, 48 [kHz] 4 channel mode, 32 [kHz]
When performing write-after read in the 8-channel mode, at least 16.5 track pitch TP follows the reproducing magnetic heads 6A and 6B, and the recording magnetic heads 4A and 4B.
B must be placed.

As a result, the random access memory circuit 1
8, in the digital audio tape recorder 1, when performing interleave processing in units of N frames, the recording heads 4A and 4B corresponding to the reproducing magnetic heads 6A and 6B are provided with the head step difference represented by the following general formula. The audio data D2A to D2H output from the random access memory circuit 18 by arranging m
It can be seen that can be recorded in the original recording track.

[Equation 2]

That is, as described above, the magnetic heads 4A to 6B are
With the above arrangement, write-after read can be performed in each operation mode without providing a dedicated buffer memory circuit or the like for time adjustment.

In this case, in a multi-channel digital audio tape recorder, when write-after-read is performed by switching the number of channels, a magnetic head for recording and a magnetic head for reproduction are prepared by the amount corresponding to the head step, and the rotary drum is constructed accordingly. Is complicated and impractical.

Therefore, as shown in FIG. 11, in this embodiment, the digital audio tape recorder 1 is
The maximum head step m (16.5T) required in the operation mode of this digital audio tape recorder 1
Place the magnetic heads 4A to 6B in P), 8.5 TP, 12.5
When the head level difference of TP is required, the random access memory circuit 18 delays the audio data accordingly.

As a result, the digital audio tape recorder 1 can perform write-after-read by changing the number of channels with a simple structure.

Therefore, in the digital audio tape recorder 1, as shown in FIG.
Is set to 16.5 TP, the track length is L, the track angle is φ, the distance between the scanning start ends of the corresponding recording tracks is n, and the reproducing magnetic heads 6A and 6B to the corresponding recording magnetic heads 4A and 4B. Let x be the angle up to

[Equation 3]

[Equation 4] By solving this equation, the reproducing magnetic heads 6A and 6B can be replaced by the corresponding recording magnetic heads 4A and 4B.
The reproducing magnetic heads 6A and 6B and the recording magnetic heads 4A and 4B are arranged so that the angle between them is about 82 °.

Further, as shown in FIG. 13, in the normal operation mode, in the timing generator 20, the address of the random access memory circuit 18 is increased so that the value sequentially increases in two frame periods (FIG. 13A). Data is generated (FIGS. 13B to 13D), whereby the reproduced audio data DADT and ADDT (D2A and D2B) are sequentially stored and output in the recording system and the reproducing system.

At this time, in the timing generator 20, the stored audio data DADT, ADDT
Respectively generate address data in the recording system and the reproducing system so as to be delayed by a period of two frames, thereby delaying the output data of the reproduction signal processing circuit 24 by a period of four frames as a whole and outputting it to the recording signal generation circuit 24. To do.

Accordingly, in the digital audio tape recorder 1, the operation modes are 44.1 [kHz] 4 channel mode, 48 [kHz] 4 channel mode and 32 [kH
z] Even when the 8-channel mode is switched to the normal operation mode, the write-after read can be performed for the 2-channel audio signal by simply switching the address data generated by the timing generator 20.

On the other hand, in the 32 [kHz] 4 channel mode, the interleave processing is performed by the random access memory circuit 18, and the audio data A is also added.
The DDT and DADT are delayed by one frame period, whereby the audio data is also delayed by two frame periods in the recording / reproducing system.

Therefore, as shown in FIG. 14, in the timing generator 20, in practice, as shown by doubling the numbers in correspondence with FIG. 2, the address data can be interleaved in one frame period. Is generated (FIGS. 14A to 14C), and this address data is
It is generated so as to be repeated at the frame cycle.

That is, as shown in FIG. 15, when the audio data ADDT and DADT are stored, in the timing generator 20, the lower 2nd bit is set to the value "0" and the value "1" during the first half frame and the second half frame, respectively. ", And the remaining bits are sequentially counted up by the value" 1 "to generate address data.

On the other hand, at the time of reproduction, in the timing generator 20, the lower 2 bits are held at the value "0, 0" and the remaining upper bits are sequentially counted up from the value "0" by the value "1". When the remaining high-order bits reach the value "1919", the low-order 2 bits are counted up, and the remaining high-order bits are counted up again by the value "0" from the value "0". The timing generator 20 then repeats this counting operation for the lower 2 bits of the value "1,0", and then repeats this counting operation for the lower 2 bits of the value "1,1". The access memory circuit 18 performs interleave processing, and at the same time, performs audio data ADDT, DA
DT is delayed by one frame period and then output.

As a result, the operation mode of the digital audio tape recorder 1 is 44.1 [kHz] 4 channel mode, 48 [kHz] 4 channel mode, 32 [kH].
Even if the z] 8 channel mode is switched to the 32 [kHz] 4 channel mode, or even if the 32 [kHz] 4 channel mode is switched to the normal operation mode, the address data generated by the timing generator 20 can be simply switched. It is possible to write-after-read for 4 channel and 2 channel audio signals.

(4) Effects of the Embodiments According to the above configuration, in the digital audio tape recorder for recording / reproducing audio data of multichannel by time-axis compression / decompression of audio data, time-axis compression / expansion memory circuit. 44.1 [kHz] and 48 [kHz] 4 channel modes, by switching the operation of 4 and delaying audio data for a predetermined time.
Operation of the timing generator even when switching from 32 [kHz] 8 channel mode to 32 [kHz] 4 channel mode or normal operation mode, and further when switching from 32 [kHz] 4 channel mode to normal operation mode You can easily perform write-after-read by simply switching.

(5) Other Embodiments In the above embodiments, the case where the audio data is delayed by one frame period or two frame periods in the recording system and the reproducing system has been described, but the present invention is not limited to this. Not limited to this, the delay may be performed by either the recording system or the reproducing system.

Further, in the above embodiment, the case where the random access memory circuit is shared by the recording system and the reproducing system is described, but the present invention is not limited to this, and the memory circuit dedicated to the recording system and the reproducing system respectively. May be provided.

[0131]

As described above, according to the present invention, the reproducing audio data is recorded at the same location on the magnetic tape with respect to the recording magnetic head arranged by the predetermined track pitch on the trailing side with respect to the reproducing magnetic head. By delaying and processing the audio data in the memory circuit that compresses and / or expands the time axis in the multi-channel mode,
It is possible to obtain a magnetic recording / reproducing apparatus with a simple structure capable of performing write-after read even if the number of channels is switched.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital audio tape recorder according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining the operation of a random access memory circuit in a 32 [kHz] 4-channel mode.

FIG. 3 is a signal waveform diagram for explaining a recording / reproducing operation in a 32 [kHz] 4-channel mode.

FIG. 4 is a schematic diagram for explaining an operation of a random access memory circuit in a 44.1 [kHz] 4 channel mode.

FIG. 5 is a signal waveform diagram for explaining a recording / reproducing operation in a 44.1 [kHz] 4-channel mode.

FIG. 6 is a schematic diagram for explaining the operation of a random access memory circuit in a 48 [kHz] 4-channel mode.

FIG. 7 is a signal waveform diagram for explaining a recording / reproducing operation in a 48 [kHz] 4-channel mode.

FIG. 8 is a schematic diagram for explaining the operation of a random access memory circuit in a 32 [kHz] 8-channel mode.

FIG. 9 is a signal waveform diagram for explaining a recording / reproducing operation in a 32 [kHz] 8-channel mode.

FIG. 10 is a schematic diagram for explaining a head step.

FIG. 11 is a schematic diagram showing a head step.

FIG. 12 is a schematic diagram for explaining angle division.

FIG. 13 is a schematic diagram for explaining the operation of the random access memory circuit in a normal operation mode.

FIG. 14 is a schematic diagram for explaining the operation of the timing generator in the 32 [kHz] 4-channel mode.

FIG. 15 is a schematic diagram for explaining address data at the time of writing.

FIG. 16 is a schematic diagram for explaining address data at the time of reading.

[Explanation of symbols]

1 ... Digital audio tape recorder, 2 ... rotating drum, 4A, 4B, 6A, 6B ... magnetic head, 1
0 ... System control circuit, 12 ... Analog digital conversion circuit, 18 ... Random access memory circuit, 24
...... Recording signal generation circuit, 30 ...... Reproduction signal processing circuit, 3
6 ... Digital analog conversion circuit.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

In the random access memory circuit 18, the data latch circuit 16 is based on the identification data O / E output from the system control circuit 10 with reference to the address data AD output from the timing generator (TG) 20. And 22 are sequentially stored and output in a predetermined order.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

The system control circuit 10 switches the entire operation in response to a user's operation and based on the sub-code data output from the reproduction signal processing circuit 30. Thereby, the entire digital audio tape recorder 1 is required. It is designed to operate in various operating modes. At this time, the system control circuit 10 outputs the identification data O / E to the timing generator 20 based on the frame address reproduced by the reproduction signal processing circuit 30, thereby controlling the operation of the random access memory circuit 18. .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

Further, in the system control circuit 10,
A digital signal processing circuit (DSP) 40 is driven, so that the digital signal processing circuit 40 moves to the rotary drum 40.
It outputs the reference signal EXSY synchronized with the rotation cycle of, the bit clock BCK, and the like. The timing generator 20 receives the reference signal EXSY and the bit clock BCK.
Also, the address data of the random access memory circuit 18 is output based on the identification data O / E, and the clocks CK and LRCK for operation reference are output.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0070

[Correction method] Change

[Correction content]

That is, if one frame in the first half and the latter half is erroneously processed, the audio signals S1A and S1B assigned to the first and second channels and recorded and the audio signals S1C and S assigned to the third and fourth channels are recorded.
1D is reproduced as audio signals S2C and S2D of the third and fourth channels, and audio signals S2A and S2B of the first and second channels, respectively. Therefore, in this embodiment, the system control circuit 10 detects the frame address of the reproduced audio data and determines the lowest bit of this frame address as the identification data O / E.
Is output to the timing generator 20 to correctly demodulate the channel.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0102

[Correction method] Change

[Correction content]

At this time, in the system control circuit 10, the operation of the timing generator 20 is switched to switch the operation of the random access memory circuit 18 between the recording system and the reproducing system in a time division manner. The memory circuit required for time axis expansion and compression, interleaving and deinterleaving processing is shared to simplify the overall configuration.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 27, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

On the other hand, in the multi-channel mode, the digital audio tape recorder 1 performs the error correction processing and the deinterleave processing on the reproduction data in the reproduction signal processing circuit 30, and then the random access memory circuit 1
The digital audio signal D2 of 4 channels or 8 channels recorded by being assigned to a predetermined recording track by deinterleaving processing at 8 and expanding on the time axis.
A to D2H can be reproduced.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction content]

On the other hand, in the analog digital conversion circuit 12, in the recording mode and the editing mode,
The 4-channel audio signals S1A to S1D are converted into digital audio signals D1A to D1D at a sampling frequency of 32 [kHz] and output. On the other hand, as shown in FIG. 2, in the data latch circuit 16 and the random access memory circuit 18, in the recording mode and the editing mode, the array of the audio data that is sequentially input is switched, whereby the sampling frequency 32 [kHz]
z] 4 channel audio data D1A to D1D
Is converted into 2-channel audio data DADT having a sampling frequency of 64 [kHz] and output.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

Here, in FIG. 2, the reference signal EXSY is used.
Data input / output of the random access memory circuit 18 is represented with reference to FIG. 2 (A), and at the time of recording (represented by the symbol REC (FIG. 2 (C))), the audio of the first and second channels is sequentially displayed. Data (denoted by numeral 0), audio data for the third and fourth channels (denoted by numeral 1),
The audio data of the first and second channels (represented by the numeral 2) are successively input in the order of, and the audio data are sequentially input in the order of input as shown by the numerals 0, 1, 2, 3 ,. Store.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction content]

Correspondingly, in the recording signal generating circuit 24, the audio data AD is operated at a speed twice as high as that of the normal sampling frequency 32 [kHz] mode.
DT is converted into a recording signal S1, and thus, in the digital audio tape recorder 1, 32 [kHz]
4 channel digital audio signals D1A to D1
D can be recorded according to the standard.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
..., 3838, 1, 3, ..., as shown by 3839,
Audio data of the first and second channels (represented by numeral 0), audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), After storing this audio data DADT in the order of the 3rd and 4th channel audio data (represented by numeral 3), ..., As shown by the numerals 0, 1, 2, 3 ,. The audio data of the second channel (represented by numeral 0), the audio data of the third and fourth channels (represented by numeral 1), the audio data of the first and second channels (represented by numeral 2), and so on. Then, the audio data at the time of recording is reproduced via the data latch circuit 32.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction content]

At this time, the random access memory circuit 18
In the above, the audio data that is sequentially input is interleaved in units of two frames, whereby the cycle of forming a pair of recording tracks is set to each audio data D1.
Even if it is not held at an integral multiple of the sampling cycle of A to D1D, the recording signal generation circuit 24, the reproduction signal processing circuit 30 and the like are operated at a double operating speed to obtain a sampling frequency of 44.1 kHz. The channel audio data D1A to D1D can be recorded and reproduced.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0062

[Correction method] Change

[Correction content]

That is, the random access memory circuit 18
In the recording mode, the audio data of the first and second channels (represented by numeral 0), the audio data of the third and fourth channels (represented by numeral 1), the audio data of the first and second channels ( Numbers 0, 1, 2, 3, ... for audio data ADDT that are input continuously in this order.
, 5290 and 5291 are sequentially stored in the input order (FIG. 4C).

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0067

[Correction method] Change

[Correction content]

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
..., 5290, 1, 3, ..., as shown by 5291,
Audio data of the first and second channels (represented by numeral 0), audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), After storing the reproduced audio data DADT in the order of the third and fourth channel audio data (represented by numeral 3), ..
As shown by the numbers 0, 1, 2, 3, ... 5290, 5291, the audio data of the first and second channels (represented by the number 0), the audio data of the third and fourth channels (represented by the number 1), The audio data of the first and second channels (represented by numeral 2) are output in this order, and the audio data at the time of recording is reproduced via the data latch circuit 32.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0082

[Correction method] Change

[Correction content]

That is, the random access memory circuit 18
In the same manner as in the 44.1 [kHz] 4 channel mode, in the recording mode, the first and second
Channel audio data (denoted by numeral 0), 3rd
And the 4th channel audio data (represented by numeral 1), the 1st and 2nd channel audio data (represented by numeral 2), ... 2, 3, ...
, 5758 and 5759 are sequentially stored in the input order (FIG. 6C). In this case, since the sampling frequency is different from the case of the 44.1 [kHz] 4 channel mode, the number of samples per 2 frames becomes larger than that in the case of FIG.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0086

[Correction method] Change

[Correction content]

The random access memory circuit 18 is shown in FIG.
As shown in (B), the numbers 0, 2, ...
..., 5758, 1, 3, ..., as shown by 5759,
Audio data of the first and second channels (represented by numeral 0), audio data of the first and second channels (represented by numeral 2) ..., Audio data of the third and fourth channels (represented by numeral 1), After storing the reproduced audio data ADDT in the order of the third and fourth channel audio data (represented by numeral 3) ,.
As indicated by the numbers 0, 1, 2, 3, ..., 5758, 5759, the audio data of the first and second channels (represented by the number 0) and the audio data of the third and fourth channels (represented by the number 1) , 1st and 2nd channel audio data (represented by numeral 2), ...
As a result, the audio data at the time of recording is reproduced via the data latch circuit 32.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0104

[Correction method] Change

[Correction content]

Further, the digital audio tape recorder 1 deinterleaves and outputs the error-corrected audio data in the subsequent one frame period (represented by symbol OUT). On the other hand, when the output audio data is directly input to the recording signal generating circuit 24 without being processed (FIG. 10).
(B)) In the digital audio tape recorder 1, this audio data is input to the recording system and interleaved at one frame cycle of deinterleave processing and output (indicated by symbol IN), and the subsequent one frame. An error correction code is generated in a cycle (denoted by the symbol ECC).

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0114

[Correction method] Change

[Correction content]

As a result, the random access memory circuit 1
8, in the digital audio tape recorder 1, when performing interleave processing in units of N frames, the recording heads 4A and 4B corresponding to the reproducing magnetic heads 6A and 6B are provided with the head step difference represented by the following general formula. The audio data D2A to D2H output from the random access memory circuit 18 by arranging m
Can be recorded on the original recording track. m = (8.5 + 4N) TP (2)

Claims (1)

[Claims] 1. A magnetic recording / reproducing apparatus for sequentially recording a pair of recording tracks of positive and negative azimuth angles on a magnetic tape to record audio data, wherein a reproducing magnetic head arranged on a rotary drum is used. The reproduced signal output is processed to obtain reproduced data, and the reproduced magnetic head performs error correction processing on the reproduced data in units of the period of scanning the pair of recording tracks. Playback means for deinterleaving the pair of recording tracks as a unit to output 2-channel playback audio data, and an audio data output circuit for sequentially storing and outputting the 2-channel playback audio data. , 2 channel recording by sequentially storing audio data output from the audio data output circuit The audio data input circuit for outputting audio data and the recording magnetic head disposed on the trailing side of the reproducing magnetic head on the rotating drum are driven so that the recording magnetic head forms the pair of recording tracks. After the two channels of recording audio data are interleaved in units of cycles, an error correction code is generated in units of the cycle in which the recording magnetic head forms the pair of recording tracks. The audio data output circuit comprises a recording signal generating circuit for recording the two-channel recording audio data and the error correction code on the magnetic tape through a magnetic head, and the audio data output circuit sequentially outputs the reproduction audio data in the multi-channel mode. By storing and outputting the magnetic head for reproduction, The reproduction audio data is time-axis-expanded to demodulate the audio data of M channels of 4 channels or more in units of the period of scanning the recording track, and the audio data input circuit outputs the audio data output circuit. By sequentially storing the audio data and outputting the recording audio data of the two channels, the audio data of the M channels is set as a time axis in units of the cycle in which the recording magnetic head forms the pair of recording tracks. Compress and multiplex,
The two-channel recording audio data is generated, and the recording magnetic head records the reproducing audio data reproduced through the reproducing magnetic head in the same position on the magnetic tape in the multi-channel mode. In order to obtain, the audio data output circuit and / or the audio data input circuit are arranged on the trailing side by a predetermined track pitch with respect to the magnetic head for reproduction, and the audio data output circuit and / or the audio data input circuit are reproduced through the magnetic head for reproduction in the 2-channel mode. The reproduced audio data and / or the audio data output from the audio data output circuit is output after being delayed for a predetermined period so that the reproduced audio data thus reproduced is recorded at the same location on the magnetic tape. Magnetic recording / reproducing device.