JPH06161621A - Data transmission system - Google Patents

Abstract

PURPOSE:To provide a data transmission system capable of speeding-up a data transfer by optimizing a signal waveform and making signal propagation delay time constant, in the data transmission between a control part which is different in the number of sheets of package in memory package and plural memory packages, in particular. CONSTITUTION:This system is a data transmission system where the only function necessary for the reading from a memory package is shown, a mounting memory package is made one sheet and a data transmission line, and is composed of a control part 1, a memory package 2 and plural dummy packages 3 (3A to 3M). The dummy package 3A to 3M are provided with capacitors 31A to 31M having the same input impedances as that of a driving 22 within the memory package and capacitors 32A to 32M having the same input impedances as that when a memory IC 21 stops a data output and opens an output state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system between a plurality of control units, and more particularly, in a device which uses a plurality of memory packages and has a different number of mounted memory packages, the memory package and the control unit are different from each other. The present invention relates to a technology effectively applied to a data transmission method capable of speeding up data transfer in the above.

[0002]

2. Description of the Related Art For example, in an apparatus using a plurality of memory packages, a method of providing a plurality of memory slots and mounting the required number of memory packages in the memory slots is generally used. At this time, in order to perform high-speed data transfer between the control unit and the memory package, it is necessary to make the signal propagation delay time of the control signal and the data signal for controlling the memory package constant regardless of the number of mounted memory packages. is there.

Now, with reference to FIG. 5, the necessity of making the signal propagation delay time constant irrespective of the number of mounted memory packages by the timing of reading data from the memory package will be described.

First, when reading data from a memory package, a control signal necessary for reading data is output from the control unit, and read data from the memory package is received by the control unit. However, a control signal is output to read the read data. The time until reception is determined by the time B required for reading the memory package and the signal propagation delay time A between the control unit and the memory package, which time is 2A + B.

Also, when the control signal from the control unit is cut off and the data output of the memory package is ended, the time until the read data output is cut off after the control signal is cut off, the read data output of the memory package is ended. It is determined by the time C required for this and the signal propagation delay time A between the control unit and the memory package, and the time is 2A + C.

Further, the time required for the control unit to receive the read data from the memory package is determined by the data setup time D and the data hold time E with respect to the read data receiving timing.

Therefore, the time F from the output of the control signal to the read data reception timing is 2A + B + D, and the time G from the read data reception timing to the disconnection of the control signal is E- (2A + C), which is the signal of the control signal. The width H is {2A + B + D} + {E- (2A +
C)} = B + D + E−C.

However, the signal propagation delay time A between the control unit and the memory package depends on the drive capability of the control signal drive circuit of the control unit and the load of the control signal drive circuit, and the drive of the data output drive circuit of the memory package. It depends on the capacity and the load of the data output drive circuit. Here, the same delay time is used to simplify the description. This means that the signal propagation delay time A changes if the load changes.

Here, the load of the drive circuit is the stray capacitance and inductance of the connection line connecting the memory package and the control section, the stray capacitance and inductance of the memory package mounted in the memory slot, and the stray capacitance and inductance of the memory slot. Is determined by.

In general, the connection between the control unit and the plurality of memory slots for mounting the memory package is performed by the control unit and each memory in order to simplify the control unit and reduce the number of connecting lines between the control unit and the memory slot. Instead of connecting the slots one by one, each memory slot is connected in common.

Therefore, the load of the control signal drive circuit and the load of the data output drive circuit change depending on the number of memory packages mounted in the memory slot, and the signal propagation delay time A between the control unit and the memory package also changes. To do.

That is, the control unit and each memory slot are set to 1
The signal width H of the control signal in the case of connection by pair 1 is B + D + E-C as described above, but the signal width H of the control signal in the case of commonly connecting each memory slot needs to be longer than this. is there.

Assuming that the signal propagation delay time when the number of memory packages mounted in the memory slot is the minimum is A and the signal propagation delay time when the number of memory packages is the maximum is A + ΔA, The time F from the output of the control signal when the number of mounted boards is maximum to the read data reception timing is 2 (A + ΔA) + B + D
And the time G from the read data receiving timing to the disconnection of the control signal is E- {2 (A + ΔA) + C}
Becomes

Therefore, the time F from the output of the control signal to the read data reception timing is large when the number of mounted memory packages is maximum, and conversely the time G from the read data reception timing to the disconnection of the control signal. In most cases, the number of mounted memory packages is the smallest.

Further, in order for the control unit to correctly receive the read data from the memory package, it is necessary to guarantee the data setup time D and the data hold time E with respect to the read data reception timing regardless of the number of mounted memory packages.

Therefore, the time F from the output of the control signal to the read data receiving timing is 2 (A + ΔA) + B + D when the number of mounted memory packages is maximum.
The time G from the read data reception timing to the disconnection of the control signal needs to be E- (2A + C) when the number of mounted memory packages is minimum.

From the above, the signal width H of the control signal is {2 (A + ΔA) + B + D} + {E- (2A + C)} =
B + D + E−C + 2 · ΔA, which needs to be increased by 2 · ΔA as compared with the case where the control unit and each memory slot are connected one-to-one.

This means that when data is continuously read from the memory package, the time required for one read becomes long, which is a serious problem in performing high-speed data transfer between the control unit and the memory package.

In addition, when the control section and each memory slot are connected in common, there is another problem. That is,
The signal waveform of the control signal from the control unit to the memory package or the data signal from the memory package to the control unit is determined by the characteristic impedance of the drive circuit and the characteristic impedance of the load of the drive circuit.

Therefore, when the number of mounted memory packages changes, the characteristic impedance of the load of the drive circuit changes,
The signal waveform will change. Therefore, in order to perform high-speed data transfer between the control unit and the memory package, it is necessary to optimize the signal waveforms of the control signal and the read data signal.

This differs depending on whether the connection net between the control unit and the memory package is a terminal net or a non-terminal net.
For example, in the case of a termination net, the signal waveform can be optimized by terminating with the same impedance as the characteristic impedance of the connection net. However, when terminated with an impedance different from the characteristic impedance of the connection net, the signal waveform is distorted, and the signal propagation delay time increases accordingly.

On the other hand, when the connecting net is a non-terminating net, the signal is reflected when the signal propagation is delayed because there is no termination of the net, and there is a step in the signal waveform when the overshoot or undershoot occurs and the signal level changes. Waveform distortion occurs. To prevent this, a resistor is generally inserted between the signal drive circuit and the signal net. This resistance is called a damping resistance, but this damping resistance minimizes waveform distortion and optimizes the signal waveform.

As described above, in the conventional technique, the signal waveform is optimized by the termination or the damping resistor.
Since the characteristic impedance of the load of the drive circuit changes when the number of mounted memory packages changes, it is necessary to change the termination or damping resistance each time. However, this is not practical.

Therefore, in order to simplify the connection between the control unit and the plurality of memory slots for mounting the memory package, and to reduce the number of connecting lines between the control unit and the memory slot, the control unit and the memory are connected. It is common to connect each memory slot in common at the expense of high speed data transfer between packages.

As described above, in order to perform high-speed data transfer between the control unit and the memory package, the signal propagation delay time of the control signal for controlling the memory package and the data signal is constant regardless of the number of mounted memory packages. Need to

As a conventional technique for keeping the signal propagation delay time constant, there is a method of connecting a fixed number of reference clock signals of a processor or the like to the same load.

[0027]

However, in the prior art as described above, in order to apply, for example, to the connection between the control unit and the memory package, the number of memory packages to be mounted and the number of packages actually required are Regardless of the relationship, it is necessary to always mount the maximum number of sheets or to make one-to-one connection between the control unit and the memory package, but neither is practical.

That is, when the former maximum number of memory packages is always mounted, there is a problem that more memory packages than the actually required number of memory packages are required.

In the latter case of one-to-one connection, the read data receiving circuits in the control unit are required for the number of memory packages, which makes the control unit enormous in logical scale and further requires the control unit. The connection with the memory slot for mounting the memory package is required for the number of memory packages, which causes a problem that the number of connection lines becomes enormous.

Therefore, an object of the present invention is to transmit data between a plurality of control units, particularly between a control unit having a different number of mounted memory packages and a plurality of memory packages.
It is an object of the present invention to provide a data transmission method capable of performing high-speed data transfer between a memory package and a control unit while optimizing a signal waveform and keeping a signal propagation delay time constant.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0032]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the data transmission system of the present invention has a plurality of control units and a plurality of slots, and a plurality of control units are mounted in the plurality of slots, respectively, and the plurality of slots are commonly connected to each other. A data transmission method that transfers data between multiple control units depending on the path, and the characteristic impedance of the data transmission path seen from each of the multiple control units is always constant regardless of the number of mounted control units. The impedance control means is provided.

In this case, the plurality of control units and the plurality of slots are used as a control section and a plurality of memory slots, and the control section and the plurality of memory slots are mounted in the plurality of memory slots by a data transmission line commonly connected to each other. The data transfer is performed between the single or plural memory packages and the control unit.

As the impedance control means, a dummy package that can be mounted in a memory slot and has the same characteristic impedance as the memory package is provided, and the dummy package is mounted in a memory slot in which the memory package is not mounted. Is.

Further, as the impedance control means, a dummy load capable of varying the characteristic impedance is provided in the control unit, and the dummy load is controlled to set the characteristic impedance.

Further, as the impedance control means, a dummy package having a dummy load which can be mounted in a memory slot and whose characteristic impedance can be varied is provided, and only one dummy package is mounted in a memory slot in which no memory package is mounted. In addition, the control unit is provided with control means for controlling the dummy package, and the control unit controls the dummy package to set its characteristic impedance.

Further, as the impedance control means, a dummy load capable of varying the characteristic impedance is provided in the memory package, and a control means for controlling the dummy load is provided from the control section. The impedance is set.

In this case, the dummy load is composed of a dummy load circuit having the same characteristic impedance as the memory package and a plurality of switches for connecting or disconnecting the dummy load circuit.

[0040]

According to the above-described data transmission system, the impedance control means is provided, so that the control unit and the plurality of slots, for example, the control unit and the plurality of memory slots, respectively, can be installed in one or a plurality of memory packages. It is possible to make the characteristic impedance of the data transmission path as seen always constant regardless of the number of mounted memory packages.

That is, the control section and the memory slot in which the memory package is mounted are commonly connected to each memory slot, and the impedance control means can change the characteristic impedance, for example, a dummy having the same characteristic impedance as the memory package. A dummy load whose characteristic impedance can be changed in the package, the control unit, the dummy package, or the memory package can be made possible by connecting the dummy load on the connection line between the control unit and the memory package.

As a result, by mounting the dummy package or changing the characteristic impedance of the dummy load, the load of the control section or the signal drive circuit of the memory package is always constant regardless of the number of mounted memory packages. The signal waveform can be optimized, and the signal transmission delay time between the control unit and the memory package can be made constant, so that the data transmission between the control unit and the memory package can be performed at high speed. Further, the cost increase for this can be suppressed to the minimum.

[0043]

[Embodiment 1] FIG. 1 is a functional block diagram showing a data transmission system using a dummy package according to an embodiment of the present invention.

First, the configuration of the data transmission system using the dummy package of this embodiment will be described with reference to FIG.

The data transmission system of the present embodiment shows only the functions required for reading from the memory package for the sake of simplicity of explanation, and the number of memory packages mounted on the data transmission system is one, and the data transmission path allows the memory package to be installed. And a data transmission method that transfers data between the control unit,
The control unit 1, the memory package 2, and a plurality of dummy packages (impedance control means) 3 (3A to 3M) are included. The memory package 2 and the dummy packages 3A to 3M are mounted in the plurality of memory slots 4A to 4N, respectively. Controller 1 and memory slot 4A-
4N are commonly connected through a control signal connection line 5 and a data signal connection line 6.

The control unit 1 includes a control signal driving circuit 11 for outputting a control signal, a read data receiving circuit 12,
A read data reception timing signal 13 indicating the timing of receiving the read data, and a timing generation circuit 14 for generating the control signal and the read data reception timing signal 13 are provided.

The memory package 2 is provided with a plurality of memory ICs 21 satisfying the data width required for the device and a memory package drive circuit 22 for supplying a control signal from the controller 1 to the memory IC 21. Only one 2 is mounted in the memory slot 4N.

The memory IC 21 starts its operation in response to a control signal from the control section 1, outputs the stored data after reading it, and stops the data output when the control signal is cut off. The output state is released.

The dummy packages 3A to 3M have the same circuit configuration, and the capacitors 31A to 31M each having the same input impedance as the drive circuit 22 in the memory package, and the memory IC 21 stop the data output and set the output state. Capacitors 32A to 32M having the same input impedance as when they are opened are provided, and the dummy packages 3A to 3M are mounted in the memory slots 4A to 4M where the memory package 2 is not mounted.

Next, the operation of this embodiment will be described.

First, the timing generation circuit 1 in the control unit 1
The control signal generated by 4 is output to the control signal connection line 5 by the control signal drive circuit 11, and the control signal is supplied to the memory package 2 mounted in the memory slot 4N by the control signal connection line 5.

Further, when the memory package 2 receives the control signal, the drive circuit 22 in the memory package supplies the control signal to each memory IC 21 so that the memory IC 21 receives the control signal.
Is operated to read out the data stored in each memory IC 21 and then output it.

Then, the read data from each memory IC 21 is transmitted to the read data receiving circuit 12 in the control section 1 through the data signal connecting line 6, and the read data receiving timing signal 1 from the timing generating circuit 14 is sent.
3, the read data receiving circuit 12 receives the read data.

In this case, the operation timing of each unit is 2A + B + D as the time F from the output of the control signal from the control unit 1 to the read data receiving timing is 2A + B + D as described in the prior art with reference to FIG. The time G from the data reception timing to the disconnection of the control signal is E- (2A + C), and the signal width H of the control signal is {2A
+ B + D} + {E− (2A + C)} = B + D + E−C.

Here, the signal propagation delay time A between the control unit 1 and the memory package 2 is determined by the drive capability of the control signal drive circuit 11 of the control unit 1 and the load of the control signal drive circuit 11, that is, the control signal connection line. 5, due to the stray capacitance and inductance of the data signal connection line 6 and the stray capacitance and inductance of the memory package 2 and the stray capacitance and inductance of the memory slot 4N, and also due to the driving ability of the memory IC 21 of the memory package 2 and the load of the memory IC 21. It is determined.

That is, the control unit 1 and the memory package 2
The connection between the memory slots 4N in which is mounted is common to each of the memory slots 4A to 4N, and the load of the control signal drive circuit 11 and the load of the memory IC 21 depend on the number of memory packages 2 mounted in the memory slots 4N. Changes, and the signal propagation delay time A between the control unit 1 and the memory package 2 also changes.

However, in this embodiment, the dummy packages 3A to 3M are mounted in the memory slots 4A to 4M in which the memory package 2 is not mounted, and the dummy packages 3A to 3M have the same input impedance as the memory package 2. Since they are the same, the load of the control signal drive circuit 11 and the load of the memory IC 21 can be made constant regardless of the number of mounted memory packages 2.

As a result, the load of the control signal drive circuit 11 and the load of the memory IC 21 are always constant,
The signal propagation delay time A between the control unit 1 and the memory package 2 is also constant, so that the timing of the control signal can be optimized, and the signal width of the control signal can be minimized so that the signal width between the control unit 1 and the memory package 2 is reduced. The data transfer can be performed at high speed.

Further, in each of the memory slots 4A to 4N,
Memory package 2 or dummy packages 3A to 3M having the same characteristic impedance as the memory package 2
Is mounted, the load distribution is always constant regardless of the number of mounted memory packages 2, and the signal waveform can be easily optimized.

Therefore, according to the data transmission method of the present embodiment, the dummy packages 3A to 31M to 31M and the dummy packages 3A to 32M are provided in the memory slots 4A to 4M in which the memory package 2 is not mounted.
By implementing 3M, the signal waveform can be optimized,
Moreover, high-speed data transmission between the control unit 1 and the memory package 2 becomes possible.

[0061]

[Embodiment 2] FIG. 2 is a functional block diagram showing a data transmission system in which a dummy load is provided in a control unit according to another embodiment of the present invention.

Similar to the first embodiment, the data transmission system of the present embodiment shows only the functions necessary for reading from the memory package, one memory package is mounted on the data transmission system, and the data transmission path controls the memory package. It is a data transmission system for performing data transfer between parts and differs from the first embodiment in that a dummy load (impedance control means) 7 capable of varying the characteristic impedance is provided in the control part 1a.

That is, in the control section 1a, in addition to the control signal driving circuit 11, the read data receiving circuit 12, the read data receiving timing signal 13 and the timing generating circuit 14, the dummy load 7 capable of setting the characteristic impedance and the timing. A dummy load control signal 15 output from the generation circuit 14a is provided so that the characteristic impedance of the data transmission path viewed from the control unit 1 and the memory package 2 becomes constant regardless of the number of mounted memory packages 2. ing.

The dummy load 7 has capacitors 71A to 71M having the same input impedance as the drive circuit 22 in the memory package, and the same input impedance as when the memory IC 21 stops the data output and opens the output state. The capacitors 73A to 73M, the switches 72A to 72M that determine whether to connect or disconnect the control signal output and the capacitors 71A to 71M, and the data signal input and the capacitors 73A to 73M are connected or disconnected. Switches 74A to 74M that determine whether or not are provided.

Then, the capacitors 71A to 71M, 73
A-73M switches 72A-72M, 74A-74M
One end not connected to is connected to the ground, and the connection / disconnection of the switches 72A to 72M and 74A to 74M is
It is controlled by the dummy load control signal 15.

The capacitors 71A to 71M, 73A
~ 73M and switches 72A-72M, 74A-74
M has a maximum of N memory packages 2 but N
-1 is set because at least one memory package 2 is mounted.

In this embodiment, there are four memory slots.
There are N memory packages A to 4N, and a maximum of N memory packages 2 are mounted. In this case, however, since only one memory package 2 is mounted, compared to the case where N memory packages 2 are mounted. Control signal drive circuit 1 for N-1 sheets
The load of 1 and the load of the memory IC 21 are reduced.

Therefore, by the dummy load control signal 15,
The load of the control signal drive circuit 11 and the load of the memory IC 21 are corrected by setting the N−1 switches 72A to 72M and 74A to 74M in the connected state to obtain the same load as when the N memory packages 2 are mounted.

Similarly, when two memory packages 2 are mounted, the dummy load control signal 15 sets N-2 switches 72A to 72L and 74A to 74L in a connected state, and N memory packages 2 are mounted. If
All the switches 72A to 72M and 74A to 74M are turned off to load the control signal drive circuit 11 and the memory IC 21 regardless of the number of mounted memory packages 2.
The load can be kept constant.

Therefore, according to the data transmission method of this embodiment, the dummy load 7 capable of setting the characteristic impedance by the capacitors 71A to 71M, the capacitors 73A to 73M, the switches 72A to 72M and the switches 74A to 74M is provided in the control unit 1a. Example 1 by being provided
Similarly to the above, the timing of the control signal can be optimized, the signal width of the control signal can be minimized, and the speed of data transfer between the control unit 1 and the memory package 2 can be increased. Since we only need to implement 2,
It is not necessary to remove the dummy package 3 when additionally mounting the memory package 2, unlike the first embodiment.

[0071]

[Third Embodiment] FIG. 3 is a functional block diagram showing a data transmission system in which a dummy load is provided in a dummy package according to a third embodiment of the present invention.

Similar to the first and second embodiments, the data transmission system of the present embodiment shows only the functions necessary for reading from the memory package, one memory package is mounted on the data transmission system, and the memory package is provided by the data transmission path. A data transmission system for performing data transfer between the control unit and the control unit is different. The difference from the second embodiment is that a dummy load (impedance control unit) 7 capable of varying the characteristic impedance is provided in the dummy package 3a instead of the control unit 1a. It is a point.

That is, the dummy load 7 is mounted on the dummy package 3a, and the dummy load 7 has the second embodiment.
71A-71M and 73A
.About.73M, switches 72A to 72M for deciding whether to connect or disconnect between the control signal input of the dummy package 3a and the capacitors 71A to 71M, and between the data signal output of the dummy package 3a and the capacitors 73A to 73M. Switches 74A-7 that determine whether to connect or disconnect
4M is equipped.

In addition to the control signal drive circuit 11, the read data receiving circuit 12 and the read data receiving timing signal 13, the control section 1b has a dummy load control signal 15 in addition to the control signal and the read data receiving timing signal 13. And a dummy load control signal drive circuit 16 for outputting a dummy load control signal 15 for controlling the dummy load 7 in the dummy package 3a. The controller 1 and the memory slot 4A of the dummy package 3a are provided. Are connected through the dummy load control signal connection line 8.

The states of the switches 72A to 72M and 74A to 74M are set by the dummy load control signal 15 at the time of initial setting before operating the memory package 2.

Therefore, according to the data transmission method of this embodiment, the capacitors 71A to 71A are provided in the dummy package 3a.
M, capacitors 73A to 73M, switches 72A to 72
By providing the dummy load 7 capable of setting the characteristic impedance by M and the switches 74A to 74M, the load of the control signal drive circuit 11 and the load of the memory IC 21 can be made constant regardless of the number of mounted memory packages 2. Therefore, similarly to the second embodiment, the control unit 1
The data transfer between the memory package 2 and the memory package 2 can be speeded up, and the required number of memory packages 2 can be mounted when the memory package 2 is additionally mounted.

[0077]

[Fourth Embodiment] FIG. 4 is a functional block diagram showing a data transmission system in which a dummy load is provided in a memory package according to a fourth embodiment of the present invention.

The data transmission method of this embodiment is the same as that of the first embodiment.
Similar to 3, only the functions required for reading from the memory package are shown, a single memory package is mounted on top of this, and the data transmission method is used to transfer data between the memory package and the control unit through a data transmission path. The difference from Examples 2 and 3 is that the control unit 1a and the dummy package 3 are
Instead of a, a dummy load (impedance control means) capable of varying the characteristic impedance of the memory package 2a
7 is the point to be provided.

That is, the memory package 2a is provided with the dummy load 7 capable of setting the characteristic impedance, in addition to the plurality of memory ICs 21 and the memory package drive circuit 22.

The dummy load 7 includes the second and third embodiments.
71A-71M and 73A
˜73M, switches 72A to 72M for deciding whether to connect or disconnect between the control signal input of the memory package 2a and the capacitors 71A to 71M, and the data signal output of the memory package 2a and the capacitors 73A to 73M. Switches 74A-7 that determine whether to connect or disconnect
4M is equipped.

The control section 1b also includes a control signal drive circuit 11, a read data receiving circuit 12, a read data receiving timing signal 13, a control signal, a read data receiving timing signal 13 and a dummy load control signal 1.
5, a timing generation circuit 14a for generating 5 and a dummy load control signal drive circuit 16 for outputting a dummy load control signal 15 for controlling the dummy load 7 in the memory package 2a are provided, and the control section 1b and the memory slot 4N of the memory package 2a are provided. Are connected through the dummy load control signal connection line 8.

In this embodiment, since the number of the memory packages 2a to be mounted is one, the dummy load 7 is one in total, and the N-1 switches 72A to 72M in one dummy load 7 are included. , 74A to 74M are connected. However, when two memory packages 2a are mounted, the dummy load 7 is two in total, so N−2 switches 72A to 72L, 7 in the two dummy loads 7 are included.
4A to 74L are brought into the connected state.

At this time, it is better to disperse the switches 72A and 74A of one dummy load 7 among the two dummy loads 7 on the average of the two dummy loads 7 rather than connecting them. Good. Similarly, when three or more memory packages 2a are mounted, each memory package 2a
It is better to disperse the dummy loads 7 in the average load.

This is because when the maximum number of memory packages 2a are mounted, the memory packages 2a are mounted in all the memory slots 4A to 4N, and the load is distributed evenly, so that the dummy loads 7 are distributed to a plurality of dummy loads 7. The reason for this is that if the load is distributed evenly, the load condition at this time can be approached.

Therefore, according to the data transmission method of this embodiment, the capacitors 71A to 71A are provided in the memory package 2a.
M, capacitors 73A to 73M, switches 72A to 72
By providing the dummy load 7 capable of setting the characteristic impedance by M and the switches 74A to 74M, the load of the control signal drive circuit 11 and the load of the memory IC 21 can be made constant regardless of the number of mounted memory packages 2a. Therefore, it is possible to speed up the data transfer between the control unit 1b and the memory package 2a as in the second and third embodiments, and when the additional mounting of the memory package 2a is performed, the required number of the memory packages 2a can be mounted. It will be possible.

Although the invention made by the present inventor has been specifically described based on the first to fourth embodiments, the present invention is not limited to the above-mentioned embodiments and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the data transmission method of each of the above embodiments, the capacitor 71A used for the dummy load 7 is used.
.About.71M and 73A to 73M having fixed capacities have been described, the present invention is not limited to the above-described embodiment, and is widely applicable to the case of using other parts.

That is, the capacitors 71A to 71M, 7
As 3A to 73M, it is also possible to use a capacitor whose electrostatic capacity changes depending on the applied voltage. In this case, since the electrostatic capacity changes depending on the applied voltage, no switch is required, and the number of components can be reduced. Become.

Further, in each of the above-described embodiments, only the functions necessary for reading from the memory packages 2 and 2a are shown for simplification of description, and the description is given assuming that one memory package 2 and 2a is mainly mounted. However, it goes without saying that the memory package can be provided with a writing function and the number of memory packages can be variously changed.

In the above description, the case where the invention made by the present inventor is mainly applied to a data transmission system for transferring data between the memory packages 2 and 2a and the control units 1, 1a and 1b, which is the field of use thereof, will be described. However, the present invention is not limited to this, and is widely applicable to data transfer between a plurality of control units each having a control function.

[0091]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). An impedance control means is provided to make the characteristic impedance of the data transmission path viewed from each of the plurality of control units mounted in the plurality of slots always constant regardless of the number of mounted control units. Due to the mounting of the impedance control means, the load of the control unit is always constant regardless of the number of mounted units.
The signal waveform can be optimized, and the signal transmission delay time between the control units can be made constant to speed up data transmission.

(2). When a plurality of control units are mounted in a control section and a plurality of memory slots to form a single or a plurality of memory packages and data transfer between the memory packages and the control sections is performed, the control section and the memory are Since the characteristic impedance of the data transmission path seen from each package can be kept constant regardless of the number of mounted memory packages, the signal width of the control signal for controlling the memory package should be minimized and the control unit and the memory It is possible to speed up data transmission between packages.

(3) As an impedance control means, a dummy package that can be mounted in the memory slot and has the same characteristic impedance as the memory package is provided, and this dummy package is mounted in the unmounted slot of the memory package, Since the characteristic impedance of the data transmission path seen from the control unit and the memory package can be made constant as in 2), the speed of data transmission between the control unit and the memory package can be increased.

(4) As the impedance control means, a dummy package capable of varying the characteristic impedance is provided in the control unit, a dummy package mountable in the memory slot, or a dummy load capable of varying the characteristic impedance, and the dummy load is controlled to set the characteristic impedance. By doing so, the data transmission between the control unit and the memory package can be performed at high speed as in the above (2), and the required number of additional memory packages can be easily mounted.

(5) Due to the above (1) to (4), the characteristic impedance seen from the control section and the memory package can always be made constant regardless of the number of memory packages to be mounted. The constant signal propagation delay time makes it possible to speed up data transmission, and in particular, it is possible to obtain a good data transmission method for data transmission using a memory IC having a high-speed read mode.

(6) According to the above (1) to (4), in order to speed up the data transmission, it is realized by the configuration of a dummy load circuit such as a capacitor and a plurality of switches for connecting or disconnecting the dummy load circuit. Therefore, it is possible to obtain a data transmission method that can minimize cost increase.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a data transmission system using a dummy package which is Embodiment 1 of the present invention.

FIG. 2 is a functional block diagram showing a data transmission system in which a dummy load is provided in a control unit that is Embodiment 2 of the present invention.

FIG. 3 is a functional block diagram showing a data transmission system in which a dummy load is provided in a dummy package which is Embodiment 3 of the present invention.

FIG. 4 is a functional block diagram showing a data transmission system in which a dummy load is provided in a memory package which is Embodiment 4 of the present invention.

FIG. 5 is a timing chart when reading data from a memory package in a data transmission method as an example of a conventional technique.

[Explanation of symbols]

1, 1a, 1b Control unit 2, 2a Memory package 3, 3a Dummy package (impedance control means) 3A to 3M Dummy package (impedance control means) 4A to 4N Memory slot 5 Control signal connection line 6 Data signal connection line 7 Dummy load (Impedance control means) 8 dummy load control signal connection line 11 control signal drive circuit 12 read data reception circuit 13 read data reception timing signal 14, 14a timing generation circuit 15 dummy load control signal 16 dummy load control signal drive circuit 21 memory IC 22 Drive circuit in memory package 31A-31M capacitor 32A-32M capacitor 71A-71M capacitor 72A-72M switch 73A-73M capacitor 74A-74M switch

Claims (7)

[Claims] 1. A plurality of control units and a plurality of slots, wherein the plurality of control units are respectively mounted in the plurality of slots, and the plurality of slots are connected by a data transmission line commonly connected to the plurality of slots. A data transmission method for performing data transfer between control units, wherein the characteristic impedance of the data transmission line viewed from each of the plurality of control units is always constant regardless of the number of mounted control units. A data transmission method comprising impedance control means. 2. The plurality of control units and the plurality of slots are used as a control unit and a plurality of memory slots, and the control units and the plurality of memory slots are mounted in the plurality of memory slots by a data transmission line commonly connected to each other. In the case of performing data transfer between the single or plural memory packages and the control unit, the characteristic impedance of the data transmission path viewed from each of the control unit and the memory package is set regardless of the number of mounted memory packages. The data transmission method according to claim 1, wherein the data transmission method is always constant. 3. As the impedance control means, a dummy package that can be mounted in the memory slot and has the same characteristic impedance as the memory package is provided, and the dummy package is mounted in a memory slot in which the memory package is not mounted. The data transmission method according to claim 2, wherein 4. As the impedance control means, a dummy load capable of varying the characteristic impedance is provided in the control unit, the dummy load is controlled to set the characteristic impedance, and the dummy load is set regardless of the number of mounted memory packages. 3. The data transmission method according to claim 2, wherein the characteristic impedance of the data transmission line viewed from the control unit and the memory package is always constant. 5. As the impedance control means, a dummy package having a dummy load mountable in the memory slot and capable of varying the characteristic impedance is provided, and only one dummy package is provided in the memory slot in which the memory package is not mounted. Mounting means, and providing control means for controlling the dummy package from the control section,
The dummy impedance is controlled by the control unit to set its characteristic impedance so that the characteristic impedance of the data transmission line viewed from the control unit and the memory package is always constant regardless of the number of mounted memory packages. The data transmission method according to claim 2, wherein 6. As the impedance control means, a dummy load capable of varying a characteristic impedance is provided in the memory package, and control means for controlling the dummy load is provided from the control section, and the dummy load is provided from the control section. 3. The characteristic impedance is controlled to set the characteristic impedance so that the characteristic impedance of the data transmission line viewed from the control unit and the memory package is always constant regardless of the number of mounted memory packages. Data transmission method described. 7. A dummy load circuit having the same characteristic impedance as the memory package, wherein the dummy load is a dummy load circuit.
7. The data transmission method according to claim 4, wherein the dummy load circuit is composed of a plurality of switches for connecting or disconnecting, and the characteristic impedance is changed by connecting or disconnecting each of the plurality of switches. .