JPH061602B2 - PCM recording and reproducing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a PCM recording / reproducing apparatus which gives an optimum frame number of bits to a plurality of kinds of quantization bits.

[Prior Art] An analog signal is sampled at a sampling frequency Fs, subjected to A / D conversion to be converted into PCM data, and a plurality of PCM data are collectively formed into a frame structure and distributed to a plurality of tracks for recording and reproduction. A PCM recorder or the like is an example of a device that does this.
The frame / block configuration of these PCM recording devices is shown in FIG. In the figure, (a) shows a frame structure and (b) shows a block structure. One frame is composed of 252 bits, and 14 samples of PCM data having a quantization bit number of 16 are collected, and are composed of 10 bits of synchronizing signal, 2 bits of control signal, and 16 bits of C1 check data for error detection and correction. (b) shows a block structure, in which a frame-structured signal is recorded in a total of 8 tracks of 6 tracks for PCM data and 2 tracks for error detection and correction. The frame structure of FIG. 3 is determined as follows.
Now, the number of channels of an analog signal is N, the number of samples constituting one frame is S, and the number of tracks for recording PCM data is
If Tr, the frame and block frequency F _B is given by the following equation.

When the number of bits in one frame is T _S , T _S = B × S + m (4) Where B is the number of quantization bits in one sample, m
Is the number of additional bits such as a synchronization signal. The transmission frequency F _C of the bit in the frame is given by F _C = F _B × T _S (5) At this time, since F _C and F _S × N can be generated from one clock if F _C and F _S × N have a simple integer ratio, S and m are selected so as to be possible. In the case of FIG. 3, since N = 2, S = 14, and Tr = 6, the block frequency F _B is F _S at 48 kHz, Is. Since the sync signal is 10 bits, the control signal is 2 bits, and the C1 inspection data is 16 bits, m = 10 + 2 + 16 = 2
Since 8 and B = 16, T _S = 16 × 14 + 28 = 25 from equation (4).
2 bits. Therefore, from equation (5), F _C = 252 × 1.143kHz = 2
It becomes 88kHz, and the ratio of F _C to F _C × N is 288: 48 × 2 = 3: 1, which is a simple integer ratio. Such a clock can be generated by the clock generation circuit shown in FIG. In the figure, (1) is the master clock oscillator, (2) is the 6 divider,
(3) is a 42 frequency divider, (4) is a 252 counter, and (5) (6) (7) (8) are output terminals. Generates 288kHz by the master clock oscillator (1), divides by 6 circuit (2), 252 counter (4) and output terminal
Sent to (6). The output of the divide-by-6 circuit (2) is 48kHz and 42
It is sent to the frequency dividing circuit (3) and the output terminal (8). 252 counter
At (4), the clock necessary for generating the sync signal and the control signal is output to the output terminal (5). (42) The block frequency F _B is output from the frequency divider to the output terminal (8).

A block diagram of a PCM recording / reproducing apparatus having such a frame structure is shown in FIG. In the figure, (9) is a 2-channel analog signal input terminal, (10) is an A / D conversion circuit,
(11) is an encoding circuit, (12) is a track distribution circuit, (13) (14)
(15) is a modulation circuit, (16) (17) (18) is a recording amplifier, (19) (20)
(21) is the recording head, (22) (23) (24) is the playback head, and (25) (2).
6) (27) is a reproduction amplifier, (28) (29) (30) is a demodulation circuit, (31) (3
2) (33) is a time axis correction circuit (hereinafter abbreviated as TBC circuit), (3
4) is the decoding circuit, (35) is the digital analog conversion circuit,
(36) is a channel analog output terminal, and (37) is a clock generation circuit. Next, the operation will be described. First, on the recording side, the analog signal input from the input terminal (9) is
The D conversion circuit (10) converts the data into PCM data with the quantization bit number B = 16, and the encoding circuit (11) corrects and detects an error due to a medium such as a tape. An error correction detection code is added. A control signal is added to the encoded signal by the track distribution circuit (12), and the coded signal is distributed to eight tracks to be modulated by the modulation circuits (13) (14) (1).
Sent to 5). The modulation circuit (13) (14) (15) modulates to a signal suitable for recording and reproducing on the medium, and then a sync signal is added to the recording amplifier (16) (17) (18) from the recording head ( 19) (20)
It is recorded on the medium through (21). On the playback side, the playback head
The signals reproduced by (22) (23) (24) are reproduced by amplifiers (25) (26) (2
The signal is amplified in 7) and the demodulation circuit (28) (29) (30) detects and protects the sync signal, and the clock is reproduced, and the clock and the data separated from the sync signal are transferred to the TBC circuit (31) (32). Send to (33). The TBC circuits (31), (32) and (33) remove the jitter data from the reproduced data and send it to the decoding circuit (34). The decoding circuit (34) carries out error correction detection based on the C1 check data and the C2 check data, converts it into an original analog signal by the D / A conversion circuit (35) and outputs it from the output terminal (36). The control signal is used to control the device such as the presence or absence of F _S type emphasis. The clock generation circuit (37) is mainly constructed based on Fig. 4,
F _S is _supplied to the A / D converter (10) and D / A converter (35), and the outputs of F _C , F _B and the output terminal (5) are the track distribution circuit (12), the modulation circuit (13) and (14). ) (15) and TBC circuits (31) (32) (33).

Since the conventional frame configuration is configured as above,
If we try to correspond to the _second number of quantization bits B ₂ = 20,
The frame / block configuration of FIG. 6 is possible. Since only the number of quantization bits is changed from Fig. 3, T from Eq. (4)
_S = 20 x 14 + 28 = 308, from equation (5), F _C = 1.143kHz x 308 = 35
It becomes 2kHz. As described above, when the number of bits in one frame is 16 and the number of quantization bits is 16, the length is different from that of 252 and the number of quantization bits 308. The main part of the clock generation circuit corresponding to these two quantization bit numbers is given in FIG. In the figure, (38) is a 3.168 MHz master clock oscillator,
(39) is 11 divider, (40) is 66 divider, (41) is 9 divider, (4
2) is a 252 counter, (43) is a 42 frequency divider, (44) is a 308 counter, and (45) (46) (47) (48) (49) (50) are output terminals. When the number of quantization bits is 16, the signal from the output terminal (45) (46) (47) (48) is used, and when the number of quantization bits is 20, the output terminal (47) (48)
The signals of (49) and (50) are used.

[Problems to be solved by the invention]

Since the frame structure of the conventional PCM recording / reproducing apparatus is structured as described above, it has the following drawbacks. First, as you can see in Fig. 4 and Fig. 7, the frequency of the master clock is 11 times higher from 288kHz to 3.168MHz.
Since the CM recording / reproducing apparatus uses various clocks for encoding or the like, it has a drawback that the degree of freedom in selection is reduced and it is difficult to use. Next, the signals at the output terminals (45) and (50) are sent to the track distribution circuit (12) and the TBC circuits (31), (32) and (33), and these circuits normally use memory. Therefore, if the number of bits in one frame is different, the control becomes complicated. Further, if the number of bits in one frame is different, the synchronization signal protection circuit in the demodulation circuit (28) (29) (30) does not work, and each track is sent to the TBC circuit (31) (32) (33). There were some drawbacks such as complicated hardware because the clocks had to be switched.

The present invention has been made in order to solve the above problems, and the number of frame bits is the same for two or more quantization bits, the master clock does not become high, and the track distribution circuit (12) , Modulation circuit (13) (14) (15), Demodulation circuit (2
It is an object of the present invention to obtain a PCM recording / reproducing device in which the 8) (29) (30) and the TCB circuits (31) (32) (33) can be easily constructed.

[Means for solving problems]

The PCM recording and reproducing apparatus according to this generation uses the equations (1) and (2) so that the number of frame bits is the same for two or more quantization bits, and the number of samples S in one frame and the number of frame bits are set. The number T _A is set and the recording and reproducing are performed.

[Action]

In the frame structure according to the present invention, one frame is composed of an integer multiple of the least common multiple of two or more quantization bits and an additional bit such as a synchronizing signal, and the number of channels N, the number of samples S in one frame, and the number of tracks. The product of Tr and the number of bits in one frame are determined to be a simple integer ratio.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, (a) is a frame structure and (b) is a block structure. The synchronization signal is 16 bits, the control signal is 8 bits, and P is
CM data or inspection data 320 data, C1 inspection data 1
A total of 6 bits, 360 bits. This frame structure is determined as follows. Number of channels N = 2, PCM
Number of data distribution tracks Tr = 6, two kinds of quantization bits
If B ₁ = 16 and B ₂ = 20, then LCM (B ₁ ,
B ₂ ) = 80. 80 bits / 16 bits = 5, but 2
Since even numbers are desirable in the case of channels, Tables 1 and 2 show the results obtained by calculating equations (1) and (2) with 80 × 2 = 160 bits and collecting TA and TB with a simple ratio. Table 1 shows the case where the number of quantization bits B ₁ = 16 bits, and Table 2 shows the case where the number of quantization bits B ₂ = 20.

Here, P: Q represents the ratio of TA to TB, where Q is 10
The following are listed. F _M is the master clock frequency. Since m contains a synchronizing signal, a control signal, and C1 inspection data, an even number between 24 and 48 bits is given. In Tables 1 and 2, those with the same number of bits for T _A are selected, and the one with T _A = 360 bits has the frame / block configuration of FIG.

The main part of the clock generation circuit for realizing this frame / block structure can be realized by FIG. In FIG. 2, (51) is a master clock oscillator, (52) is a frequency divider by 5,
(53) is a 30 divider, (54) is a 4 divider, (55) is a 60 divider, (5
6) is a 48 divider, (57) is a switch, (58) is a 360 counter, (5
9) (60) (61) (62) (63) (64) are output terminals.

As can be seen from Table 1 and Table 2, the master clock oscillator
At (51), 1.44 MHz is generated and sent to the frequency dividing circuit (52), the frequency dividing circuit (53), the frequency dividing circuit (53), and the frequency dividing circuit (54). The output of the divide-by-5 circuit (52) is the bit frequency F corresponding to the number of quantization bits B ₁ = 16.
_It becomes _C1 = 288kHz and is sent to the output terminal (59). Divide-by-4 circuit
The output of (54) has a bit frequency F _C2 = 360 kHz corresponding to the quantization bit number B ₂ = 20 and is sent to the output terminal (63). The output of the 30 frequency divider (53) is F _S = 48 kHz and is sent to the 60 frequency divider circuit (55), the 48 frequency divider circuit (56), and the output terminal (61). 60 frequency divider (5
5) The outputs F _B1 = 0.8 kHz and F _B2 = 1 kHz of the 48 divider circuit (56) are sent to the output terminals (60) and (62), respectively. The switching device (57) selects the output of the frequency divider (52) when the number of quantization bits B ₁ = 16 and the output of the frequency divider (54) when the number of quantization bits B ₂ = 20. Switch.

In the above embodiment, the number of channels N = 2 and the number of tracks Tr
Although the case of = 6 has been described, it is clear that the number of frame bits can be determined from the equations (1) and (2) with other channel numbers and track numbers. In the above embodiment, the case where the number of quantization bits is R = 2 (B ₁ = 16, B ₂ = 20) is shown.
It goes without saying that the equations (1) and (2) are valid even in the case of more than this.

Furthermore, in the above embodiment, an example of a multi-track recording / reproducing apparatus with Tr = 6 is shown, but with one transmission line, track 1, track 2, ..., Track 6, track 7, track 8, track 1 ... It is also applicable when performing sequential recording and reproduction.

〔The invention's effect〕

As described above, according to the present invention, since the number of frame bits can be made equal to the number of quantization bits of two or more, the hardware of the recording / reproducing apparatus becomes simple and the frequency of the master clock becomes low. effective.

[Brief description of drawings]

FIG. 1 is a diagram showing a frame / block structure according to one embodiment of the present invention, FIG. 2 is a block diagram of a clock generation circuit according to one embodiment of the present invention, and FIG. 3 is a block diagram of a conventional quantization bit number 16. Figure showing the frame / block configuration in the case,
FIG. 4 is a block diagram of a conventional clock generation circuit, and FIG. 5 is a block diagram of a multi-track PCM recording / reproducing device.
FIG. 6 shows a frame / frame when the conventional quantization bit number is 20.
FIG. 7 is a block diagram of a block generating circuit for realizing the frame / block configuration of FIGS. 3 and 6 showing the block configuration. In the figure, (51) is a master clock oscillator and (52) is 5
Frequency divider, (53) 30 frequency divider, (54) 4 frequency divider, (55) 60 frequency divider, (56) 48 frequency divider, (57) switch, (58) Is a 360 counter. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. An N-channel (N: integer) analog signal is analog-digital converted at a sampling frequency Fs (hereinafter referred to as A).
/ D conversion) to convert it into PCM data, and combine several PCM data into a frame structure.
In a PCM recording and reproducing apparatus that records and reproduces data by distributing it to Tr (Tr: integer) tracks, when the number of k quantization bits is Bi (i = 1, ..., K), the following equation is used. A PCM recording / reproducing apparatus characterized in that a given ratio of TA and TB is expressed by a simple integer ratio, and the same TA is recorded as the number of bits of one frame in each number of quantization bits. TA = n × LCM (Bi (i = 1, ... k)) + m… (1) TB ＝ N × S × Tr… (2) where n: integer m: number of additional bits such as sync signal LCM ( Bi (i = 1, ..., k): Least common multiple of Bi (i = 1, ..., k) S: Number of samples constituting one frame 2. A PCM recording and reproducing apparatus according to claim 1, wherein k = 2, B1 = 16 and B2 = 20. 3. N = 2, Tr = 6, k = 2, B1 = 16, B2 = 20,
The PCM according to claim 1, wherein n = 4 and m = 40 and the number of bits in one frame is 360 bits.
Recording and playback device.