JPH06153187A - Video telephone set - Google Patents

Abstract

PURPOSE:To provide the video telephone set easily reproducing a picture received before with simple circuit configuration without separately providing of a picture recording device or the like. CONSTITUTION:A video decoding circuit 7 and an inverse format conversion circuit 8 convert a coded signal inputted from a line side into a digital video signal. A D/A converter circuit 9 converts a digital video signal into an analog video signal. Then a picture storage circuit 1 has a memory capacity able to store the digital video signal outputted by the inverse format conversion circuit 8 and usually the digital video signal outputted by the inverse format conversion circuit 8 is outputted to the D/A converter circuit 9 as it is, and when a storage command is given, the digital video signal is stored in the memory. Furthermore, when a read command is given, the digital video signal stored in the memory is outputted to the D/A converter circuit 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a videophone device which provides a face-to-face communication environment using video signals and audio signals.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the structure of a conventional videophone device. In the figure, 2 is a person or landscape,
A camera 3 for picking up a document or the like and outputting an analog video signal 21 thereof, an A / D converter circuit 3 for converting the analog video signal 21 into a digital video signal 31, and a converter 4 for converting the digital video signal 31 into a non-interlaced signal 41. A format conversion circuit, 5 is a video coding circuit for coding the non-interlaced signal 41, and 6 is a demultiplexing circuit for multiplexing the coded signal 51 output from the video coding circuit 5 with an audio signal and other data signals. Is.

The demultiplexing circuit 6 also performs a demultiplexing process on the received signal. Reference numeral 7 is a video decoding circuit for decoding the encoded signal 71 separated by the demultiplexing circuit 6, and 8 is a non-interlaced signal 81 output from the video decoding circuit 7 and a digital video signal 91.
An inverse format conversion circuit 9 for converting the digital video signal 91 into an analog video signal 101
The -A conversion circuit 10 is a camera that performs display according to the analog video signal 101.

Next, the operation will be described. The analog video signal 21 output from the camera 2 is input to the A / D conversion circuit 3. Here, the analog video signal 21 is NTSC.
(National Television System Committee) method, PA
L (Phase Alternation Line) system, SECAM (Sequ
Priority Couleur A Memoire) signal format. The A / D conversion circuit 3 converts the analog video signal 21 into a digital video signal 31. The digital video signal 31 is also a digital signal of a signal format based on the NTSC system, the PAL system, the SECAM system, or the like.

The format conversion circuit 4 uses the CCITT
(International Telegraph and Telephone Advisory Committee) In order to use the video encoding circuit 5 for encoding in accordance with the international standardization recommendation, the input digital video signal 31 is a non-interlaced signal of 352 pixels × 288 lines in common. The signal is converted into a signal 41 in an intermediate format (Comm Intermediate Format, hereinafter referred to as CIF) or a signal format of QCIF (Quarter CIF) which is a non-interlaced signal of 176 pixels × 144 lines.

This non-interlaced signal 41 is a CCI.
TT Recommendation H. The encoded signal 51 is encoded by the video encoding unit 5 that performs encoding according to the high-efficiency encoding method defined by H.261. The demultiplexing circuit 6 sends the coded signal 51, the digitized voice signal and the like to CCITT Recommendation H.264. Two
The frame structure defined in No. 21 is multiplexed. The multiplexed signal is ISDN (Integrated Service Digital Network)
Etc. are sent to the partner device via a circuit switched network or a dedicated line such as a high-speed digital line.

On the other hand, when receiving the multiplexed signal from the partner device, the demultiplexing circuit 6 separates the multiplexed signal into a voice signal and the like and a coded signal 71. Separated coded signal 7
1 is CCITT Recommendation H.264. The non-interlaced signal 81 in the CIF or QCIF signal format is decoded by the video decoding circuit 7 that performs decoding according to the high-efficiency coding method defined by H.261. The inverse format converter 8 sends the non-interlaced signal 81 to the NTSC system, the PAL system,
It is converted into a digital video signal 91 in a signal format based on the SECAM method or the like.

Next, the D-A conversion circuit 9 outputs the digital video signal 91 to the NTSC system, the PAL system, and the SECAM.
It is converted into an analog video signal 101 in a signal format according to the method. Then, the monitor 10 reproduces an image of a person, a landscape, a calligraphy, or the like captured by the partner device on the screen according to the analog video signal 101 given from the D-A conversion circuit 9.

[0009]

Since the conventional videophone device is configured as described above, the received moving image is transient. Therefore, even if the operator wants to see the image received previously, the image cannot be reproduced. If an image recording device such as a VTR is provided and the analog video signal 101 is recorded therein, such a request can be answered. However, if an image recording device or the like is provided, the videophone device becomes large and expensive.

Accordingly, it is an object of the present invention to provide a videophone device which can easily reproduce a previously received image with a simple circuit configuration without providing an image recording device or the like.

[0011]

According to a first aspect of the present invention, there is provided a video telephone device, which includes an AD conversion circuit for converting an analog video signal to be sent to a partner device into a digital video signal, and a received digital video signal. And a D-A conversion circuit for converting a digital video signal into an analog video signal for transmitting and receiving a digitalized video signal of a predetermined format, and capable of accumulating a digital video signal input to the D-A conversion circuit. The image storage circuit has a memory and outputs a digital video signal stored in the memory to a D-A conversion circuit.

According to the second aspect of the present invention, a videophone device includes an AD conversion circuit for converting an analog video signal to be sent to a partner device into a digital video signal, and the received digital video signal as an analog video signal. A D-A conversion circuit for converting into a digital format and transmitting and receiving a digitized video signal of a predetermined format.
An image having a memory capable of accumulating a digital video signal input to the A conversion circuit and a digital video signal output from the AD conversion circuit, and outputting the digital video signal accumulated in the memory to the DA conversion circuit It is provided with a storage circuit.

[0013]

The image storage circuit according to the invention of claim 1 is
The image from the other side is stored locally at any point during the call, and at any subsequent point the operator desires,
Allows you to play the image.

The image storage circuit according to the first aspect of the present invention locally stores the image and the transmission image from the other party at any time during the call, and the image at any time thereafter desired by the operator. To be able to play.

[0015]

1 is a block diagram showing the configuration of a video telephone apparatus according to an embodiment of the present invention. As shown in the figure,
In this case, the digital video signal 91 output from the inverse format converter 8 is once input to the image storage circuit 1. Then, the D-A conversion circuit 9 is supplied with the digital video signal 91 from the image storage circuit 1. The rest of the configuration is similar to that shown in FIG.

FIG. 2 is a block diagram showing an example of the configuration of the image storage circuit. As shown in the figure, in the image storage circuit 1A, the digital video signal 91A from the inverse format conversion unit 8 is branched into two and input to the switch 111 and the selector 112. The other side of the switch 111 is connected to the memory 113, and the memory 113 is also connected to the other side of the selector 112.

Normally, the accumulation / reproduction control circuit 114 gives a switch on / off signal S11 indicating an off command to the switch 111 so as to select the digital video signal 91A from the inverse format converter 8 (in FIG. 2). select signal S13 to selector 112 so that a is selected)
Is giving. Therefore, the digital video signal 91A output from the inverse format converter 8 is converted into the DA converter 9
Is converted into an analog video signal 101 and sent to the monitor 10.

Upon receiving the operation signal S14 instructing the storage from the host system or the like, the storage / reproduction control circuit 114 synchronizes with the frame pulse output from the inverse format conversion section 8 and switches on / off the switch which indicates an on command. Signal S1
1 is supplied to the switch 111, and the switch 111 is set to the conductive state for one frame period or a predetermined period. Further, the read / write signal S12 instructing the write state is given to the memory 113 to set the memory 113 in the write state. At this time, the select signal S13 is set to select a.

As a result, the digital video signal 91A is
The data is sent to the D / A conversion circuit 9 and written in the memory 113 in synchronization with the memory driving clock that is also the clock for the inverse format conversion unit 8. When the operation signal S14 instructing storage is input again, the memory 113 is written from the address next to the address where the digital video signal 91A was stored last.

When receiving the operation signal S14 for instructing reproduction from the host system or the like, the storage / reproduction control circuit 114 selects the output of the memory 113 in synchronization with the frame pulse output from the inverse format conversion section 8. To (Fig. 2
The select signal S13 is given to the selector 112 so as to select b in the above). Further, the read / write signal S12 instructing the read state is given to the memory 113 to set the memory 113 in the read state. As a result, the digital video signal 91B read from the memory 113 in synchronization with the memory driving clock is D
It is sent to the -A conversion circuit 9. And the video signal is D
Is converted into an analog video signal 101 by the -A conversion circuit 9,
It is sent to the monitor 10.

As described above, the operator can store the required image and reproduce the image at an arbitrary time through the host system or the like. Here, it is also conceivable that an image storage circuit is provided between the video decoding circuit 7 and the inverse format conversion unit 8 to store the non-interlaced signal 81 output from the video decoding circuit 7. But CCI
TT Recommendation H. The signal decoded according to H.261 is CIF.
Alternatively, it is a QCIF signal. Therefore, when accumulating and reproducing the signal, it is recognized which one of them, and a control signal required for switching control and timing control between the image storage circuit and the inverse format conversion unit 8. Must be transmitted and received, and the circuit configuration becomes complicated.

FIG. 3 is a block diagram showing another configuration example of the image storage circuit. As shown in the figure, the image storage circuit 1B
In, the digital video signal 91A from the inverse format conversion unit 8 is branched into two and input to the switch 121 and the selector 122. The other side of the switch 121 is connected to the memories 123 to 125.
To 125 are also connected to the other side of the selector 122. In this case, the # 1 memory 123 to the #n memory 125
N memories are frame memories or field memories.

In the normal state, similarly to the one shown in FIG. 2, the accumulation / reproduction control circuit 126 gives a switch on / off signal S21 indicating an off command to the switch 121 and selects the selector 122 to select a. The signal S23 is given. Therefore, the digital video signal 91A output from the inverse format conversion unit 8 is converted into the analog video signal 101 by the DA conversion circuit 9 and sent to the monitor 10.

In this case, the memory selection instruction signal S25 is given from the host system or the like together with the operation signal S24 for instructing storage or reproduction. For example, when receiving the memory selection instruction signal S25 for selecting the # 1 memory 123 and the operation signal S24 for instructing the accumulation, the accumulation / reproduction control circuit 125 synchronizes with the frame pulse output from the inverse format conversion unit 8, A switch on / off signal S21 indicating an on command is given to the switch 121, and the switch 121 is set to the conductive state for one frame period or a predetermined period. Further, the read / write signal S22 for setting only the # 1 memory 123 to the write state is set to the # 1 memories 123 to #n.
It is given to the memory 125, the # 1 memory 123 is set to the write state, and the # 2 memory 124 to #n memory 1
25 is set to the write-protected state. At this time, the select signal S13 is set to select a.

As a result, the digital video signal 91A is
While being sent to the D-A conversion circuit 9, it is written in the # 1 memory 123 in synchronization with the memory driving clock. Further, the contents of the # 2 memory 124 to #n memory 125 are protected.

When receiving the memory selection instruction signal S25 for selecting the # 1 memory 123 and the operation signal S24 for instructing reproduction from the host system or the like, the storage / reproduction control circuit 126
Gives a select signal S23 to the selector 122 so as to select b in synchronization with the frame pulse output from the inverse format converter 8. Also, the # 1 memory 123
Only the read / write signal S12 that sets only the read state is set, and only the # 1 memory 123 is set to the read state.
The # 2 memory 124 to the #n memory 125 are set to the read prohibited state. As a result, the digital video signal 91B read from the # 1 memory 123 in synchronization with the memory driving clock is transferred to the DA conversion circuit 9 via the selector 122.
Sent to. Then, the video signal is converted into the D-A conversion circuit 9
Is converted into an analog video signal 101 and sent to the monitor 10.

FIG. 4 is a block diagram showing the structure of a videophone device according to another embodiment of the present invention. As shown in the figure, in this case, the digital video signal 91 output from the inverse format conversion unit 8 is temporarily stored in the image storage circuit 1.
Enter 1. Then, the D-A conversion circuit 9 is supplied with the digital video signal 91 from the image storage circuit 11.
Further, the digital video signal 31 output from the A-D conversion circuit 3 is branched into two and is input to the format conversion circuit 4 and also to the image storage circuit 11.

FIG. 5 is a block diagram showing an example of the configuration of the image storage circuit. As shown in the figure, in the image storage circuit 11, the digital video signal 91A from the inverse format conversion unit 8 is branched into two and input to the switch 131 and the selector 132. Then, the digital video signal 31 output from the A / D conversion circuit 3 is also input to the switch 131. The other side of the switch 131 is connected to the memory 133, and the memory 133 is also connected to the other side of the selector 132. Therefore, in this case, the switch 131 supplies one of the digital video signal 91A and the digital video signal 31 to the memory 133.

In the normal state, the accumulation / reproduction control circuit 134 gives a switch on / off signal S31 indicating an off command to the switch 131, and gives a select signal S33 to the selector 132 so as to select a. Therefore, the digital video signal 91A output from the inverse format conversion unit 8 is directly applied to the DA conversion circuit 9, converted into the analog video signal 101 by the DA conversion circuit 9, and sent to the monitor 10.

When receiving the operation signal S34 instructing the accumulation of the transmission signal from the host system or the like, the accumulation / reproduction control circuit 1
The switch 34 applies a switch ON / OFF signal S31 indicating an ON command to the switch 131 in synchronization with the frame pulse output from the inverse format converter 8, and the switch 131
The side connected to the output of the A-D conversion circuit 3 and the side connected to the memory 133 are set to the conductive state for one frame period or a predetermined period. Further, the read / write signal S32 instructing the write state is given to the memory 133, and the memory 133 is set to the write state. At this time, the select signal S33 is set to select a.

As a result, the digital video signal 91A becomes D
The digital video signal 31 output from the AD conversion circuit 3 is written to the memory 133 while being sent to the -A conversion circuit 9 and in synchronization with the memory driving clock.

When receiving the operation signal S34 for instructing the accumulation of the received signal from the host system or the like, the accumulation / reproduction control circuit 134 issues an ON command in synchronization with the frame pulse output from the inverse format converter 8. The switch on / off signal S31 shown in the figure is given to the switch 131, and the side connected to the output of the DA conversion circuit 9 of the switch 131 and the side connected to the memory 133 are conducted for one frame period or a predetermined period. Set to state. Further, the read / write signal S32 for instructing the write state is sent to the memory 133.
Then, the memory 133 is set to the write state. At this time, the select signal S33 is set to select a.

As a result, the digital video signal 91A is
The data is sent to the D-A conversion circuit 9 and written in the memory 133 in synchronization with the memory driving clock. In addition,
Operation signal S3 for instructing accumulation of transmission signal or reception signal
When 4 is input again, the memory 133 is written from the address next to the address at which the digital video signal 31 or the digital video signal 91A is finally stored.

When receiving the operation signal S34 for instructing reproduction from the host system or the like, the storage / reproduction control circuit 134 synchronizes with the frame pulse output from the inverse format conversion unit 8 and selects the selector b. To the select signal S33. Further, the read / write signal S32 instructing the read state is given to the memory 133 to set the memory 133 in the read state. As a result, the digital video signal 91B read from the memory 133 in synchronization with the memory driving clock is D
It is sent to the -A conversion circuit 9. And the video signal is D
Is converted into an analog video signal 101 by the -A conversion circuit 9,
It is sent to the monitor 10.

As described above, the operator can store the required received image and reproduce the image at an arbitrary time through the host system and store the required transmitted image. And that image can be reproduced at any time.

[0036]

As described above, according to the present invention, since the videophone device has a configuration having an image storage circuit for storing an image of a digital video signal, an image recording device such as a VTR is not required, Further, there is an effect that a transmitted image or a received image can be stored during communication without changing the communication state, and that the image can be reproduced at any time thereafter. That is, it is possible to selectively accumulate necessary images from the moving image information that is originally a transitory character, and reproduce the images at any time during communication or standby and confirm the contents. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a videophone device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an image storage circuit.

FIG. 3 is a block diagram showing another configuration example of an image storage circuit.

FIG. 4 is a block diagram showing a configuration of a videophone device according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of an image storage circuit.

FIG. 6 is a block diagram showing a configuration of a conventional videophone device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 image storage circuit 2 camera 3 A-D conversion circuit 4 format conversion circuit 5 video encoding circuit 6 demultiplexing circuit 7 video decoding circuit 8 inverse format conversion circuit 9 DA conversion circuit 10 camera 11 image storage circuit 111, 121 , 131 switch 112, 122, 132 selector 113, 133 memory 123 # 1 memory 124 # 2 memory 125 #n memory 114, 126, 134 storage / reproduction control circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masaki Yamashina 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. An AD conversion circuit for converting an analog video signal sent to a partner device into a digital video signal, and a D-D circuit for converting a digital video signal created from a signal received from the partner device into an analog video signal. A videophone device including an A conversion circuit for transmitting and receiving a digitized video signal, comprising a memory capable of accumulating a digital video signal input to the D-A conversion circuit, and the digital signal accumulated in the memory. A video telephone device comprising an image storage circuit for outputting a video signal to the D-A conversion circuit. 2. An AD conversion circuit for converting an analog video signal sent to a partner device into a digital video signal, and a D-D converter for converting a digital video signal created from a signal received from the partner device into an analog video signal. In a videophone device including an A conversion circuit for transmitting and receiving a digitized video signal, a digital video signal input to the D-A conversion circuit and a digital video signal output by the A-D conversion circuit are accumulated. A videophone device having a memory capable of storing the image data, and an image storage circuit for outputting the digital video signal stored in the memory to the D-A conversion circuit.