JPH06153175A - High efficiency coding device for digital video signal - Google Patents

Abstract

PURPOSE:To prevent a quantization error from being concentrated on difference data whose transmission is omitted in order to provide compatibility of the high efficiency coding system between two video signal systems with different resolution or to reduce the transmission data quantity. CONSTITUTION:By taking a ratio N ( 4) of resolution of a high vision signal and an NTSC signal into account, sub blocks of (2X2=4) are formed. A block processing and average value generating circuit 2 generates a mean value (y) of each sub block. A men value coding circuit 8 encodes a mean value of (4X4) sub blocks. With respect to data of each picture element, a subtractor 7 generates a difference DELTAx with a mean value and the difference is coded by a difference coding circuit 9. A difference optimizing circuit 10 is provided after the circuit 9 and the coded difference value is changed in a quantization step width so as to minimize the sum of quantization errors with respect to four picture elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency coding apparatus for digital video signals, which is compatible with the coding of two types of digital video signals having different resolutions.

[0002]

2. Description of the Related Art As a television system, for example, a high-definition system, which has a higher resolution than a standard system such as a practically used NTSC system, has been proposed. Research and development of equipment is done. It has also been proposed to record high resolution video signals, for example in the form of digital data. Even with the current standard system, the amount of information in the digital video signal is large and the high resolution digital video signal (H
In the case of the D signal), it is necessary to record / reproduce a larger amount of information. For this reason, when recording HD signals, it is usual to employ high-efficiency coding for compressing the amount of recording data.

Conventionally, the high-efficiency coding applied to an HD signal and the high-efficiency coding applied to a standard digital video signal (referred to as an SD signal) are independent. There was no compatibility between. However, during the period when a plurality of methods are mixed, the digital V
Considering the case of TR, a digital VTR for HD signals
It is preferable that the tape recorded by (HD VTR) can be reproduced by a digital VTR for SD signal (called SD VTR). On the contrary, SD V
It is preferable that the tape recorded by TR can be reproduced by HD VTR. The bidirectional compatibility described above is effective not only for VTRs but also for transmission / reception of digital video signals in that the encoding device and the decoding device are commonly used and the scale of hardware is reduced.

Therefore, the applicant of the present application has proposed a high-efficiency coding apparatus for digital video signals having bidirectional compatibility between HD signals and SD signals. This encoding device averages N pieces of pixel data, for example, 4 pieces, which are approximately equal to the resolution ratio of SD signals and HD signals, blocks 16 pieces of averaged data, and block-encodes them. The difference data between the pixel data of the signal and the averaged data is encoded, and the encoded output of the averaged data and the encoded output of the difference data are recorded. In this method, S
A reproduced image can be obtained by the D VTR reproducing the average value information of the tape recorded by the HD VTR.
The HD VTR can obtain a reproduced image by decoding each pixel data of the tape recorded by the SD VTR.

The above-mentioned high efficiency coding device will be described in more detail. As shown in FIG. 5, the HD signal is divided into (2 pixels × 2 lines) sub-blocks. Pixel data x1, x2, x3, and x4 are included in the sub-block. The size of the sub-block substantially corresponds to the resolution or the data amount ratio of the HD signal and the SD signal. For example H
The HD signal, which is one of the D signals, is the current NT
The number of pixels in the horizontal direction and the number of lines in the vertical direction are approximately double and the resolution is approximately four times that of the SC system.
Therefore, the sub-block is composed of four pixels.

Next, as shown in FIG. 6, the average value y is formed from the pixel data of each sub-block. Therefore, FIG.
From (8 pixels × 8 lines) area of (4 × 4 = 1 in FIG.
6) An average value is formed. When the average value is y, y = 1 / 4Σx _i (1) (Σ means the sum from i = 1 to i = 4). If the difference value of each pixel from the average value y of the HD signal is Δi, then Δ _i = x _i −y (2).

Here, ΣΔx _i = Σ (x _i −y) = Σx _i −4 y = 0 (3) Therefore, if y, Δx1, Δx2, and Δx3 are known, Δx4 = −Σ′Δx _i (4) (Σ ′ means the sum from i = 1 to i = 3.)
Thus, Δx4 can be obtained. Therefore, Δx4
It is possible to reduce the amount of data to be transmitted by omitting the transmission of.

[0008]

However, since the decoded value of x includes the quantization error, the equation (4) cannot be established. When the decoded value of x ^ x and _{denoted, ΣΔ ^ x i ≠ 0 (} 5) where an error between the true value of delta ^ x _i represents the _{ε i, εi = Δ ^ x} i -Δx i (6 ), Ε4 = Δ ^ x4−Δx4 = −Σ′Δ ^ x _i −Δx4 = −Σ ′ (Δx _i + ε _i ) −Δx4 From equation (3) or (4), = −Σ′ε _i ( 7) and the quantization error of Δx1, Δx2, and Δx3 is Δx4.
Concentrate on.

Therefore, an object of the present invention is to provide a high-efficiency coding apparatus for a digital video signal, which can solve the problem that the quantization error concentrates on the omitted difference value when the transmission of one difference value is omitted. To do.

[0010]

According to the present invention, a second standard video signal having a higher resolution than the first standard video signal is supplied, and this signal is digitized and then compression coded for transmission. In a high-efficiency encoder for digital video signals, an averaging circuit for averaging N pixel data that is approximately equal to the ratio of the resolutions of the first and second standard video signals of the digital video signal, and the averaging circuit A first encoding circuit for block-coding a plurality of average data and block-encoding the difference data between N pixel data and average data so that the total error after decoding is minimized. , A second encoding circuit that outputs a value obtained by changing the quantized data and omits transmission of one of the N difference data, and outputs of the first and second encoding circuits. It is a high-efficiency encoding apparatus of a digital video signal comprising a means for transmitting.

[0011]

After the quantization, the optimization process for correcting the transmitted difference value is performed. This modification is to increase or decrease each difference value by the quantization step width so as to minimize the sum of squared errors. By this optimization, it is possible to prevent errors from being concentrated on the decoded value of the difference value that is not transmitted.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example of a digital video signal recording apparatus for recording an HD signal, for example, a high-definition signal on a magnetic tape by a rotary head.

In FIG. 1, reference numeral 1 is an input terminal of an HD signal to be recorded, and each pixel of this video signal is digitized into 8 bits. The HD signal is supplied to the block formation and average value generation circuit 2. In this circuit 2,
The sampling cycle delay circuit represented by T and the line cycle delay circuit represented by H synchronize four (2 × 2) pixels, and the addition circuit 3 for adding pixel data and the addition output ¼ The average value y of the pixel data
Is generated.

The average value y is supplied to the subtraction circuit 7 and the average value encoding circuit 8 via the register 5. The pixel data x1 to x4 are transferred to the subtraction circuit 7 via the switching circuit 6.
Are sequentially supplied. The subtraction circuit 7 produces difference data Δx _i for each pixel. The difference data is supplied to the difference value encoding circuit 9. The encoded output of the difference value encoding circuit 9 is supplied to the difference value optimizing circuit 10. Although not shown, the coded output SDDT of the average value coding circuit 8 and the coded output HDDT of the difference value optimization circuit 10 are supplied to the framing circuit. In the framing circuit, processing such as error correction coding and conversion of the data structure into recording data composed of sync blocks is performed.

Recording data output from the framing circuit is supplied to the rotary head via a channel encoding circuit, a recording amplifier, etc., and recorded on a magnetic tape. As a method of recording data on the magnetic tape, for example, the track pattern of FIG. 2 can be adopted. That is, as the rotary head device, a device in which a pair of double azimuth heads having two gaps close to each other and facing each other by 180 ° are provided on the drum is used. Two tracks A and B are simultaneously formed on the tape by one double azimuth head, and then two tracks A ′ and B ′ are formed by the other double azimuth head. The data HDDT generated from the difference value optimizing circuit 10 is recorded as tracks A and A ′, and the data SDDT generated from the average value encoding circuit 8 is recorded as tracks B and B ′.

The HD VTR can reproduce all the data of the track pattern and can reproduce the HD signal by the decoding process. The SD VTR reproduces only the tracks B and B'of the track pattern of FIG. And
Average value data can be obtained by decoding the reproduced data SDDT. From this average value data, S
Restore the D image.

The encoding circuits 8 and 9 are for compressing the data amount of the average value data and the difference value data,
For example, a quantization circuit that compresses each data by requantization can be used. The feature of the present invention is that the difference value optimizing circuit 10
Thus, the difference value optimization process is performed to correct the quantized data. This processing is to allow the encoded value Δx ′ of the difference value Δx to be increased or decreased by the quantization step width d. Therefore, the difference value data Δ actually recorded / reproduced
x ″ can be expressed as Δxi ″ (k _i ) = Δxi ′ + k _i d _i (i = 1, 2, 3) (8). Here, k _i = −1,0,1 (9). Therefore, the corrected error is ε _i ′ = Δxi ″ (k _i ) −Δx _i = ε _i + k _i d _i (10).

Further, the sum of squared error E is used as an index of the total error. E (k ₁ , k ₂ , k ₃ ) = Σε _i ′ ² = Σ′ε _i ′ ² + (− Σ′ε _i ′) ² = Σ ″ {(ε _i + k _i d _i ) + (ε _j + k _{j dj} )} ² (11) (Σ ″ means addition of 1 ≦ i ≦ 2 and 1 ≦ j ≦ 3.)

Minimize E () (k ₁ , k ₂ , k ₃ ).
Then, (k ₁ ′, k ₂ ′, k ₃ ′) is obtained. (K ₁ ′, k ₂ ′, k ₃ ′) = {(k ₁ , k ₂ , k ₃ ) | E (k ₁ , k ₂ , k ₃ ) = min E (l _1, l _2, l ₃ ) } (L _1,2,3 = -1,0,1) (12) As the final difference value data after the difference value optimization, Δxi ″ (k _i ′) = Δxi ′ + k _i ′ Record and transmit d _i (i = 1, 2, 3) (13).

With the above arrangement, it is possible to prevent the error from being concentrated on the difference value Δx4 in which the transmission is omitted. Further, in the optimization process, the amount of change from the original quantized value is limited to the quantization step width, so the quantized data need only be ± 1 at most, and no additional data is required. There is.

Note that E is minimized (k ₁ , k ₂ ,
When there are a plurality of sets of k ₃ ), a set having a smaller absolute value sum Σ ′ | k _i d _i | of data correction amounts is selected. Even at this stage, if there are a plurality of candidates, an arbitrary set is used. If the original quantized value has reached the maximum value or the minimum value, exception processing is necessary, but details thereof will be omitted.

For the average value encoding circuit 8 or the difference value encoding circuit 9 in FIG.
An RC (dynamic range adaptive coding) method may be applied. The ADRC encoding is proposed by the applicant of the present application, and is the maximum value MAX of the pixel data in the ADRC block.
Range D, which is the difference between the minimum value MIN and the minimum value MIN
The encoding is adapted to R. In this example, the average value data or difference value of (4 × 4) is used as the ADRC block.

FIG. 3 shows an example of the ADRC encoder. Input data in the order of blocks is supplied from the input terminal 21, and the maximum value M for each block is detected by the detection circuit 22.
AX and the minimum value MIN are detected. In the subtraction circuit 23, the dynamic range DR is calculated by (MAX-MIN + 1 = DR). Also, the input data is supplied to the subtraction circuit 25 via the delay circuit 24 for timing adjustment. In the subtraction circuit 25, the minimum value MIN is subtracted from the input data, and the data after the removal of the minimum value is obtained.

The data after the removal of the minimum value and the dynamic range DR are supplied to the quantization circuit 26, and the data is quantized into a code signal DT having a 4-bit length, for example, in accordance with the dynamic range DR. The quantization is Qi = [(xi−MIN + 0.5) × (2 ⁴ / DR)], where Qi is the quantized value and xi is the value of the input data.
It is rounding down. The number of bits of the code signal DT is not limited to 4 bits, and a code signal having a variable number of bits may be formed.

FIG. 4 shows an example of the configuration of a decoding circuit provided in the reproduction system of the digital VTR. Among the reproduced data reproduced from the tape and subjected to the processes such as channel decoding and error correction, the average value encoded data SDDT is supplied to the average value decoding circuit 31, and the difference value encoded data HDDT of the reproduced data is supplied. Is supplied to the difference value decoding circuit 32. Decoding output of average value decoding circuit 31 and difference value decoding circuit 3
The decoded output of 2 is supplied to the adder circuit 33. By the adder circuit 33, three HD signal pixels x1, x2, and x3 corresponding to the encoded data of the three difference values reproduced.
The decoded value of is formed.

For the pixel x4 for which transmission has been omitted, the decoded average value is supplied to the subtraction circuit 35 via the multiplication circuit 34 (which can be constituted by a shift register). On the other hand, x
The decoded values for 1, x2 and x3 are accumulated by the accumulation circuit 36, and the accumulated value is supplied to the subtraction circuit 35. In the subtraction circuit 35, the decoded values of the other three pixels are subtracted from the value four times the decoded average value, and therefore the decoded value of the pixel x4 appears from the subtraction circuit 35. As for the pixel x4, as described above, the difference value decoding circuit 32 may obtain Δx4 from other difference values and decode it.

In the above embodiment, the simple average value is used as the average value information, but a weighted average value may be used. The weighted average value y ′ is represented by y ′ = Σw _i x _i , and the sum of the weighting factors w _i is 1.

Further, as the difference value, a method of using the difference from the local decoded value of the average value may be adopted.
In this case, the equation (3) itself does not hold exactly, and the error is also concentrated on Δx4. Therefore, the concentration of this error can also be prevented by the present invention.

[0029]

According to the present invention, a block having a size considering the resolution ratio of the two types of video signals is taken into consideration, and the data amount after encoding can be made substantially equal in both types. Further, since the average value information and the difference value data are encoded separately, an HD image can be constructed by decoding the average value information and the difference value information, and an SD image can be obtained by decoding only the average value information. Can be configured. According to the present invention, since the transmission of one encoded value of the difference value data is omitted, the transmission data amount can be reduced,
Further, it is possible to prevent the error from concentrating on pixels for which transmission is omitted.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an example of a track pattern of this embodiment.

FIG. 3 is a block diagram of an example of an encoding circuit.

FIG. 4 is a block diagram of an example of a decoding device.

FIG. 5 is a schematic diagram showing a block composed of HD signals.

FIG. 6 is a schematic diagram showing a block composed of average values of HD signals.

[Explanation of symbols]

 2 Blocking and average value generation circuit 7 Subtraction circuit 8 Average value coding circuit 9 Difference value coding circuit 10 Difference value optimization circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kunio Kawaguchi 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (2)

[Claims] 1. A high-efficiency coding of a digital video signal supplied with a second standard video signal having a resolution higher than that of the first standard video signal, digitized, and then compressed and coded for transmission. In the apparatus, an averaging means for averaging N pixel data which is approximately equal to a ratio of resolutions of the first and second standard video signals of the digital video signal, and a plurality of average data from the averaging means are provided. First encoding means for block-forming and block-encoding, quantizing data of respective differences between the N pixel data and the average data, and quantizing so as to minimize a total error after decoding. Second encoding means for outputting a value obtained by changing the data after encoding and omitting transmission of one of the N differential data, and outputs of the first and second encoding means High-efficiency encoding apparatus of a digital video signal comprising a means for transmitting. 2. A high-efficiency encoder for digital video signals according to claim 1, wherein the averaging means forms weighted average data.