JPH06152549A - Operating level measuring device - Google Patents

Operating level measuring device

Info

Publication number
JPH06152549A
JPH06152549A JP4295964A JP29596492A JPH06152549A JP H06152549 A JPH06152549 A JP H06152549A JP 4295964 A JP4295964 A JP 4295964A JP 29596492 A JP29596492 A JP 29596492A JP H06152549 A JPH06152549 A JP H06152549A
Authority
JP
Japan
Prior art keywords
correction value
cpu
level
prom
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4295964A
Other languages
Japanese (ja)
Inventor
Masayuki Onuki
政幸 大貫
Toshiaki Suzuki
利昭 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4295964A priority Critical patent/JPH06152549A/en
Publication of JPH06152549A publication Critical patent/JPH06152549A/en
Withdrawn legal-status Critical Current

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  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To simplify the operation of a corrected value storage, and to obtain an exact measured value even when a variation is generated among products by providing an automatic corrected value calculating means and a corrected value storage means. CONSTITUTION:For example, an IF(intermediate frequency signal) level monitor circuit of a modulating unit(NOD) 40 is equipped with a level detecting circuit constituted of a detector 30 and a multiplier 32, A/D converter 48, CPU 50, and E<2>PROM 52. The CPU 50 transmits an instruction to set the frequency of an outside oscillator 64 at a prescribed intermediate frequency, gradually changes an output level, and inputs data from the A/D converter 48. The CPU 50 discriminates whether or not the inputted data are matched with a designed value within a prescribed permitted range. Then, when the inputted data are not matched with the designed data, the CPU 50 prepares a conversion table, and writes it in the E<2>PROM 52. When the inputted data are matched with the designed data, the CPU 50 writes a flag to indicate that the correction s not necessary in the E<2>PROM 52.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、通信設備等の設備内の
送信ユニット、受信ユニット、変調ユニット、電源ユニ
ット等の回路ユニットの保守・点検のためにその動作レ
ベルを測定するための動作レベル測定装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation level for measuring the operation level of a transmission unit, a reception unit, a modulation unit, a power supply unit and other circuit units in equipment such as communication equipment for maintenance and inspection. Regarding measuring device.

【0002】[0002]

【従来の技術】パッケージ化された送信ユニット(以下
TXと称する)、受信ユニット(RX)、変調ユニット
(MOD)、電源ユニット(PS) 等の回路ユニットを
含んで構成される通信設備の保守・点検のため、従来で
は図5に示される様な構成がとられていた。
2. Description of the Related Art Maintenance of communication equipment including circuit units such as a packaged transmission unit (hereinafter referred to as TX), reception unit (RX), modulation unit (MOD), power supply unit (PS), etc. For inspection, the structure shown in FIG. 5 has been conventionally used.

【0003】MOD 10,TX 12,RX 14およびP
S 16のパッケージ内には、それぞれ、IF(中間周波
信号)レベル、送信出力レベル、受信レベル、および一
次,二次電圧のモニタ回路が設けられている。それらか
ら出力されるアナログ電圧は通信設備内に備えられたS
V INTF(supervisor interface) 18内のA/D
変換器20へ入力されてデジタル信号へ変換され、CP
U 22へ入力される。CPU 22には通信用IC 24と
2 PROM 26が接続される。モニタ回路は、例えば
MOD 10では、IF AMP 28の出力に接続された
検波器30およびその出力を増幅するOPアンプ、抵
抗、コンデンサ等で構成される増幅器32から構成され
る。
MOD 10, TX 12, RX 14 and P
Inside the package of S 16 are provided monitor circuits for IF (intermediate frequency signal) level, transmission output level, reception level, and primary and secondary voltages, respectively. The analog voltage output from them is S provided in the communication equipment.
A / D in V INTF (supervisor interface) 18
It is input to the converter 20 and converted into a digital signal,
Input to U 22. A communication IC 24 and an E 2 PROM 26 are connected to the CPU 22. In the MOD 10, for example, the monitor circuit includes a detector 30 connected to the output of the IF AMP 28 and an amplifier 32 configured by an OP amplifier, a resistor, a capacitor and the like for amplifying the output.

【0004】保守・点検時には、SV INTF 18の
通信用IC 24にMPT(Maintenance Portable Termi
nal) 34を接続する。MPT 34に入力されたコマンド
に従って、CPU 22は所望個所のレベル値をデジタル
で収集し、E2 PROM 26に格納されている補正値で
補正して通信用IC 24を介してMPT 34へ出力し、
それによってMPT34のディスプレイ上に測定値がデ
ジタル表示される。
At the time of maintenance and inspection, MPT (Maintenance Portable Termi) is added to the communication IC 24 of the SV INTF 18
nal) 34 is connected. According to the command input to the MPT 34, the CPU 22 digitally collects the level value at a desired position, corrects it with the correction value stored in the E 2 PROM 26, and outputs it to the MPT 34 via the communication IC 24. ,
As a result, the measured value is digitally displayed on the display of the MPT 34.

【0005】[0005]

【発明が解決しようとする課題】E2 PROM 26には
各モニタ回路のゲイン及び/又は直線性を補正するため
の補正値が格納されているが、従来では組上げられた多
数のパッケージから数個のパッケージを抽出してそれぞ
れ特性を測定し、補正値を算出し、それらの平均値を算
出して手動で入力して格納していた。
The E 2 PROM 26 stores a correction value for correcting the gain and / or linearity of each monitor circuit. In the past, however, several correction values have been stored in a large number of assembled packages. The package was extracted, the characteristics of each package were measured, the correction value was calculated, and the average value thereof was calculated and manually input and stored.

【0006】そのため、操作が煩雑であり、また、パッ
ケージの特性が製品によってバラツキがあるときは誤差
が大きくなるという問題があった。したがって本発明の
目的は、補正値格納のための操作が簡単であり、かつ、
パッケージの製品間でバラツキがあっても正確な測定値
を得ることのできる動作レベル測定装置を提供すること
にある。
Therefore, there is a problem that the operation is complicated and the error becomes large when the characteristics of the package vary depending on the products. Therefore, an object of the present invention is that the operation for storing the correction value is simple, and
An object of the present invention is to provide an operation level measuring device capable of obtaining an accurate measured value even if there are variations among packaged products.

【0007】[0007]

【課題を解決するための手段】前述の問題を解決する本
発明の動作レベル測定装置は、回路ユニット上に設けら
れ、該回路ユニットの動作レベルを測定するレベル測定
手段と、該レベル測定手段へ基準信号が入力されたとき
の測定値から該レベル測定手段の測定値を補正するため
の補正値を自動的に算出する自動補正値算出手段と、該
自動補正値算出手段が算出した補正値を該回路ユニット
の個々の製品の各々に対応させて記憶する補正値記憶手
段とを具備することを特徴とするものである。
SUMMARY OF THE INVENTION An operation level measuring device of the present invention for solving the above-mentioned problems is provided on a circuit unit, and a level measuring means for measuring an operation level of the circuit unit, and to the level measuring means. An automatic correction value calculation means for automatically calculating a correction value for correcting the measurement value of the level measurement means from the measurement value when the reference signal is input; and a correction value calculated by the automatic correction value calculation means. And a correction value storage means for storing the product corresponding to each individual product of the circuit unit.

【0008】[0008]

【作用】自動補正値算出手段が特性を自動的に測定して
補正値を算出し、それが補正値記憶手段に記憶されるの
で、操作が簡単である。また、補正値は回路ユニットの
個々の製品毎に記憶されるので、製品によって特性にバ
ラツキがある場合でも正確な測定が可能である。
The automatic correction value calculating means automatically measures the characteristic to calculate the correction value, and the correction value is stored in the correction value storing means, so that the operation is simple. In addition, since the correction value is stored for each individual product of the circuit unit, accurate measurement is possible even when the characteristics of each product vary.

【0009】[0009]

【実施例】図1は本発明の第1の実施例を表わすブロッ
ク図である。本実施例においては、変調ユニット(MO
D)40、送信ユニット(TX)42、受信ユニット
(RX)44、及び電源ユニット(PS)46にそれぞ
れ具備されるIFレベルモニタ回路、送信出力レベルモ
ニタ回路、受信レベルモニタ回路、及び一次,二次電圧
モニタ回路はそれぞれのレベル検出回路の他にA/D変
換器48、CPU 50、及びE2 PROM 52を具備し
ている。
1 is a block diagram showing a first embodiment of the present invention. In this embodiment, the modulation unit (MO
D) 40, transmission unit (TX) 42, reception unit (RX) 44, and power supply unit (PS) 46, respectively, an IF level monitor circuit, a transmission output level monitor circuit, a reception level monitor circuit, and primary and secondary The next voltage monitor circuit includes an A / D converter 48, a CPU 50, and an E 2 PROM 52 in addition to the respective level detection circuits.

【0010】SV INTF 54は図5の従来例と同
様、CPU 56およびMPT 58との接続のための通信
用IC 60を含んで構成されるが、補正値を格納する必
要がないので、E2 PROM 26のかわりにPROM 6
2が具備される。図2は回路ユニット、例えばMOD 4
0が組み上がった後の補正値書込みの手順を表わすフロ
ーチャートである。図1および図2を参照しつつ第1の
実施例における補正値書込みの手順を説明する。
Like the conventional example of FIG. 5, the SV INTF 54 is configured to include a communication IC 60 for connection with the CPU 56 and the MPT 58, but since it is not necessary to store a correction value, E 2 PROM 6 instead of PROM 26
2 is provided. Figure 2 shows a circuit unit, eg MOD 4
9 is a flowchart showing a procedure for writing a correction value after 0 is assembled. A procedure for writing a correction value in the first embodiment will be described with reference to FIGS. 1 and 2.

【0011】最初に、外部発振器64の出力を回路ユニ
ットの基準信号入力端子に接続し、外部発振器64の周
波数、レベル設定入力および制御入力をCPU 50に接
続する(ステップ1000)。なお、PS 46の場合に
は外部電圧発生器66が接続される。MPT 58より補
正値書込みの指令が入力されると、通信用IC 60およ
びCPU 56を経てCPU 50へそれが伝達される(ス
テップ1002)。CPU 50は外部発振器64の周波
数を所定の中間周波数に設定する命令を送り、さらに出
力レベルを段階的に変化させながらその都度A/D変換
器48からデータを入力する(ステップ1004)。C
PU 50は入力されたデータが所定の許容範囲内で設計
値と一致しているか否かを判定し(ステップ100
6)、一致していなければ変換テーブルを作成し(ステ
ップ1008)、E2 PROM 52へ書込む(ステップ
1010)。設計値と一致していれば、補正の必要がな
いことを示すフラグをE2 PROM 52へ書込む(ステ
ップ1012)。
First, the output of the external oscillator 64 is connected to the reference signal input terminal of the circuit unit, and the frequency, level setting input and control input of the external oscillator 64 are connected to the CPU 50 (step 1000). In the case of PS 46, the external voltage generator 66 is connected. When a correction value writing command is input from the MPT 58, it is transmitted to the CPU 50 via the communication IC 60 and the CPU 56 (step 1002). The CPU 50 sends an instruction to set the frequency of the external oscillator 64 to a predetermined intermediate frequency, and inputs data from the A / D converter 48 each time while changing the output level stepwise (step 1004). C
The PU 50 determines whether or not the input data matches the design value within a predetermined allowable range (step 100).
6) If they do not match, a conversion table is created (step 1008) and written in the E 2 PROM 52 (step 1010). If it agrees with the design value, a flag indicating that no correction is necessary is written in the E 2 PROM 52 (step 1012).

【0012】以後は、CPU 50はMPT 58からの指
令に応じてレベルを測定した後、前記のフラグが立って
いなければ補正値を読み出して補正演算を行い出力す
る。図3は本発明の第2の実施例を表わすブロック図で
ある。本実施例においては、各回路ユニットに、モニタ
回路30,32の他に、製品を識別するためのパッケー
ジ識別用ID設定回路70が設けられる。ID設定回路
70は例えば基板上に実装可能なディップスイッチ又は
ロータリースイッチからなり、製品毎に異なる値が設定
される。SV INTF 72に具備されるE2PROM
74には各回路ユニットについてID毎に補正値が格納
され、MPT 58からレベル読み出しの指令が入力され
たとき、CPU 56はA/D変換器76を介してレベル
値を読み出すとともにIDを読み出し、それに対応して
2 PROM 74に格納されている補正値を使って補正
し、出力する。
After that, the CPU 50 measures the level according to a command from the MPT 58, and if the flag is not set, reads the correction value, performs the correction calculation, and outputs the correction value. FIG. 3 is a block diagram showing a second embodiment of the present invention. In this embodiment, each circuit unit is provided with a package identification ID setting circuit 70 for identifying a product, in addition to the monitor circuits 30 and 32. The ID setting circuit 70 includes, for example, a dip switch or a rotary switch that can be mounted on a substrate, and a different value is set for each product. E 2 PROM included in SV INTF 72
A correction value is stored for each ID for each circuit unit in 74, and when a level reading command is input from the MPT 58, the CPU 56 reads the level value via the A / D converter 76 and reads the ID. Correspondingly, the correction value stored in the E 2 PROM 74 is used for correction and output.

【0013】図4は図3の実施例において補正値書込み
の手順を表わすフローチャートである。図2の場合と同
様に、外部発振器64の出力を回路ユニットの基準信号
入力端子に接続する(ステップ1020)。設定入力お
よび制御入力はSV INTF72のCPU 56に接続
し、CPU 56からすべての制御を行う。MPT 58よ
り補正値書込みの指令が入力されると、通信用IC 60
を経てCPU 56へ伝送される(ステップ1022)。
CPU 56はまず回路ユニットのID設定回路70から
パッケージ識別用IDを読み出す(ステップ102
4)。続いて、CPU56は図2で説明したCPU 50
が行ったと同様な制御を外部発振器64に対して行いA
/D変換器76からデータを自動的に取得し(ステップ
1026)、図2の場合と同様にして変換テーブル又は
フラグをE2 PROM 74に書込む(ステップ1028
〜1034)。このとき、ステップ1024において読
み出したIDに対応させて変換テーブル又はフラグを書
込む。
FIG. 4 is a flow chart showing the procedure for writing the correction value in the embodiment of FIG. As in the case of FIG. 2, the output of the external oscillator 64 is connected to the reference signal input terminal of the circuit unit (step 1020). The setting input and control input are connected to the CPU 56 of the SV INTF 72, and the CPU 56 controls all operations. When the correction value writing command is input from the MPT 58, the communication IC 60
Then, it is transmitted to the CPU 56 (step 1022).
The CPU 56 first reads the package identification ID from the ID setting circuit 70 of the circuit unit (step 102).
4). Subsequently, the CPU 56 is the CPU 50 described in FIG.
The same control as that performed by the external oscillator 64
Data is automatically acquired from the / D converter 76 (step 1026), and the conversion table or flag is written in the E 2 PROM 74 in the same manner as in FIG. 2 (step 1028).
1034). At this time, the conversion table or flag is written in association with the ID read in step 1024.

【0014】[0014]

【発明の効果】以上述べてきたように本発明によれば、
簡単な操作で補正値を書き込むことが可能であり、製品
間でバラツキがある場合でも正確な補正をすることが可
能である。
As described above, according to the present invention,
The correction value can be written by a simple operation, and accurate correction can be performed even if there are variations among products.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を表わすブロック図であ
る。
FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図2】図1の装置における補正値書込みの手順を表わ
すフローチャートである。
FIG. 2 is a flowchart showing a procedure for writing a correction value in the apparatus of FIG.

【図3】本発明の第2の実施例を表わすブロック図であ
る。
FIG. 3 is a block diagram showing a second embodiment of the present invention.

【図4】図1の装置における補正値書込みの手順を表わ
すフローチャートである。
4 is a flowchart showing a procedure for writing a correction value in the apparatus of FIG.

【図5】従来の補正値書込みの方式を説明するための図
である。
FIG. 5 is a diagram for explaining a conventional correction value writing method.

【符号の説明】[Explanation of symbols]

10,40…変調ユニット(MOD) 12,42…送信ユニット(TX) 14,44…受信ユニット(RX) 16,46…電源ユニット(PS) 64…外部発振器 10, 40 ... Modulation unit (MOD) 12, 42 ... Transmission unit (TX) 14, 44 ... Reception unit (RX) 16, 46 ... Power supply unit (PS) 64 ... External oscillator

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 回路ユニット上に設けられ、該回路ユニ
ットの動作レベルを測定するレベル測定手段(30,3
2)と、 該レベル測定手段へ基準信号が入力されたときの測定値
から該レベル測定手段の測定値を補正するための補正値
を自動的に算出する自動補正値算出手段(50;56)
と、 該自動補正値算出手段が算出した補正値を該回路ユニッ
トの個々の製品の各々に対応させて記憶する補正値記憶
手段(52;74)とを具備することを特徴とする動作
レベル測定装置。
1. A level measuring means (30, 3) provided on a circuit unit for measuring an operation level of the circuit unit.
2) and an automatic correction value calculation means (50; 56) for automatically calculating a correction value for correcting the measurement value of the level measurement means from the measurement value when the reference signal is input to the level measurement means.
And a correction value storage means (52; 74) for storing the correction value calculated by the automatic correction value calculation means in association with each individual product of the circuit unit. apparatus.
【請求項2】 複数の回路ユニットにおける前記レベル
測定手段の測定値を収集する収集手段(54;72)を
さらに具備する請求項1記載の動作レベル測定装置。
2. The operation level measuring device according to claim 1, further comprising a collecting means (54; 72) for collecting the measurement values of the level measuring means in a plurality of circuit units.
【請求項3】 前記補正値記憶手段(52)は前記回路
ユニット上に設けられる請求項1または2記載の動作レ
ベル測定装置。
3. The operation level measuring device according to claim 1, wherein the correction value storage means (52) is provided on the circuit unit.
【請求項4】 前記回路ユニットは製品を識別するため
の識別符号を出力する識別符号出力手段(70)を有
し、 前記補正値記憶手段(74)は該識別符号に対応させて
前記補正値を記憶する請求項1または2記載の動作レベ
ル測定装置。
4. The circuit unit has an identification code output means (70) for outputting an identification code for identifying a product, and the correction value storage means (74) corresponds to the identification code and the correction value. The operation level measuring device according to claim 1, which stores
JP4295964A 1992-11-05 1992-11-05 Operating level measuring device Withdrawn JPH06152549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4295964A JPH06152549A (en) 1992-11-05 1992-11-05 Operating level measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4295964A JPH06152549A (en) 1992-11-05 1992-11-05 Operating level measuring device

Publications (1)

Publication Number Publication Date
JPH06152549A true JPH06152549A (en) 1994-05-31

Family

ID=17827369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4295964A Withdrawn JPH06152549A (en) 1992-11-05 1992-11-05 Operating level measuring device

Country Status (1)

Country Link
JP (1) JPH06152549A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5649887A (en) * 1995-05-24 1997-07-22 Okuma Corporation Machine tool provided with tool changer
JP2001235517A (en) * 1999-12-23 2001-08-31 Em Microelectronic Marin Sa Integrated circuit equipped with means for calibrating electronic module and method for calibrating electronic module of integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5649887A (en) * 1995-05-24 1997-07-22 Okuma Corporation Machine tool provided with tool changer
JP2001235517A (en) * 1999-12-23 2001-08-31 Em Microelectronic Marin Sa Integrated circuit equipped with means for calibrating electronic module and method for calibrating electronic module of integrated circuit

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