JPH06149678A - Cache control circuit - Google Patents

Abstract

PURPOSE:To improve a hit rate by a pseudo set associative system by switching an external FF together with the switching of a context register in a cache control unit so as to switch the cache control unit concerned without using a multichip mode. CONSTITUTION:This cache control circuit is provided with an FF 4 connected to plural cache control units 1 to set up a selection signal for selecting one of the control unit 1 and constituted so that a value is set up in the FF 4 correspondingly to the sending of a rewrite signal for a context register 3 from an access requesting source to switch its connection to the cache control unit 1 in the corresponding space, a space address is set up in the register 3 in the unit l, a tag memory 2 in the unit 1 is retrieved correspondingly to the succeeding access request and data are sent from a cache memory 6 when a hit is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control circuit for controlling a cache. Computers adopting the SPARC architecture (one of RISC architectures) and the like are becoming higher in performance in the trend of standardization. Generally, in order to realize high performance, the CPU clock speed is increased and CP is increased.
U Make the internal architecture a superscalar, etc. to enable parallel execution. Improve memory access performance. There are techniques such as increasing the cache capacity to increase the cache hit rate. The speed of achieving higher performance is increasing year by year, and it is desired to improve the hit rate of the cache in order to achieve higher performance by combining LSIs provided by semiconductor manufacturers.

[0002]

2. Description of the Related Art Conventionally, a cache control unit (for example, CY7C604 and CY7C605 manufactured by Cypress Co., Ltd.) can control a cache of 64 Kbytes with one LSI chip. This LSI chip has a multi-chip mode. If two chips are used, the cache capacity can be easily increased to 64 × 2 = 128 Kbytes as shown in FIG. 10, and if four chips are used, 256 Kbytes can be increased. it can. The configuration and operation of FIG. 10 will be briefly described below.

FIG. 10 shows an explanatory view of the prior art. This shows an explanatory diagram of a configuration example of a multi-chip mode in which two cache control units 21 are used. In FIG. 10, cache control units # 1 and # 2 are cache control memory management LSIs. Here, the configuration used in the multi-chip mode is shown.

The numerical operation unit 22 is a unit for performing a numerical operation, and here issues an access request to the cache control units # 1 and # 2. The cache memory 23 is a memory that stores data and the like and reads the data at a high speed upon hit.

Next, the operation will be described. (1) Two cache control units # 1 and cache control unit # 2, which are cache control memory management LSIs, are connected as shown and a multichip mode is set. Further, the cache memory 23 is connected as shown.

(2) In the state of (1), FIG.
As shown in 1 (b), the cache tag doubles to 40
There are 96 entries. (3) When, for example, a read request is issued from the numerical calculation unit 22 using a virtual address, as shown in FIG. 11B, the VA read by reading the tag memory at the middle address and the upper address of the virtual address And the read CXN and the address of the space previously set in the context register match, it is determined to be a cache hit. At the time of cache hit, the data read from the cache memory 23 is sent to the numerical operation unit 22 of the access source via the data bus. On the other hand, in the case of a mishit, the data is read from the main memory (not shown) and written to the cache memory 23, and the address is written and stored in the tag memory of the cache control unit # 1 or the cache control unit # 2. .

(4) Numerical operation unit 2 of access source
2 takes in data from the data bus. In such a multi-chip mode, even if two cache control units # 1 and # 2 are connected,
The number of entries in the tag memory was only doubled to 4096 entries.

[0008]

In the conventional multi-chip mode configuration of FIG. 10 described above, the direct map type cache capacity shown in the one-chip mode of FIG. 11 (a) is shown in FIG. 11 (b). To increase (here, 20
(Increase from 48 entries to 4096 entries)
Compared to set-associative cache,
There was a problem that the cache hit rate with the same cache capacity could not be improved so much. Here, in the set associative method, the same offset address can be stored in each of the 2-way cache memories, and when the offset addresses are accessed alternately, a cache hit occurs and the hit rate improves. Hereinafter, FIG. 11 will be briefly described.

FIG. 11 (a) shows a cache configuration using one cache control unit. SPARC
In this architecture, the value of the internal context register is changed for each processing process to access the memory with a virtual address. The tag memory has 2048 entries and determines which tag line is selected by the middle address of the virtual address. Then, the virtual address VA (31 to 16) and the VA read from the tag memory
When (31 to 16) and CXN (11 to 0) and the value (11 to 0) set in the context register match, a cache hit is determined.

FIG. 11 (b) shows a cache configuration using two cache control units # 1 and # 2.
In this configuration, the tag memory is 2048 × 2 = 40
It has 96 entries, the number of tag line entries is doubled, and the number of direct map type entries is increased.

The present invention solves these problems.
Without using in the multi-chip mode, the external F
F to switch the cache control unit,
The purpose is to improve the hit rate by using the pseudo set associative method.

[0012]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, the cache control unit 1 determines hit / miss for an accessed address for each space, and has a tag memory 2 and a context register 3.

The tag memory 2 is for determining hit / miss of the cache memory 6, and the context register 3 is for setting a space address.

The FF 4 sets a signal indicating which cache control unit 1 is selected. The cache memory 6 is a memory for reading data when hit.

[0015]

According to the present invention, as shown in FIG. 1, a tag memory 2 and a context register 3 are provided in a cache control unit 1 and an FF 4 for switching the cache control unit 1 is provided externally, and a context register from an access request source is provided. Corresponding to the sending of the rewriting signal of 3, the value is set in FF4 and the cache control unit 1 of the corresponding space is set.
And the space address is set in the context register 3 of the cache control unit 1 and the cache memory 6 is searched when the tag memory 2 of the cache control unit 1 is searched and hit in response to the subsequent access request. To send the data to the data bus.

Further, when the number of cache control units 1 is 2n (n is a positive integer), an n-bit FF 4 is provided, and n of the addresses set in the context register 3 are selected.
A bit (for example, lower n bits) is set to FF4 to switch the cache control unit 1.

The access request source sends the first space address, sets n bits in FF4 to switch the cache control unit 1 to the corresponding one, and then sends the same second space address. A space address is set in the context register 3 of the cache control unit 1 that has switched levers to switch the cache control unit 1.

Therefore, the context register 3 of the cache control unit 1 is not used in the multi-chip mode.
By switching the external FF 4 and switching the cache control unit 1 in addition to the switching, it is possible to improve the hit rate by using the pseudo set associative method.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, the cache control unit 1 determines whether it is a cache hit or a miss in response to an access request from an access request source, and sends a data from a cache memory 6 (not shown) to a data bus at the time of hit. The data is transferred to the access request source, the data read from the main memory at the time of a miss is stored in the cache memory 6 and the address information thereof is stored in the tag memory 2, and the tag memory 2, And the context register 3 and the like.

The tag memory 2 is for determining whether or not the access request is a cache hit. Here, as shown in the figure, the tag memory 2 is read using the middle address (A15 to A5) of the virtual address for which access is requested as the tag line, and the read address VA (A31 to A16) and VA of the virtual address ( A31 to A16) are compared with each other by a comparator and coincident with each other, and the read address C
This is for determining a cache hit when XN (A11 to A0) and the address (spatial address) read from the context register 3 are compared by the comparator and they match.

The context register 3 is for setting a space address and the like. FF (flip-flop)
Reference numeral 4 sets a signal indicating which cache control unit 1 is selected. This is an FF externally added in the present invention, which writes n bits (for example, lower n bits) of a space address to be written in the context register 3, and when the cache control unit 1 is two, for example, Write the lower 1 bit to FF4. When the value of FF4 is "1", cache control unit #
Select 1 When the value of FF4 is "0", cache control unit #
It is switched so as to select 2 (see FIGS. 3 and 4).

The operation of the configuration of FIG. 1 will be described. (1) Initialize the cache control unit (# 1) 1 and the cache control unit (# 2) 1 to the single mode (normal mode).

(2) The access request source writes the space address in the context register 3 by the special instruction twice. (2-1) The space address is written to the context register 3 (the written space address becomes insignificant) in response to the issuance of the special instruction for writing the space address to the context register 3 for the first time. The lower 1 bit of the space address, for example, "1" is F
Write to F4 and cache control unit (# 1) 1
Switch to use.

(2-2) In response to the second issue of the special instruction for writing the same space address to the context register 3, the context of the switching cache control unit (# 1) 1 is set at (2-1). The space address is written in the register 3. As described above, the cache control unit (# 2) 1 is switched to the cache control unit (# 1) 1 and the space address is set in the context register 3.

(3) In response to the access request from the access request source, the tag memory 2 is read with the middle address (A15 to A5) of the virtual address as the tag line,
The read address VA (A31 to A16) and the virtual address VA (A31 to A16) are compared with each other by a comparator, and they match each other, and the read address CXN (A11 to A0) and the address read from the context register 3 (space) Address) is compared by a comparator, and when they match, it is determined as a cache hit.

(4) (3) When a cache hit is determined, data is sent from the cache memory 6 (not shown) to the data bus, and the access request source fetches the data from the data bus. On the other hand, when the cache miss is determined in (3), the data read from the main memory is sent to the data bus and transferred to the access request source, and stored in the cache memory 6 and the address information at that time is stored in the tag memory. Store in 2.

As described above, the FF 4 is provided externally, and when writing the space address to the context register 3, the n bits (lower 1 bit here) of the FF 4 are stored to store the cache control unit (# 1) 1 and the cache control. By switching to any of the units (# 2) 1 and realizing the pseudo set associative method, it is possible to improve the cache hit rate at the time of switching the spatial address. The details will be sequentially described below.

FIG. 2 is a diagram illustrating a specific example of the present invention. This is a specific circuit configuration example of the configuration of FIG. 2, the cache control unit (# 1) 1 and the cache control unit (# 2) 1 determine whether the access request is a cache hit or a cache miss. (# 1)
1 and cache control unit (# 2) 1
The tag memory 2 and the context register 3 are provided inside.

The numerical operation unit 5 is an access request source and is an LSI for calculating numerical values. The cache memory (# 1) 6 and the cache memory (# 2) 6 store data, and when the cache control unit (# 1) 1 or the cache control unit (# 2) 1 determines that there is a cache hit, the instruction is given. Correspondingly, data is sent to the data bus to enable high-speed reading and the like.

FF4 is a cache control unit (#
1) 1 and a cache control unit (# 2) according to the present invention provided outside the cache control unit (# 1) 1 and the cache control unit (# 2)
It switches between 1 and 1. Here, the space address is also set when setting it in the context register 3 in the cache control unit 1, and the cache control unit 1 to be used is switched.

Next, a specific example of the configuration of the FF 4 in FIG. 2 will be described in detail with reference to FIG. Here, in order for the cache control memory management LSI manufactured by Cypress (corresponding to the cache control unit 1) to write the context register 3, ASI = 0x04 and VA = 0x0200 from the integer arithmetic LSI (corresponding to the integer arithmetic unit 5) This is when the WE signal is active. Only when these conditions are met, here is a circuit configured to set VD00 (and also VD01 in the case of a 256 Kbyte cache) in the flip-flop 41, and hold the state otherwise. is there.

The special instruction is an instruction issued when the numerical operation LSI writes to the context register 3, and when this instruction is decoded, ASI = 0x04. Therefore, this is detected by hardware. is there.

The virtual address is a virtual address issued at the time of a special instruction. Since the context register 3 is written when VA = 0x0200, this is detected by hardware.

* WE is a signal for writing data to the context register 3. VD00 is the least significant 1 bit of data, and here is the flip-flop 41.
Data to be written to. When the least significant bit is "1", an active signal is sent to the CSEL of the cache control unit (# 1) 1 to switch to the cache control unit (# 1) 1. On the other hand, the least significant bit is “0”
Then the CSEL of the cache control unit (# 2) 1
To the cache control unit (# 2) 1 by sending an active signal to the cache control unit (# 2) 1.

The flip-flop 41 stores which CSEL of the cache control unit (# 1) 1 or the cache control unit (# 2) 1 the active signal is sent to.

Therefore, when the numerical operation unit 5 writes the data VD00 to the context register 3 only when ASI = 0x04, VA = 0x0200, and WE active by a special instruction, the numerical operation unit 5 also writes it to the flip-flop 41 and caches it. Control unit (# 1) 1 or cache control unit (# 2) 1
It is possible to switch to any of the above. As a result, here, the 2-way pseudo-set associative method can be realized.

When the software updates the context value of the context register 3 with reference to FIG. 4, it may be performed twice consecutively as shown in the figure. This will be described below. S1
Write an even context value. Here, since the operation is performed in the odd context process (the cache control unit (# 1) 1 is operating), the even context value is written (first write). As a result, an even context value (even space address) is written to the context register 3 of the cache control unit (# 1) 1, and the least significant 1 bit (even value “0”) is written to the FF4. Cache control unit (#
1) Switch from 1 to cache control unit (# 2) 1. Note that, here, it is insignificant to write an even number of context values to the context register 3.

S2 writes an even context value. Here, by writing an even context value to FF4 in S1, the cache control unit (#
2) Write an even number of context values while switching to 1 (second write). As a result, an even context value (even space address) is written to the context register 3 of the cache control unit (# 2) 1 to set the space address, and the least significant 1 bit (even value “0”) is set in the FF4. ) Is written. Here, the reason why the even number context value is written to FF4 is
It becomes redundant and redundant.

As described above, the odd context process (for example, cache control unit (# 1) 1) is switched to the even context process (for example, cache control unit (# 2) 1) and the even context value is written in the context register 3. This means that the space address has been rewritten.

FIG. 5 shows an operation explanatory diagram of the present invention. Figure 5
(A) shows an example of the context value / virtual address. Here, the context value is an 8-bit space address as shown in the figure.

The virtual address is composed of a high-order address (Region space, 8 bits) and a middle-order address (S
(egg space + Page space, 6 bits + 6 bits), and lower address (transition within Page, 12 bits).

FIG. 5B shows the context register /
An example of FF is shown. In the context register 3, the MSB to the LSB of the 8-bit context value sent to the data bus are written.

One bit of the LSB of the 8-bit context value is written to the FF4 here. This means that the cache control unit (# 1) 1 and the cache control unit (# 2) 1 are used and switched to either the even number or the odd number.

FIG. 6 is an explanatory view of the pseudo set associative system of the present invention. FIG. 6A shows a direct map. This means that when the cache control unit 1 is to be associated with the main memory, for example, the space 1 and is associated with the space 2, it is necessary to newly store the cache control unit 1. Then, when attempting to associate it with the original space 1, it is necessary to newly store the rewritten portion, which causes a problem that the cache hit rate decreases.

FIG. 6B shows a 2-way quasi-set associative system according to the present invention. Compared to the direct map of FIG. 6A, this is different from the cache control unit (# 1) 1 and the cache control unit (# 1).
2) By providing two of 1 and associating them with the space 1 and the space 2 as shown in the figure, the cache hit rate can be significantly improved. That is, when reading data from space 1, the cache control unit (#
The cache hit rate can be greatly improved by switching to 1) 1 and switching to the cache control unit (# 2) 1 when reading data from the space 2.

FIG. 7 shows an initialization flow chart of the present invention. This corresponds to the two cache control units (# 1) 1 and the cache control unit (#
2) The procedure for performing the initial setting for 1 will be described.

In FIG. 7, S11 sets "1" to FF. This sets "1" in the FF4 of FIGS. 1 and 2, and switches to the cache control unit (# 1) 1. In S12, the cache control unit (# 1) 1 is initialized (set to normal). These S11 and S12 are initialized (set to normal) with the FF 4 set to "1" and switched to the cache control unit (# 1) 1. As an initial setting, the control bit is cleared, the cache tag is cleared, the address translation is cleared, and the operation is set in the normal mode.

Similarly, in S13, 0 is set in FF. This sets "0" in the FF4 of FIGS. 1 and 2, and switches to the cache control unit (# 2) 1.
In S14, the cache control unit (# 2) 1 is initialized (set to normal). These S13 and S1
4 sets the FF 4 to "0" and switches to the cache control unit (# 2) 1 to perform initial setting (set to normal). As an initial setting, the control bit is cleared, the cache tag is cleared, the address translation is cleared, and the operation is set in the normal mode.

FIG. 8 shows an operation explanatory diagram of the present invention. This is the cache control unit (#
2) From the operating state in 1, the cache control unit (#
1) This is a procedure for switching to 1 and performing memory access by a virtual address.

In S21, the integer arithmetic unit 5 writes the context register 3 by a special instruction. This is because the integer arithmetic unit 5 uses the address modification instruction (ASI = 0x04), virtual address (VA = 0x0200), and write (* WE) of FIG. 3 as a special instruction to activate the data VD00 (the least significant bit of the data).
Is written to the context register 3 of the cache control unit (# 1) 1 for the first time. By this write operation, "1" is set in the FF4 and the cache control unit (# 1) 1 is switched to.

In S22, the integer arithmetic unit 5 writes the context register 3 by a special instruction. This is because the FF4 is set to "1" in S21 to switch to the cache control unit (# 1) 1 and the second context register 3 is written to the context control register 3 of the cache control unit (# 1) 1. Write the context value (space address).

In step S23, the numerical calculation unit 5 performs memory access using a virtual address. In this state, since the cache control unit (# 1) 1 has already been switched to and the context value (space address) has been set in the context register 3, it is determined whether the cache hit occurs in response to the access by the virtual address, and YES. In this case, cache data is sent from the cache memory (# 1) 6 to the data bus, and the numerical operation unit 5 takes in the data from the data bus.

As described above, the numerical operation unit 5 continuously writes the special instruction to the context register 3 twice, thereby completing the switching of the cache control unit 1 and the writing to the context register 3, and the access by the virtual address. On the other hand, it becomes possible to determine whether or not there is a cache hit, and the 2WAY pseudo-set associative system can be realized.

FIG. 9 shows a switching flow chart of the cache control unit of the used space according to the present invention. In FIG. 9, S31 determines whether task switching has occurred. In the case of YES, it is necessary to switch the spaces, so the process proceeds to S32. In the case of NO, there is no need to switch the space and the access is within the same space, so the process waits as it is.

S32 is a context register (# 1)
Rewrite 3 and set to FF4. This writes the context value for the first time, sets the LSB of the context value in FF4, and switches the cache control unit 1.

S33 is a context register (# 1)
Rewrite 3 and set to FF4. This is because the second writing of the context value is performed, and the context register (#
1) Write the context value to 3 and set the space address.

As described above, according to the present invention, the cache control unit 1 and the context register 3 are rewritten and the space is switched by writing the context value to the context register 3 and the FF 4 twice. As a result, the pseudo set associative method is realized.

[0059]

As described above, according to the present invention,
Since the cache control unit 1 is switched by switching the external FF 4 together with the switching of the context register 3 of the cache control unit 1 without using it in the multi-chip mode, the hit rate is set to the pseudo set associative method. Can be improved. As a result, a cache system based on a pseudo set associative system having a higher cache hit rate than the normal multi-chip mode can be realized only by adding a simple circuit such as FF4.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a specific example of the present invention.

FIG. 3 is a configuration example of an FF of the present invention.

FIG. 4 is an operation explanatory diagram when rewriting a context value according to the present invention.

FIG. 5 is an operation explanatory diagram of the present invention.

FIG. 6 is an explanatory diagram of a pseudo set associative method of the present invention.

FIG. 7 is an initial setting flowchart of the present invention.

FIG. 8 is an operation explanatory diagram of the present invention.

FIG. 9 is a flow chart of switching between the used space and the cache control unit of the present invention.

FIG. 10 is an explanatory diagram of a conventional technique.

FIG. 11 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: cache control unit 2: tag memory 3: context register 4: FF (flip-flop) 5: numerical operation unit 6: cache memory

Claims (3)

[Claims] 1. A cache control unit for controlling a cache, comprising a tag memory (2) for determining hit / miss of a cache memory (6) and a context register (3) for setting a space address. (1) and an FF (4) for connecting a plurality of cache control units (1) and setting a selection signal for selecting which one, and the rewriting signal of the context register (3) from the access request source. Corresponding to transmission, a value is set in the FF (4) to switch to the cache control unit (1) of the corresponding space, and the space address is set in the context register (3) of this cache control unit (1). , Searching the tag memory (2) of the cache control unit (1) in response to the subsequent access request A cache control circuit characterized in that data is sent from the cache memory (6) when a hit occurs. 2. The cache control unit (1) is 2n
When the number is n (n is a positive integer), n-bit FF (4) above
Is provided, and the n bits (for example, the lower n bits) of the address set in the context register (3) are FF
2. The cache control circuit according to claim 1, wherein the cache control circuit is configured to be set to (4) to switch the cache control unit (1). 3. The access request source sends the first space address, sets n bits in the FF (4), and switches the cache control unit (1) to a corresponding one.
3. The structure according to claim 1, wherein the same second space address is transmitted and the space address is set in the context register (3) of the cache control unit (1) that has been switched. The described cache control circuit.