JPH06149670A - Methods for controlling cache memory and conversion table - Google Patents

Abstract

PURPOSE:To improve the hit rate of a cache memory. CONSTITUTION:In a data processor provided with a cache memory 1 and a storage buffer 20 for temporarily storing data in order to purge a prescribed data block from the memory 1 to a main storage device 3 for instance, the data block purged to the buffer 20 are controlled so as to be entered into the memory 1 again in accordance with a new reference request (1). A purge buffer 21 for temporarily storing the data block purged from the memory 1 and not to be transferred to the device 3 is also prepared and controlled so that the data block purged to the buffer 21 after being registered in the memory 1 are entered into the memory 1 again in accordance with the request (1).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In recent years, for example, in microprocessors, various cache memories (instruction cache, data cache) and various buffers are used in order to avoid access to a main memory device in order to increase processing speed. , A table {store buffer, address translation buffer (TLB)} is generally provided.

However, in reality, there is a problem that these mechanisms are not fully utilized, and it is necessary to fully utilize these mechanisms and further increase the hit rate.

[0003]

2. Description of the Related Art FIG. 4 is a diagram for explaining a conventional cache memory control method. As is well known, the cache memory 1 includes a full associative system and a set associative system, and at present, a set associative system equipped with several sets is general.

In this set associative system,
A part of a certain address is defined as a tag, and the block data of the entry that matches it is registered in a predetermined line. If there is a request for a different address with the same tag, it is registered in the same different set.

Assuming a cache memory 1 having four sets as shown in FIG. 4, four different addresses having the same tag (addresses 1, 5, 9, 249 in FIG. 4). Can be cached at the same time.

In this state, when an access request is made to the fifth address 253, an address which has not been used recently among the four addresses, for example, the address 249.
Is selected and kicked out. This logic is called the LRU method.

If the block data of the address 249 has been previously accessed for store and its contents have been changed from the data block existing in the main memory at that time, the block data of the block Return the contents to the corresponding address area of the main memory and reflect the contents (match)
However, it is usually not reflected in the main memory immediately, and the above-mentioned LRU not shown is shown.
In the logic circuit, it is stored that the block data of the entry is the block data that has been accessed for store, and when the eviction request is made, the data that needs to be reflected in the main memory is held as a queue. It is temporarily stored in store buffer 20 for
Due to the temporary storage in the store buffer 20, the access request 253 is made to the empty cache memory entry.
The block data of is stored.

In this way, the data block 249
Thus, the block data of the fifth request address 253 is cached in the empty entry that has been evicted.

Writing to the store buffer 20
It is a FIFO (First In First Out) method, and when it is ejected from the write queue (store buffer) 20, it is written into the main storage device 3 for the first time.

While a certain block data is in the write queue (store buffer) 20, the central processing unit (CP
When U) 4 refers to the address of this block data (249), a faster data access is possible by referring to the write queue (store buffer) 20 after the miss hit of the cache memory 1. Has been realized.

[0011]

However, in such a conventional cache memory control method, once the write queue is
The block data flushed to (Store Buffer) is
When its write queue (store buffer) is full, it is flushed to main memory.

Therefore, even after it is found that there is a reference request from the central processing unit (CPU) 4, since the write queue (store buffer) 20 is of the FIFO type, it will eventually be evicted to the main storage unit 3. .

When the central processing unit (CPU) 4 refers to the address after the data is evicted to the main storage device 3, the main storage device 3 must be accessed and cached again. It will take time.

In view of the above-mentioned conventional drawbacks, the present invention focuses on the fact that the block data expelled from the cache memory is temporarily stored in the store buffer or the like, and is expelled and temporarily stored in the store buffer. An object of the present invention is to provide a cache memory control method capable of improving the hit rate of the cache memory by caching the block data again in the cache memory.

[0015]

FIG. 1 is a diagram for explaining the principle of the present invention. The above problems can be solved by the cache memory control method configured as follows.

(1) In a data processing device provided with a cache memory 1 and a store buffer 20 for temporarily storing a predetermined data block from the cache memory 1 to the main storage device 3, After being registered in 1, the data block evicted in the store buffer 20 above is
The control is again performed so that the cache memory 1 is loaded.

(2) The data processing device has a data block evicted from the cache memory 1 and not transferred to the main memory device 3, for example, there is no store access and it is not recently used, and the LRU logic is not used. Equipped with a flush buffer 21 for temporarily storing the block data to be flushed based on
After being registered in the cache memory 1, the data block flushed to the flush buffer 21 is controlled to be fetched again in the cache memory 1 in response to a new reference request.

(3) In a data processing device equipped with a predetermined conversion table, the conversion table expelled from the conversion table is temporarily stored, a store buffer, or
With the eviction buffer, once registered in the conversion table, the store buffer or the eviction buffer converted data is fetched into the conversion table again in response to a new reference request. Control.

[0019]

That is, in the present invention, in order to solve the above-mentioned problems, when the central processing unit (CPU) issues a new reference request to block data in the write queue (store buffer), , Take a control method of caching in the cache memory.

A mechanism for explaining the principle of the present invention will be described with reference to FIG. Here, the cache memory is 4
If there is a request to register an entry that has two sets and is full, and has the same tag, the well-known L
It is premised that replacement is caused by RU (Least Recently Used) logic.

From a central processing unit (CPU) (not shown), for example, addresses 249, 1, 5, and 5 in the main storage device.
In the order of 9, the block data of each address is referred to, the block data of the address 249 is accessed for writing, and the block data of the address 249 is stored in an LRU logic circuit (not shown). ,
When there is an access to the address 253 and there is a mishit, the LRU logic causes the block data of the address 249 to be ejected as the least recently used block and queued in the store buffer 20. The state of the cache memory is shown in FIG. 1 with lines 10a and 10b of the cache memory and the store buffer 2
It is expressed as 0.

The block data 249 depends on the number of entries in the write buffer, but is eventually ejected.
Destined to be written to main memory. In this state, when the central processing unit (CPU) refers to the block data 249, it once searches the cache memory 1 and confirms a miss hit.

At this time, when it is confirmed that all the sets are in use (eg, the valid bit of each entry is "on"), the LRU logic determines the number of the entry to be replaced next (in this example, " 2 ″) is stored in the replace register 11, for example.

In the conventional technique, this LRU logic worked only when caching new block data from the main storage device into the cache memory. However, the above logic {replacement register 11 stores the number of the next replacement entry. Introducing the logic to perform a mistake hit at the time when the above-mentioned miss hit is confirmed, the replacement process in the caching process that occurs later becomes simple.

When a cache miss occurs, the write queue (store buffer) 20 is searched next, but when the address of the target block data is found here (in the past, this data is transmitted to the main storage device). Was only)
In the present invention, the replacement register 11
The contents of the entry stored in
(Store buffer) Operates to replace (replace) the target block data stored in 20.

In the above example, the block data expelled to the write queue (store buffer) is cached again in the cache memory when the next central processing unit (CPU) refers to it. Not the block data that was written, not recently used,
In the LRU logic, block data to be evicted from the cache memory is stored in, for example, an evacuation buffer having a queue structure, and a new reference from the central processing unit (CPU) causes a miss hit, and the evicting is performed. When the target block data is detected by searching the buffer, it is temporarily stored in the eviction buffer,
It goes without saying that the target block data may be cached in the cache memory again.

Although the above description has been made by taking a cache memory as an example, it is obvious that the present invention can be applied to a storage buffer such as a translation table found in an address translation buffer (TLB).

Therefore, the central processing unit (CPU) is re-cached by re-caching the block data of the address which becomes unnecessary in a certain period of time and is flushed from the cache memory.
It is possible to obtain a high-speed response to an access request from the device and improve the hit rate.

[0029]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 described above is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram schematically showing an embodiment of the present invention, and FIG.
It is the figure which showed one Example of this invention with the flowchart.

In the present invention, the cache memory 1
And a store buffer 20 for temporarily storing a predetermined data block from the cache memory 1 to the main memory device 3, the data processing device is temporarily stored in the cache memory 1 and then stored. The data block evicted in the buffer 20 is controlled to be fetched again in the cache memory 1 in response to a new reference request. Further, it is equipped with a eviction buffer 21 for temporarily storing a data block that is evicted from the cache memory 1 and is not returned to the main memory device 3. A means for controlling the data block to be fetched again in the cache memory 1 in response to a new reference request is a means necessary for implementing the present invention. The same reference numerals indicate the same objects throughout the drawings.

The cache memory control method of the present invention will be described below with reference to FIGS. 2 and 3 with reference to FIG. In FIG. 2, 4 is a central processing unit (CPU), 15 is a cache memory 1, and a comparator that retrieves target block data from a store buffer 20, 1 is the cache memory, 20 is the store buffer, and 11 is the store buffer. , A register that stores the entry number of the replacement destination of the cache memory 1 (called a replace register), and 3 is a main memory device.

The replace register 11 has a cache entry number (for each line of the cache memory shown in FIG. 4, addresses 1, 2 ,. ． 256 means the address of the stored entry, which can be translated into the entry address of the cache memory. )
To store.

1) As shown in FIG. 1, the central processing unit (CPU) 4 already has addresses 249, 1,
I will begin the discussion by accessing 5, 9, and 253 in order. At this point, as explained in the prior art section,
The block data at the address 249 has been pushed out to the write queue (store buffer) 20.

2) When the central processing unit (CPU) 4 of FIG. 2 again refers to the address 249, the comparator 15 of FIG. 2 first searches the cache memory 1. At this time, if an empty entry is detected at the same time,
Register the entry number in the replace register 11 above.

If there is no empty space, the LRU logic determines the entry number to be ejected next, and similarly registers it in the replace register 11. {Processing steps 100,1 in FIG. 3
When the block data of the target address 249 is found in the cache memory 1, the central processing unit (CPU) 4 is notified and the processing is terminated. {Processing steps 100 and 104 in FIG.
Reference} 3) If the target block data of the address 249 is not found in the cache memory 1, the write buffer (store buffer) 20 is continuously searched. {Refer to processing step 102 in FIG. 3} 4) If the block data of the target address 249 is not found in the write buffer (store buffer) 20, the block data of the target address is read from the main memory 3, The entry in the cache memory 1 pointed to by the replace register 11 is evicted to, for example, the write buffer (store buffer) 20 {if the block data in the entry is the LRU logic,
If it is not stored that the block data has been rewritten, it is not necessary to flush it to the write buffer}.
Register in the cache memory 1 and finish the process.

5) Write buffer (store buffer)
If the block data of the target address is found in 20, the entry data in the cache memory 1 pointed to by the replace register 11 and the entry data in the write buffer (store buffer) 20 are replaced in the present invention ( Replace). {Refer to processing step 103 in FIG. 3} 6) In the processing of 2) above, the replace register 11
In the present invention, when the block data of the entry registered in is not rewritten from the central processing unit (CPU) 1 and it is not stored in the LRU logic as the rewritten block data, Instead of using the write buffer (store buffer) 20 described above, the data is evicted and stored in the ejection buffer 21.

7) Then, the block data of the address referred to by the access from the central processing unit (CPU) 4 is
When it is detected that the cache memory 1 does not exist (that is, a mishit) and is stored in the eviction buffer 21, it is re-executed in the same manner as the case of the write buffer (store buffer) 20. By replacing the entry data in the cache memory 1 pointed to by the replace register 11 with the entry data in the eviction buffer 21, the same effect as that of the write buffer (store buffer) 20 can be obtained.

In the above embodiment, the central processing unit (CP
U) When there is an access request from 4, the tag memory (not shown) in the cache memory is searched, and when a free entry is found due to a mishit, or when there is no free space, the LRU logic described above , When an entry in which the least used block data is cached is detected, the entry number is registered in the replace register 11 and is actually replaced with the move-in block data from the main memory 3. At this time, an example in which the replacement process is simply performed by replacing the entry registered in the replacement register 11 has been described, but the present invention is not limited to this, and as is well known, the main storage device 3 is actually used. When a move-in request is issued to the main memory device, the replace entry is detected and
It goes without saying that it may be the method of replacing the block data moved in from 3 (that is, the method without the replace register 11).

In this embodiment, the cache memory is cited, but in addition, for example, the address translation buffer (T
It is also applicable to the storage buffer of the conversion table found in LB).

In this case, for example, in a data processing device having an address translation buffer (TLB), the address translation data expelled from the address translation buffer (TLB) is temporarily stored, a store buffer, or With the eviction buffer, once the address translation buffer is registered, the conversion data evicted in the store buffer or the eviction buffer is fetched again in the address translation buffer in response to a new reference request. Will be controlled.

As described above, according to the present invention, the cache is temporarily stored in the data processor provided with the cache memory and the store buffer for temporarily storing a predetermined data block from the cache memory to the main memory. After the data block is registered in the memory, the data block flushed to the store buffer is controlled to be fetched again in the cache memory in response to a new reference request. In addition, a data buffer that is temporarily stored in the cache memory and that is not stored in the main memory is stored in the cache memory. It is characterized in that it is controlled so that the cache memory is loaded again in response to such a reference request.

[0042]

As described above in detail, according to the cache memory control method of the present invention, for example, even when the number of accesses to the same tag and different addresses exceeds the number of mounted sets, the write buffer, Alternatively, by enabling re-registration from the eviction buffer, the hit rate of the cache memory can be increased.

Further, as described above, the address translation buffer
By using the configuration of the present invention even for the conversion data temporarily displaced from the conversion table such as (TLB), the hit rate in the address conversion buffer (TLB) can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a diagram schematically showing an embodiment of the present invention.

FIG. 3 is a flowchart showing an embodiment of the present invention.

FIG. 4 is a diagram illustrating a conventional cache memory control method.

[Explanation of symbols]

1 cache memory 10a, 10b each line of cache memory 20 store buffer (write queue) 21 eviction buffer 3 main memory 4 central processing unit (CPU) reference request from central processing unit (CPU) 100 to 105 processing steps

Claims (3)

[Claims] 1. Data processing comprising: a cache memory (1); and a store buffer (20) for temporarily storing a predetermined data block from the cache memory (1) to a main storage device (3). In the device, the data block that was once registered in the cache memory (1) and then ejected to the store buffer (20) is re-registered in the cache memory in response to a new reference request ().
A method for controlling a cache memory, characterized in that the control is performed so as to be taken into (1). 2. A eviction buffer (21) for temporarily storing, in the data processing device, a data block that is evicted from the cache memory (1) and is not transferred to the main memory (3).
The data block that has been ejected to the evicting buffer (21) after being registered in the cache memory (1),
According to a new reference request (), the cache memory control method is characterized in that the cache memory (1) is controlled to be fetched again. 3. A data processing device provided with a predetermined conversion table, which is provided with a store buffer or an eviction buffer for temporarily storing the conversion table expelled from the conversion table. A conversion table control method, characterized in that the conversion data, which has been registered and then has been evicted in the evacuation buffer, is controlled so as to be fetched again in the conversion table in response to a new reference request.