JPH06149188A - Output buffer circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To shorten a time for sampling data in a liquid crystal display device and to reduce power consumption in an output buffer circuit in a data driver in an active matrix liquid crystal display device. CONSTITUTION:This output buffer circuit in the active matrix liquid crystal display device is provided with an input part 1 consisting of a differential amplifier circuit, an output part 2 operating by an output from the input part 1, bias voltage selection parts 4, 5 selecting a bias voltage supplied to the output part 2 and a phase compensation part 3 for compensating the phase, and is constituted so that a current flows through the output part 2 by the bias voltage selection parts 4, 5 when no output buffer circuit is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of a liquid crystal display device, and more particularly to an output buffer circuit of a data driver in an active matrix type liquid crystal display device. In recent years, active matrix liquid crystal display devices have been
Because of its small size, light weight, and low power consumption, it has become widespread as a pocket TV, and is also expected as a display device for information terminals such as laptop and notebook personal computers (personal computers) and word processors. . In particular, laptop computers are excellent in portability and are desired to be used for a long time with a battery. Therefore, even lower power consumption is demanded for output buffer circuits of liquid crystal display devices. .

[0002]

2. Description of the Related Art FIG. 6 is a block circuit diagram showing a data driver unit of a conventional liquid crystal display device, which is an example of an analog data driver for driving a data bus of a liquid crystal panel by inputting image data of analog signals and respective control signals. Is shown. In FIG. 6, reference numeral 100 is a liquid crystal panel, 101 is a shift register, 102 and 104 are sampling and holding circuits, 103 and 105 are output buffers, and 106 is a gate driver.

The liquid crystal panel 100 includes a plurality of liquid crystal cells in a matrix, and each liquid crystal cell is a thin film transistor (TF).
Write control is performed according to T).
The shift register 101 is composed of a plurality of flip-flops, and analog signals (R, G,
B) is controlled to which position of one horizontal scanning line (one scanning line) of the sampling and holding circuit 102 is sampled. That is, the sampling and holding circuit 10
2 indicates that the image data of the analog signal input serially is controlled by the output of the shift register 101 to control the analog switch, and the image data for one scanning line is aligned and the image data is output in parallel. Has become.

The output buffer 103 comprises a plurality of differential amplifier circuits (op amps: output buffer circuits) OPo, and outputs the image data for one scanning line held in the sampling and holding circuit 102 by the voltage follower of the op amps OPo. Is. Sampling and holding circuit 104
Is provided with a plurality of capacitors Co and analog switches So, and controls each analog switch So by a signal from the outside to sample and hold image data input in parallel from the sampling and holding circuit 102.

The output buffer 105 includes a plurality of differential amplifier circuits (op amps: output buffer circuits) OPoo, and the image data for one scanning line held in the sampling hold circuit 104 is supplied to the liquid crystal panel 100 by the voltage follower of the op amp OPoo. The data is output to the data bus (data electrode). Here, the reference symbol C _H indicates the capacity of, for example, a data bus connected to the output of the output buffer circuit OPoo.

As described above, the data driver of the liquid crystal display device shown in FIG. 6 converts the serially input analog signals (image data) R, G, B into parallel output signals for one scanning line. First sampling and holding circuit
The data is output from 102 to the second sampling and holding circuit 104 via the first output buffer 103 at once. Here, while the image data input by the control of the analog switch by the first sampling and holding circuit 102 is sampled and held to align the image data for one scanning line, the second sampling and holding circuit 104 is It holds the previous image data,
The voltage is supplied to the liquid crystal panel via the second output buffer 105.
It is designed to supply 100.

Here, the gate driver 106 sequentially selects the gate buses (scan electrodes) of the liquid crystal panel 100, turns on the TFTs connected to the buses (conducts),
Data for one scanning line supplied through the output buffer 105 is sequentially written into the liquid crystal cells for one scanning line of the selected gate bus. FIG. 7 is a circuit diagram showing an example of an output buffer circuit of a conventional liquid crystal display device, showing the output buffer circuits (differential amplifier circuits OPo, OPoo) in the output buffers 103 and 105 shown in FIG. In FIG. 7, reference numeral 1 is an input section, 2 is an output section, 30 is a phase compensation section, and 40 and 6 are bias voltage supply sections.

As shown in FIG. 7, the input section 1 is composed of a differential amplifier circuit having P-channel type MOS transistors T2, T3 and N-channel type MOS transistors T4, T5 and a P-channel type MOS transistor T1.
The gate of the transistor T1 has a P-channel type MOS
The output of the bias voltage supply unit 6 including the transistor T61 and the resistor R61 is supplied. As a result, the transistor T1 is always in the ON state, and a predetermined current always flows in the input section 1.

The output section 2 has a P-channel type MOS transistor T6 and an N-channel type MOS transistor T7, and amplifies the voltage change of the output of the input section 1. The output of the bias voltage supply section 40 constituted by a P-channel type MOS transistor T44 and a resistor R42 is supplied to the gate of the transistor T6. As a result, the transistor T6 is always turned on, and the output unit 2
In, the predetermined current always flows. Here, the input section 1 is connected to the gate of the transistor T7.
Output is being supplied. The phase compensator 30 is composed of a capacitor C _F and a resistor R _F , and is for suppressing the oscillation by the input unit 1 and the output unit 2 to perform the phase compensation.

[0010]

In the conventional output buffer circuit of the liquid crystal display device, for example, the first buffer shown in FIG.
When it is used as the output buffer circuit (differential amplifier circuit OPo) of the output buffer 103, the analog switch So is turned on in order to charge and discharge the capacitance Co via the analog switch So in the second sampling and holding circuit 104. The time constant due to the capacitance value of the resistance and the capacitance Co prevents the reduction of the sampling time. Further, for example, when it is used as the output buffer circuit (differential amplifier circuit OPoo) of the second output buffer 105 in FIG. 6, there is an effect due to the capacitance C _H of the data bus or the like. Furthermore, the use time of the first output buffer 103 is intermittent, and even if the output operation is unnecessary, a predetermined power is always consumed. Similarly, the second output buffer 10
As for 5, even if the distributed capacitance parasitically present in the data bus ends, there will be almost no current flow between the output buffer 105 and the data bus, resulting in wasted power consumption. .

In view of the problems of the output buffer circuit of the conventional liquid crystal display device described above, it is an object of the present invention to reduce the data sampling time and the power consumption in the liquid crystal display device.

[0012]

FIG. 1 is a diagram showing the principle of a first mode of an output buffer circuit of a liquid crystal display device according to the present invention. According to the first aspect of the present invention, there is provided an output buffer circuit of an active matrix liquid crystal display device, the input unit 1 constituting a differential amplifier circuit, and the input unit 1.
And an output section 2 which operates by an output from a bias voltage selection section 4 which selects a bias voltage to be supplied to the output section 2.
5 and a phase compensating unit 3 which is connected between the input and output of the output unit 2 and performs phase compensation. When the output buffer circuit is not used, the bias voltage selecting units 4 and 5 are used to switch the output unit 2 from the output unit 2. There is provided an output buffer circuit of a liquid crystal display device, which is characterized in that a flowing current is stopped.

FIG. 2 is a diagram showing the principle of the second mode of the output buffer circuit of the liquid crystal display device according to the present invention.
According to the second aspect of the present invention, with respect to the output buffer circuit of the liquid crystal display device of the first aspect, a third bias voltage selecting section 60 for selecting a bias voltage to be supplied to the input section 1 is further provided. And a third bias voltage selection unit
An output buffer circuit 60 of a liquid crystal display device is provided, wherein 60 is configured to stop the current flowing through the input section 1 when the output buffer circuit is not used.

[0014]

As shown in FIG. 1, according to the first embodiment of the semiconductor device of the present invention, the gates of the P-channel type MOS transistor T6 and the N-channel type MOS transistor T7 constituting the output section 2 have the first gate. And the outputs of the second bias selectors 4 and 5 are supplied to the first control signal OE1.
The switching of the transistors T6 and T7 of the output section 2 is controlled according to the second control signal OE2. When the output buffer circuit is not used, the transistors T6 and T7 of the output section 2 are turned off, so that the current flowing through the output section 2 is stopped. That is, the power consumption of the output section 2 as a whole can be reduced by turning on the transistors T6 and T7 of the output section 2 only when the output buffer circuit is used.

Further, the phase compensating section 3 is composed of a capacitance means C _F and a switching means S _F which are connected in series, and the switching means S _F is switched on immediately before the output section 2 is brought into the operating state, and the output section 2 is output. Is switched off immediately before it becomes inactive, which eliminates the need for an analog switch provided between the output buffer circuit and the capacitance of the output destination, and enables high-speed sampling. You can

As shown in FIG. 2, according to the second embodiment of the semiconductor device of the present invention, the third bias voltage selecting section 60 is provided.
By selecting the bias voltage to be supplied to the input unit 1 by means of the above, by stopping the current flowing through the input unit 1 when the output buffer circuit is not used, it is possible to further reduce power consumption.

[0017]

Embodiments of the output buffer circuit of a liquid crystal display device according to the present invention will be described below with reference to the drawings. FIG. 3 is a circuit diagram showing an embodiment of the first mode of the output buffer circuit of the liquid crystal display device according to the present invention and corresponds to the conventional output buffer circuit (differential amplifier circuit) shown in FIG. FIG. 5 is a waveform diagram for explaining the operation of the output buffer circuit of the liquid crystal display device of FIGS. 3 and 4.

In FIG. 3, reference numeral 1 is an input section and 2 is an input section.
Output section, 3 is phase compensation section, 4 and 5 are bias voltage selection
The selection unit and 6 indicate the bias voltage supply unit.
Here, the reference symbol Co is the sampling and holding circuit 104.
Capacity of C_HIs the capacity of the data bus, etc.
Shows. That is, the capacity Co is the output buffer times
6, the operational amplifier of the first output buffer 103 in FIG.
When used as OPo, the output of the operational amplifier OPo
It corresponds to the capacity connected to the input end, and also has a capacity C _HIs a book
The output buffer circuit is the second output buffer 10 in FIG.
When used as an operational amplifier OPoo of 5
The capacity of the data bus connected to the output terminal of the pump OPoo.
It corresponds. In addition, the input section 1, the output section 2, and the
The ass voltage supply unit 6 is a conventional output buffer circuit shown in FIG.
It is similar to the structure in the road. Also, this output buffer times
6, the operational amplifier of the first output buffer 103 in FIG.
When used as OPo, the second sampling
The analog switch So in the field circuit 104 is unnecessary.
Become.

Further, in FIG. 5, reference numeral HS indicates a horizontal synchronizing signal, SI indicates an input signal of the shift register, CLK indicates a clock signal, and R, G, B indicate image data.
The input signal SI of the shift register is supplied to the data input of the D-flip-flop of the first stage of the shift register 101 shown in FIG. 6, and the control signal corresponding to the clock signal CLK is supplied to the analog switch of the first sampling and holding circuit 102. Is supplied, and the image data R, G, B are sequentially sampled and held. Further, reference symbols OE1, OE2, OE3, OE4 indicate first to fourth control signals, respectively.

As shown in FIG. 3, the input section 1 is composed of a differential amplifier circuit having P-channel type MOS transistors T2, T3 and N-channel type MOS transistors T4, T5 and a P-channel type MOS transistor T1.
The gate of the transistor T1 has a P-channel type MOS
The output of the bias voltage supply unit 6 including the transistor T61 and the resistor R61 is supplied.

The output section 2 has a P-channel type MOS transistor T6 and an N-channel type MOS transistor T7, the output of the first bias voltage selecting section 4 is supplied to the gate of the transistor T6, and the transistor T7.
The output of the second bias voltage selection unit 5 is supplied to the gate of the. The first bias voltage selector 4 includes P-channel MOS transistors T41, T42, T43 and a resistor R.
41, the true signal (first control signal) OE1 of the first control signal is supplied to the gate of the transistor T43, and the complementary signal / OE1 of the first control signal is supplied to the gate of the transistor T42. Is being supplied. Then, the first control signal OE
When 1 is high level "H", transistors T43 and T43
41 is turned off and the transistor T42 is turned on. A high potential bias voltage is applied to the gate of the transistor T6 of the output section 2, and the transistor T6 is turned off. On the contrary, when the first control signal OE1 is at the low level "L", the transistors T43 and T41 are turned on and the transistor T42 is turned off, so that the low potential bias voltage is applied to the transistor T of the output section 2.
Applied to the gate of 6, the transistor T6 turns on. In this way, the first bias voltage selection unit 4 applies the bias voltage selected according to the first control signals OE1, / OE1 to the gate of the transistor T6 to control the switching of the transistor T6. Has become.

The second bias voltage selector 5 is composed of an N-channel type MOS transistor T51, and the gate of the transistor T51 is supplied with the second control signal OE2. Then, when the second control signal OE2 is at the high level "H", the transistor T51 is turned on, a low potential bias voltage is applied to the gate of the transistor T7 of the output section 2, and the transistor T7 is turned off. On the contrary, when the second control signal OE2 is low level "L", the transistor T51
Is turned off, and a high potential bias voltage is applied to the gate of the transistor T7 of the output section 2,
7 is on. In this way, the second bias voltage selector 5 applies the bias voltage selected according to the second control signal OE2 to the gate of the transistor T7 to control the switching of the transistor T7. .

Here, as shown in FIG. 5, the first control signal OE1 and the second control signal OE2 are designed to change at the same timing, and the first and second control signals OE1, OE1, When both OE2 are at high level "H", the transistors T6 and T7 are turned off and the output buffer circuit (op amp) becomes inactive, and conversely, both the first and second control signals OE1 and OE2 are at low level. When it is "L", the transistors T6 and T7 are turned on and the output buffer circuit (op amp) is in the operating state.

The phase compensator 3 has a capacity C _F connected in series.
And N-channel MOS transistors T31 and T32, the gate of the transistor T31 is supplied with the true signal (third control signal) OE3 of the third control signal, and the gate of the transistor T32 is supplied with the third signal. Complementary control signal / OE3
Is being supplied. Then, when the third control signal OE3 is at the high level "H", the transistor T31 is turned on to supply the output from the input section 1 to the output section 2. Here, the on-resistance of the transistor T31 has the same role as the resistance R _F of the phase compensation unit 30 of the conventional output buffer circuit shown in FIG. 7, and suppresses the oscillation by the input unit 1 and the output unit 2 together with the capacitor C _F. It is designed to perform phase compensation. Although the transistor T32 whose gate is supplied with the complementary signal / OE3 of the third control signal is not directly related to the circuit operation, the transistor T31 whose gate is supplied with the positive signal OE3 of the third control signal is used. This is for ensuring the operation by matching with. That is, the gate width of the operation compensating transistor T32 is formed to be half the gate width of the switching transistor T31.
The effect of the parasitic capacitance between the sources or between the gate and the drain is canceled by the operation compensating transistor T32 to compensate the switching operation.

Here, as shown in FIG. 5, the timing at which the third control signal OE3 changes is such that the first and second control signals OE1 and OE2 change from the high level "H" to the low level "L".
Just before changing to low level "L" to high level "H", and just before the first and second control signals OE1 and OE2 change from low level "L" to high level "H". The high level “H” changes to the low level “L”. That is,
The transistor T31 in the phase compensation unit 3 is switched on immediately before the output unit 2 is in the operating state and is switched off immediately before the output unit 2 is in the non-operating state. As a result, the capacitance Co (C
_The voltage is applied (written) to _H ) without waste, and the electric charge accumulated (written) in the capacitance Co (C _H ) is prevented from being discharged. When this output buffer circuit is used as the operational amplifier OPo of the first output buffer 103 in FIG. 6, the operational amplifier OPo itself functions as a switch, and therefore the analog switch So in the second sampling and holding circuit 104 is used.
Can be eliminated to enable high speed operation.

FIG. 4 is a circuit diagram showing an embodiment of a second mode of the output buffer circuit of the liquid crystal display device according to the present invention, and FIG. 5 is a circuit diagram of the output buffer circuit of the liquid crystal display device of FIGS. 3 and 4. It is a waveform diagram for explaining the operation. In the output buffer circuit shown in FIG. 4, the bias voltage supply unit 6 in the output buffer circuit shown in FIG. 3 is configured as a third bias voltage selection unit 60 having the same configuration as the first bias voltage selection unit 4. The other configuration is the same as that of the output buffer circuit shown in FIG.

As shown in FIG. 4, the third bias voltage selector 60 includes a P-channel MOS transistor T62,
A transistor T composed of T63, T64 and a resistor R62.
The true signal (fourth control signal) OE4 of the fourth control signal is supplied to the gate of 64, and the complementary signal / OE4 of the fourth control signal is supplied to the gate of the transistor T63. When the fourth control signal OE4 is at the high level "H", the transistors T64 and T62 are off and the transistor T63 is on, and a high potential bias voltage is applied to the gate of the transistor T1 of the input section 1, The transistor T1 is turned off. On the contrary, when the fourth control signal OE4 is at the low level "L", the transistors T64 and T62 are turned on and the transistor T63 is turned off, and the low potential bias voltage is applied to the gate of the transistor T1 of the input section 1, The transistor T1 is turned on. As described above, the third bias voltage selection unit 60 applies the bias voltage selected according to the fourth control signals OE4 and / OE4 to the gate of the transistor T1 to control the switching of the transistor T1. Has become.

Here, as shown in FIG. 5, the fourth control signal OE4 changes at the same timing as the change of the first and second control signals OE1 and OE2, and the output section 2 In the non-operating state, the input unit 1 is also set in the non-operating state, so that the power consumption of the input unit 1 is also reduced. As described above, according to the first mode of the output buffer circuit of the liquid crystal display device according to the present invention, the bias voltage of the transistors T6 and T7 is selected while the operation of the operational amplifier is unnecessary, so that the source electrodes of the respective transistors are not changed. The output terminal of the operational amplifier can have a high impedance by setting the non-conduction state between the drain electrode and the drain electrode, and setting the analog switch of the phase compensation circuit in the non-conduction state. Further, for example, when the present output buffer circuit is used as the operational amplifier OPo of the first output buffer 103 in FIG. 6, the operational amplifier OPo itself functions as a switch, and therefore the analog switch So in the second sampling and holding circuit 104 is provided. Capacity Co
It is possible to control charging and discharging of electric charges to and from the storage of electric charges. As a result, power saving of the output buffer circuit and high speed sampling can be achieved.

According to the second aspect of the output buffer circuit of the liquid crystal display device of the present invention, in the state where the output end of the output buffer circuit has a high impedance, wasteful power consumption in the input section is eliminated, and It is possible to further reduce power consumption.

[0030]

As described above in detail, according to the first embodiment of the output buffer circuit of the liquid crystal display device of the present invention, the current flowing through the output section is stopped when the output buffer circuit is not used. Therefore, the power consumption as a whole can be reduced. Further, by configuring the phase compensating section with the capacitance means and the switching means connected in series, the output terminal can have a high impedance, and the analog switch provided between the output buffer circuit and the output destination capacitance can be eliminated. Moreover, sampling can be performed at high speed. Further, according to the second aspect of the output buffer circuit of the liquid crystal display device of the present invention, when the output buffer circuit is not used, the current flowing through the input section is stopped, thereby further reducing the power consumption. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a principle of a first mode in an output buffer circuit of a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing a principle of a second mode of the output buffer circuit of the liquid crystal display device according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment of the first mode of the output buffer circuit of the liquid crystal display device according to the present invention.

FIG. 4 is a circuit diagram showing an embodiment of a second mode of the output buffer circuit of the liquid crystal display device according to the present invention.

5 is a waveform diagram for explaining the operation of the output buffer circuit of the liquid crystal display device of FIGS. 3 and 4. FIG.

FIG. 6 is a block circuit diagram showing a data driver unit of a conventional liquid crystal display device.

FIG. 7 is a circuit diagram showing an example of an output buffer circuit of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input part 2 ... Output part 3 ... Phase compensation part 4 ... 1st bias voltage selection part 5 ... 2nd bias voltage selection part 6 ... Bias voltage supply part 60 ... 3rd bias voltage selection part OE1, / OE1 ... first control signal OE2 ... second control signal OE3, / OE3 ... third control signal OE4, / OE4 ... fourth control signal

Front page continuation (72) Inventor Kenichi Nakabayashi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (4)

[Claims] 1. An output buffer circuit for an active matrix liquid crystal display device, comprising: an input section (1) constituting a differential amplifier circuit; and an output section (2) operated by an output from the input section (1).
A bias voltage selection section (4, 5) for selecting a bias voltage to be supplied to the output section (2), and a phase compensation section (3) connected between the input and output of the output section (2) for phase compensation. ) And when the output buffer circuit is not used, the bias voltage selection section (4, 5)
The output buffer circuit of the liquid crystal display device is characterized in that the current flowing through the output section (2) is stopped by the above. 2. The output section (2) is a P channel type MO.
A first bias voltage selecting unit (4) comprising an S transistor (T6) and an N channel type MOS transistor (T7), and the bias voltage selecting unit controls switching of the P channel type MOS transistor (T6). ) And a second bias voltage selection unit (5) for controlling switching of the N-channel type MOS transistor (T7), the output buffer circuit of the liquid crystal display device according to claim 1. 3. The output buffer circuit of the liquid crystal display device further comprises a third bias voltage selection section (60) for selecting a bias voltage to be supplied to the input section (1),
3. The liquid crystal display device according to claim 2, wherein the third bias voltage selection unit (60) stops the current flowing through the input unit (1) when the output buffer circuit is not used. Output buffer circuit. Wherein said phase compensating unit (3) comprises a series connected capacitance means (C _F) and a switch means (S _F), connecting the input portion (1) and said output unit (2) The switch means (S _F ) for controlling the output means (2)
2. The output buffer circuit of the liquid crystal display device according to claim 1, wherein the switch is turned on immediately before the operation state is turned on, and the switch is turned off immediately before the output section (2) is turned off.