JPH0614638B2 - A mechanism for resynchronizing the local clock signal and the received data signal - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positioning device for a transition point of a data signal with respect to a leading edge of a local clock signal which is synchronized or almost synchronized with a data signal transmitted in a numerical format. In particular, the invention provides a chaotic phase relationship to the initial clock signal in order to enable the data to be collected by sampling in a very short period of time in the middle of the period in which the data is present. It can be used in a mechanism to match the local clock signal to the data signal shown.

[Conventional technology]

Many devices which fulfill the above-mentioned functions are already known. This device generally uses means for outputting several signals delayed by a predetermined time from one of the input signals (data signal and clock signal) and means for comparing the instants at which the transition points of different signals appear. In particular, the documents EP-A-21,94
2 describes a periodic device of a data transmission system of the limited length sequence (continuous signal) type, each having an identifiable header. (Synchronization (phase matching)
Is performed on a substantially synchronized local clock signal. Due to the limited length of the sequence, very large drifts are avoided by the phasing performed only once at the beginning of each sequence.

[Problems to be Solved by the Invention]

It is an object of the present invention to provide a device for detecting a transition point of a data signal currently being received, which device is used for all numerical signals.

[Means for Solving the Problems]

Thus, the present invention provides a mechanism for resynchronizing a local clock signal and a received data signal having at least three flip-flops, a delay circuit, and a device having a logic circuit and an additional delay circuit. Each of the flip-flops
The delay circuit has a clock input terminal for inputting a local clock signal and a data input terminal for inputting a data signal with different time delays with respect to the local clock signal, and the delay circuit has a sum of the different time delays equal to or less than a clock cycle. Set the different time delays to the values so selected. The logic circuit is coupled to the output terminal of the flip-flop and is designed to generate a control signal representing a phase relationship between the clock signal and the data signal according to a predetermined standard, the control signal being
When all the flip-flops output the same signal in the first state showing correct position synchronization, or when the logic signals output from the first and second flip-flops show inconsistency, the local clock data In the first
The second state indicating phase asynchronism in the direction of, or when the logic signals output from the second and third flip-flops indicate dissimilarity, the second state between the local clock and the data,
In the third state, which represents phase asynchronization in the direction of.

An additional delay circuit (16 or 24, 26) produces an adjustable additional time delay between the local clock signal and all the data signals applied to the flip-flops, the control signal being the first Is controlled by the control signal in order to hold the state of.

The time delay can be generated by sampling the data signal at several successive positions of the delay circuit. However, although it is a somewhat complicated method, equivalent results can be reached by processing the clock signal rather than the data signal to achieve a time delay.

The mechanism thus proposed makes it possible to adjust the time of sampling of the data signal by means of the clock signal and to take that time as far as possible from the data transition point by means of suitable control. In this way any uncertainty in sampling is avoided and useful information is available at the output of the central flip-flop. First of the present invention
In this embodiment, it is assumed that the data signal and the sampling signal are mutually synchronized. In this case,
Correct phasing between these signals can be obtained by controlling the delay line. In a second embodiment,
The data signal and the clock signal are substantially synchronized with each other. In this case, control acts through the control of the frequency of the clock generator so that the average phase change of the clock signal and the phase change of the data signal match. Hereinafter, these two methods will be sequentially described.

The invention will be further clarified by reading the following description of specific embodiments described as non-limiting illustrations. The description is made with reference to the accompanying drawings.

〔Example〕

Before describing the various embodiments of the device of the present invention, when the phase relationship between the data signal and the clock signal is not predetermined, it is specified by the leading edge of the clock signal which is synchronous or nearly synchronous with the data signal. It is useful to recall the conditions necessary to collect numerical data by sampling at different times.

In order to guarantee the required acquisition reliability for the data signal D _{0 of} period T, the sampling has to be done in the effective range of 2v, which is located in the middle of the period in which the pulse is present (FIG. 2). Since the clock signal H ₀ has an arbitrary phase with respect to the data signal D ₀ , by shifting one phase of the signal, for example, by shifting the phase of the clock signal so that the clock signal moves to Hv, The leading edge of the clock must be moved and maintained within a 2v length.

The principle embodied by the invention is that at least two signals phase-shifted by + δ and -δ with respect to the clock signal H ₀ . And generating respectively. However, δ ≦ T (FIG. 3). In fact, this is the same even if the other two signals D ₁ and D ₂ that are phase-shifted by δ and 2δ with respect to the data signal are generated (FIG. 4).

The basic construction of the phase determining device is shown in FIG. 1, which comprises at least three flip-flops 10, 12, 1
It is equipped with 4. Each flip-flop inputs the clock signal H at the clock input, and also inputs the data signal having a different time delay for each flip-flop with respect to the clock signal. The delay time is determined by the delay circuits 18 and 20. Therefore, in FIG. 1, two signals D ₁ and D ₂ are generated by the received signal D ₀ . In FIG. 1, a combinational logic circuit 30 and exclusive OR gates 32 and 34 are shown.
A logic circuit having a clock controls the clock.

The phase control mechanism is applied when a data signal that is synchronized with the clock signal but has no known phase relationship is used in combination with the clock signal. Furthermore, these two signals are similarly affected in time by each other, and this wobble, or jitter, must be taken into account in the implementation of the system. The overall principle is shown in FIG.

As a phase control method, a common value δ (or δ ₁ and δ ₂ ) shorter than T / 2 is used, the phases of the clock signal and the data signal are relatively shifted, and three samplings are performed during stable operation. To collect the same value. Satisfying this condition ensures that the leading edge of H ₀ is not near the transition point of the data signal. Sampling collected near the transition point if this condition is not met But other sampling , The phase shift of the clock signal must be done in the downstream direction, as shown in the second row of FIG. The reverse is also true.

The choice of the value of δ affects the system's tolerance for phase jitter. In practice, the proposed technique divides the period of the data signal into three bands I, II and III, and divides these bands into The result is that the results sampled in (2) are made different (Fig. 6). First, it can be seen that the peak-to-peak amplitude of the phase jitter must be smaller than 2δ.
If not, both sides of the transition point of the data signal may not be detected and the signal may pass. Furthermore, the leading edge of the clock signal must not pass directly (jumping over the effective range) to the phase behind the effective range. If such a transition occurs, a ping-pong effect of error repetition and error control occurs. This second constraint is given by ω _cc = T−2δ−k (1). Where k is the magnitude of the phase shift performed by line 16 in response to the detection of off center. Therefore, the maximum allowable jitter is the smaller of the following two values:

ω _cc = inf (2δ, T−2δ−k) (2) The optimum value of k is k = T−4δ, and the maximum value ω _ccmax of the jitter amplitude corresponding to the k value is given by the following equation.

ω _ccmax = 2 δ = (T−k) / 2 (3) For a positioning device applying this method, several data signals that are transmitted one after another with transitions shifted by δ,
Alternatively, several clock signals shifted one after another and transmitted one after the other (either signal being unshifted and fixed) can be used. The first method is generally advantageous. This scheme is particularly adapted to phasing mechanisms of the type shown in FIG.

The mechanism of FIG. 5 has two input terminals DE and HE, to which a data signal and a clock signal synchronized with the data signal are applied, respectively. The positioning device comprises three flip-flops 10, 12, 14. The clock input of each flip-flop is coupled to the input terminal HE for receiving the local clock signal directly. Further, the input terminal HE is directly connected to the output terminal HS of the clock signal.

The data signal arriving at terminal DE passes through a programmable (variable delay) delay line 16 in steps of size k. The output signal of the delay line 16 is directly applied to the flip-flop 14. The output signal reaches the flip-flop 12 via the delay element 18 which produces a constant delay δ ₁ , and reaches the flip-flop 10 via the element 18 and the delay element 20 which provides the delay δ ₂ . Generally, δ ₂ = δ ₁ = δ
And The data signal at the output terminal DS is constituted by the output of the central flip-flop 12.

Further, the mechanism shown in FIG. 5 has flip-flops 10, 12, 1
An analysis circuit 22 for analyzing the output of No. 4 and controlling the variable delay line 16 is provided. The circuit 22 is a flip-flop 1
By analyzing and comparing the outputs of 0, 12, and 14,
Areas I, II, III of the data signal DS on the output terminal DS
It is provided to determine which (in FIG. 6) the leading edge of the clock signal HE is located. Further analysis circuit 2
2 must control the variable delay line 16 as follows. That is, if the leading edge of the clock signal is in region II, the delay pk
Leave unchanged.

Delay pk if the leading edge of the clock signal is in region I
To (p-1) k.

Delay p if the leading edge of the clock signal is in region III
Increase k to (p + 1) k.

The number n of basic steps provided by the delay line 16 is
A delay pk (0p is provided so that the leading edge of the clock signal can always escape from being in region I or III.
n) must be large enough to be performed. Therefore, when the peak-to-peak amplitude of the jitter is ω _cc, it is necessary that nk> δ + ω _cc . This is represented by nk> 3δ for the optimal δ studied in equation (3) above.

Next, numerical values of the embodiment and operation of the mechanism schematically shown in FIG. 5 will be described.

FIG. 7 corresponds to the numerical values selected as follows.

n = 2 k = T−4 δ (optimum value) δ = T / 6 (thus k = T / 3) In this case, the delay line incorporates two delay elements 26, each of which produces a delay of T / 3. It is composed of a multiplexer 24 having three inputs. Signal switching is 2
It is controlled by a register 28 of bits which inputs the clock signal to the clock input terminal and to the data input terminal the signals y ₀ and y ₁ from the combinational logic circuit 30.
Enter.

The combinational logic circuit 30 itself receives the output signals Z ₀ and Z _{1 of the} register 28 and the logic signals X ₀ and X ₁ output from the exclusive OR gates 32 and 34. Gates 32 and 3
The two input terminals of each of 4 are flip-flops 10, 1
It is connected to the outputs of two consecutive flip-flops 2 and 14.

The combinational logic circuit 30 analyzes by detecting four possible combinations of the signals X ₀ , X ₁ corresponding to the combination of states of the outputs of the flip-flops 10, 12, 14 given by the following table.

Here, B ⁺ , B and B ⁻ are flip-flops 1 respectively.
It corresponds to the output of 0, 12, and 14.

The truth value of the multiplexer 24 is as follows.

Here, a, b, and c represent inputs connected to the data inputs DE, T / 3 delay input, and 2T / 3 delay input, respectively.

The algorithm for the combinational logic circuit 30 to switch the multiplexer 24 is as follows.

Table 3 is equivalent to the combinational logic circuit 30 realizing the following functions.

y ₀ = X ₀ Z ₁ + X _{1 0 1 +0 1} Z ₀ y ₀ = X ₁ Z _{0 +0 1} Z ₁ + X _{0 0 1 The} above-mentioned set of functions is easily realized by a logic gate network.

The next embodiment is simpler than the previous embodiment, and it is possible to implement a single delay (ie, n = 1) by using one selection signal line Z. Only the lower part of FIG. 7 is shown modified in FIG. Here, elements corresponding to the elements in FIG. 7 are represented by the same numbers with a attached.

In this case, when δ = T / 8 and k = T / 2, the truth value of y is as follows.

Here _{y = X 0 + X 1 +} 0 1 Z.

The methods described so far can guarantee the correct phase relationship between the data signal and the sampling clock signal as long as the phase jitter is within the expected range.
On the contrary, this method is not intended to compensate for the loss of synchronization between the clock and data signals.

The second embodiment of the present invention is implemented when there is no synchronization condition between the clock signal and the data signal. In this case, frequency synchronization can be achieved by controlling the transition of the data signal. A simple method consists in using a frequency generator which operates between _two frequencies ₁ and ₂ one of which is definitely low and the other of which is absolutely high with respect to the reception frequency of the data signal DE. Frequency deviation of frequency generator (frequency deviation with respect to received frequency of data signal)
The direction of is reversed by switching when the phase difference between the data signal and the sampling clock signal exceeds a predetermined threshold value and changes from one clock frequency to the other clock frequency.

This method is adopted in the mechanism shown in FIG. 9, and the frequency generator shown in FIG. 9 employs a PLL (phase locked loop) as a basic structure and is used in a frequency synthesizer. It has a structure similar to. The transition point positioner with the mechanism of FIG. 9 has a structure similar to that of FIG. 7 as a positioner, and corresponding elements in both figures are designated by the same reference numbers.
The JK flip-flop 38 is the only logic circuit for analysis and determination, the clock input terminal of the flip-flop 38 inputs the output signal of the frequency generator 40, and the data input terminal inputs the outputs of the exclusive OR gates 32 and 34. .

Frequency generator 40 comprises a clock 42 for outputting a fixed frequency ₀ / N, the frequency ₀ / N frequency ₀
(N-1) / N and ₀ (N + 1) / N are set to be smaller and larger than the arrival frequency of the input data signal DE, respectively. The flip-flop 38 controls the frequency division ratio of the loop of the frequency generator 40. Therefore, the flip-flop 38 drives the variable frequency divider 44. The frequency division ratio x of the frequency divider is such that the signal input from the flip-flop 38 is logical 0.
N-1 when, and N + 1 when the received signal is at logic 1 level
Is.

The loop to which the frequency divider 44 is connected comprises an exclusive OR gate 46, which is used as a phase comparator and which has the output signal of the clock 42 at one input and the frequency divider at the other input. Receive output signal. Exclusive-OR gate 46 activates the frequency control input of oscillator 46 via filter RC, which outputs the clock signal H to the transition point positioner and divider 44. Flip flop 3
8 determines which frequency is most suitable at each moment and selects an appropriate frequency division ratio x for the PLL. This selection is performed according to the following table.

Δ (determines the certainty of signal synchronization detection) and (determines the fineness of the width of the frequency frame containing the reception frequency of the data signal by two possible values of the frequency of the local clock signal)
The value of N is selected depending on the characteristics of the signal. In particular, the selection must be made in consideration of the fact that the frequency of the data signal, if kept stable over a long period of time, causes a continuous deviation to one frequency and a sampling error.

Obviously, the oscillator system of FIG. 9 is shown as an example. The oscillator system can be replaced by any mechanism that can continuously change from a frequency lower than the input data signal frequency to a frequency higher than the data signal frequency and vice versa, depending on the specifications.

Mechanisms that deviate slightly from those described above based on the general principle of transition point detection can also be used.
Instead of sticking to synchronizing the clock outside the transition region of the data signal with two stops (regions I and III) that detect forward and backward drifts, as described below, It is possible to employ a mechanism that operates constantly to bring the reference clock closer to the transition point of the. In that case, it is confirmed that the clock signal can correctly sample the data in the opposite phase to the reference phase (FIG. 10). In the above-mentioned form, it is certain that the flip-flop outputs B ⁻ and B ⁺ have different states in the transition state of the data signal. Therefore, the following three states are known.

FIG. 11 shows the entire circuit diagram of the modification in the substantially synchronized reception range. This circuit diagram is only slightly different from FIG. The difference is that the flip-flop that supplies valid data is B ⁺ or B ⁻ in this embodiment, and that the command for selecting the clock signal is FIG.
Based on being the reciprocal of the 9 command.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of the principle of a transition point positioning device acting on a sampling clock signal of data. FIG. 2 shows a data signal D ₀ , an effective sampling area having a length of 2v, a clock signal H ₀ and a clock signal Hv with phase matching
2 is a time chart showing. Similar to FIG. 2, FIG. 3 shows the data signal D ₀ and three phase-shifted clock signals. Indicates. FIG. 4 shows the original data signal, the two phase-shifted data signals D ₁ , D ₂ and the sampling signal H. FIG. 5 is a principle diagram of a transition point positioning device applied to a resynchronization mechanism. FIG. 6 is a time chart showing different types of phase shifts of the clock signal and the data signal. FIG. 7 is similar to FIG. 5 and illustrates certain aspects of implementing the apparatus of FIG. FIG. 8 is a partial view showing a possible simplification of the mechanism of FIG. FIG. 9 shows a possible embodiment similar to that of FIG. 5 with a local clock signal which is substantially synchronized with the period of the data signal. FIG. 10 is a time chart of relative phases of a data signal and a clock signal in the second embodiment of the system. FIG. 11 is a schematic diagram of a logic circuit for the second embodiment. 10, 12, 14 ... Flip-flop 16 ... Delay line 18, 20 ... Delay circuit 22 ... Analysis circuit 24 ... Multiplexer 26 ... Delay element 30 ... Combination logic circuit 32, 34 ... Exclusive OR Gate 38 ... JK flip-flop 40 ... Frequency generator 42 ... Clock 44 ... Divider

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-161149 (JP, A) JP-A-56-35551 (JP, A) JP-A-60-69722 (JP, A) JP-A-59- 63835 (JP, A) JP47-39143 (JP, B1)

Claims (13)

[Claims] 1. A device for determining the position of a transition point of a data signal transmitted in digital form with respect to a leading edge of a local clock signal which is sequentially input in synchronization with or substantially in synchronization with the data signal. At least three flip-flops (10, 12, 14) and delay means (18, 20)
Logic means (22 or 30, 32, 34) and additional delay means (16 or 24, 26), each of the flip-flops having a clock input terminal for inputting a local clock signal and a local clock signal. And a data input terminal for inputting a data signal with a different time delay, the delay means (18, 20) has a value selected such that the sum of the different time delays is less than or equal to a clock cycle. Setting different time delays, the logic means being connected to the output of the flip-flop and designed to generate a control signal representing a phase relationship between the local clock signal and the data signal according to a predetermined criterion; The control signal may be in the first state, which shows correct phase synchronization when all flip-flops output the same signal, or in the first and second states. When the logic signal output from the flip-flop indicates non identical, between a local clock data, first
The second state indicating phase asynchronism in the direction of, or when the logic signals output from the second and third flip-flops indicate dissimilarity, the second state between the local clock and the data,
In a third state representing phase asynchronization in the direction of, and the additional delay means (16 or 24, 26) is adjustable between the local clock signal and all data signals applied to said flip-flops. To generate an additional time delay of and hold the control signal in the first state,
A mechanism for resynchronizing a local clock signal with a received data signal, the device having a transition point positioner for the data signal controlled by the control signal. 2. The delay means comprises a delay means (18, 2).
0) Mechanism according to claim 1, characterized in that it is produced by latching a data signal at a plurality of successive positions. 3. The mechanism according to claim 1, wherein the time delay is generated for a local clock signal. 4. When the valid data is sampled at the output of the central flip-flop and the control signal is in the second or third state, it outputs a signal different from the signal output by the two flip-flops. A means according to claim 1, characterized in that means are provided for acting on the phase relationship between the local clock signal and the data signal so that the other flip-flop present again outputs the same signal. Mechanism. 5. The control signal is first in the means for affecting the phase relationship.
The mechanism according to claim 4, wherein the mechanism does not operate when in the state of. 6. Valid data is sampled at the output of any one of the flip-flops on both sides, and when the control signal is in the second or third state, the control signal transitions from the second state to the third state, A mechanism according to claim 1, characterized in that means are provided for acting on the phase relationship between the local clock signal and the data signal so as to move in the opposite direction. 7. An adjustable delay circuit in which the local clock signal is synchronous with the data signal but has an indeterminate phase relationship with the data signal, and the means acting on the phase relationship are controlled by the control signal. 24, 26). The mechanism according to any one of claims 4 to 6, wherein 8. Mechanism according to claim 7, characterized in that a delay circuit (24, 26) is arranged at the connection for inputting a data signal to the delay means (18, 20). . 9. The mechanism of claim 8 wherein the delay circuit comprises a delay line with a plurality of plugs tied to the inputs of a multiplexer operated by a control signal. 10. A predetermined two values ( ₀ (N-1) / N and ₀ (N +) in which the local clock signal is substantially synchronized with the data signal and includes the frequency of the data signal from both sides.
1) / N) is output from a frequency generator (40) generating a variable frequency, and the frequency generator is controlled by the control signal so as to act on the phase relationship. The mechanism according to any one of claims 4 to 6. 11. The frequency generator (40) comprises a frequency synthesizer having a fixed frequency ( ₀ / N) clock (42) and a phase having a programmable frequency divider (44) operated by a control signal. 11. The mechanism according to claim 10, wherein the mechanism comprises a lock loop. 12. A logic means (22) includes an exclusive OR gate (32,34) connected to each pair of flip-flops (10,12,14) and an exclusive OR gate for outputting a control signal. A mechanism according to any one of claims 4 to 11, further comprising means for analyzing an output signal of the sum gate. 13. The logic means (22) has an exclusive OR gate (32, 34) connected to each pair of flip-flops (10, 12, 14), and the output of the exclusive OR gate is auxiliary. Drive the data input of the flip-flop (38), the clock input of the auxiliary flip-flop inputs the local clock signal, and the auxiliary flip-flop divides the frequency division ratio of the frequency divider (44) by the two values. 12. A mechanism as claimed in claim 11 which is connected to the control input of the frequency divider for selecting between.