JPH0614624B2 - Digitally controlled adaptive AGC equalization method - Google Patents

Description

Description: (a) Technical Field of the Invention The present invention relates to an AGC circuit of an AGC equalizer of a PCM relay transmission apparatus and relates to a digital control type adaptive AGC method capable of reducing the hardware scale of an integrating circuit.

(b) Prior Art and Problems The isolated pattern and intersymbol interference will be described with reference to FIG.

It is assumed that the isolated pattern shown in FIG. 5 (A) has intersymbol interference at a position 1 time slot away from the peak of "1" of the received waveform shown in (A) (c).

In this case, since the isolated patterns shown in (A) and (a) are isolated patterns, the signal "1" of the received waveforms in (A) and (c) is not affected by intersymbol interference, and the peak value changes to the loss variation of the transmission line. One-to-one correspondence.

On the other hand, in the case of the pattern shown in (B), the peak value of the received waveform of "1" when there is one "0" immediately before, such as "01", is not affected by the intersymbol interference, but is "11". If there is a "1" immediately before, such as "," the amplitude of intersymbol interference one time slot before is added, and the peak value is greater than the peak value of the "01" pattern as shown in (B) and (f). It gets smaller.

In the AGC system of the conventional AGC equalizer, all the peak values of one level of the received signal are viewed and fetched as gain update information. In this case, the 1-level peak value currently seen is not the peak value of the isolated pulse response of the transmission line itself, but is influenced by the pattern one clock before, and the 1-level peak value is received. It changes according to the pattern. Therefore, it is necessary to distinguish whether the peak value of the received signal is changing or the peak value is changing due to the influence of the reception pattern due to the fluctuation of the loss of the transmission line. In general, the fluctuation of the reception pattern due to the loss fluctuation of the transmission line fluctuates over a time much longer than the transmission speed.Therefore, by integrating the peak value during that time with a long time constant, the fluctuation of the transmission line loss The change in peak value will be recognized.

In order to do this, the capacitance of the capacitor of the integrating circuit becomes large, so that the LSI cannot be implemented and the hardware scale cannot be reduced. Therefore, if this function is realized by a digital circuit that can be integrated into an LSI, it is determined whether the peak value is larger or smaller than a predetermined reference amplitude, and the large and small numbers are integrated over a long time. However, in order to realize a long integration time constant, a large number of counters are required and the hardware scale becomes large.

(c) Object of the Invention An object of the present invention is to suppress the peak value fluctuation due to the reception pattern by extracting only one level peak value that directly represents the loss fluctuation of the transmission line in the reception pattern. The purpose of this is to provide a digital control type adaptive AGC method which can reduce the hardware scale of the integrating circuit by using the gain update information.

(d) Structure of the Invention In order to achieve the above object, the present invention focuses on the fact that one level after the continuous O levels in the reception pattern almost faithfully represents the loss variation of the transmission line. In the case where the level of the received equalized signal is equal to or higher than a predetermined amplitude is set to 1 level, a pattern in which M 0 levels (M is an integer of 1 or more) continues before 1 level is detected, and a peak included in the pattern is detected. It is characterized in that only the value is used as information for updating the gain of the line equalizer.

(e) Embodiment of the invention Since the signal sent to the transmission line normally uses a DC component suppression code such as an AMI code, in this case, the DC component regeneration is not performed. If the DC component suppression code is not used, the DC component regeneration is performed. Do 1,0
The identification voltage of is set to the middle of one level,
Except for this point, the direct current component regeneration is considered to be independent of AGC, and an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a main part of a PCM relay transmission apparatus according to an embodiment of the present invention, and FIG. 2 is a digital control type adaptive (adaptive) AGC circuit for detecting a "001" pattern according to an embodiment of the present invention. The block diagram and FIG. 3 are time charts of the waveforms of the respective parts in FIG. 2, and are V _R1 , V _R2 , a, P ₁ , P ₂ , CLK1, P ₃ ,
_{P 4, P 5, b,} P 6, P 7, P 8, P 9, C, P 0, CLK 2 corresponds to a point of the same symbols in each second view.

In the figure, 1 is a line equalizer having discrete equalization characteristics, 2 is a timing extraction circuit, 3 and 3'is a peak detection circuit, 4 is an initial pull-in circuit, 5 is an adaptive AGC circuit, 6 is a selector, and 7 is a selector. Up-down counter, 8 and 9 are comparators, 1
Reference numerals 0, 16, 20 are knot circuits, 11 and 12 are NAND circuits, 13 is an OR circuit, 14 is a shift register, 15 is a "001" pattern detection circuit, 17 is an AND circuit, 18
Is an up / down counter, and 19 is an O, N detection circuit.

FIG. 1 shows a digital control type adaptive AGC of the present invention.
The principal part of the PCM relay transmission apparatus when the method is applied is shown.

Since the line equalizer 1 is in the maximum gain state at the start of communication, the timing extraction circuit 2 cannot extract an accurate timing clock from the equalized output signal. In order for the timing extraction circuit 2 to perform accurate timing extraction, it is necessary to set the gain of the line equalizer 1 to a desired gain by some method. In the case of FIG. 1, this operation is performed by the peak detection circuit 3, the initial pull-in circuit 4, and the up / down counter 7.

This is the applicant's Japanese Patent Application No. 58-09 June 6, 1983
The patent application was filed at 9456, and the reference voltage 1 equal to the desired equalized output signal amplitude and the first comparator for inputting the equalized output signal and the voltage of 1/2 of the reference voltage 1 are used as the reference. When the output of the first comparator becomes 1 level when the outputs of the second comparator and the second comparator which input the reference voltage 2 which is a voltage and the equalized output signal are 1 level (event A) When the output of the first comparator does not reach 1 level when the output of the second comparator and the output of the second comparator is at 1 level, the means for detecting when the output of the 1st comparator is not at 1 level and the number of occurrences of the event A is counted and is a constant value. When the gain becomes N ₁ , the gain of the line equalizer 1 is updated so as to decrease, and at the same time, the count value is reset to 0 and the counting is started again.
The number of consecutive occurrences of the line equalizer is counted, and the gain of the line equalizer 1 is set to a desired gain by a means for stopping the update of the gain of the line equalizer 1 when the value reaches a constant value N ₂ .

As a result, the timing extraction circuit 2 operates in the line equalizer 1
It becomes possible to extract a clock in phase with the received equalized signal of. After that, it is an object of the present invention to update the gain of the line equalizer 1 by the peak detection circuit 3 and the adaptive AGC circuit 5 up / down counter 7.
An embodiment of the present invention will be described below with reference to FIGS.

The reference voltage V _{R1 in} FIG. ₂ is a voltage equal to the desired equalized output signal swing, and the reference voltage V _R2 is the discrimination level of the equalized output signal and is usually half the reference voltage V _R1 . This state is the third
This is shown in Figures V _R1 and V _R2 . The output P ₁ of the comparator 8 is the third
It is a signal obtained by slicing the equalized output signal shown in FIG. 3A with the reference voltage V _R1 , and becomes 1 level when the equalized output signal a is larger than the reference voltage V _{R1 as} shown in P ₁ of FIG. The output P ₂ of the comparator 9 is a signal obtained by slicing the equalized output signal shown in FIG. 3A with the reference voltage V _R2 , and the equalized output signal a is larger than the reference voltage V _{R2 as} shown in P ₂ of FIG. Hour 1
Level is 0 level when small.

The output P ₄ of the “001” pattern detection circuit 15 is the third
FIG. P ₄ becomes 1 level when the “001” pattern is detected as shown in FIG. 3 P ₄ . The output P ₆ of the O, N detection circuit 19 is 1 level when the count value n (FIG. 3b) of the up / down counter 18 is n = N or 0, as shown in P ₆ of FIG. 3, 0 <n <0 level signal serving when n, O, _{P 7} of the output of the n detection circuit 19, as shown in FIG. 3 _{P 7,} the count value n of the up-down counter 18 (FIG. 3 b) is n =
This signal is 1 level when N and 0 level when n = 0.

A clock CLK2 shown in CLK2 in FIG. 3 is a timing for updating the gain of the line equalizer, and is for observing the state of the count value n of the counter 18 in this clock cycle.

In the state where the initial pull-in is completed and the clock having the phase with the reception equalized signal is extracted, the gain is updated at the timings (1) and (2) shown below, for example. this is,
This is to prevent glitches and the like from occurring due to the transient response of the amplifier when the gain of the line equalizer is updated, and to prevent errors in significant data.

(1) In the case of normal continuous PCM transmission, switching is performed at an arbitrary point in the frame synchronization pattern. Since the time constant for updating the gain is long, the period for updating the gain is N times the frame period.

Even if a glitch occurs due to the gain update and the frame synchronization pattern of the received signal is erroneous, if the gain update period is set longer than the number of protection stages of the frame period, synchronization will not be lost due to the error.

(2) Burst PCM transmission (eg ping-pong transmission)
Then, switching is performed in the no-signal period after the reception burst ends. By doing so, even if a glitch occurs due to the gain update, the effect is eliminated.

Since the time constant for updating the gain is long, the period for updating the gain is N times the burst repetition period. CLK1 is a clock extracted by the timing extraction circuit 2 of FIG.

The operation will be described below. When the equalized output signal shown in FIG. 3a exceeds the reference voltage VR ₁ , the output signal P _{3 of the} NAND circuit 11
Becomes 1 level as shown in P ₃ of FIG. In the received data shown in P ₀ of FIG. 3 of the output of the shift register 14,
The "001" pattern is detected by the "001" pattern detection circuit 1
5, the signal P ₃ becomes 0 when the pattern arrives.
See level or level 1. That is, if P ₃ = 0 at the rising edge of the output signal P ₅ of the AND circuit 17, the up / down counter 18 does not count, and if P ₃ = 1 then one counts up. The state of this count value is shown in FIG. 3b, and this count value is sent to the O, N detection circuit 19. When the count value n is N, the O / N detection circuit 19 determines that the equalized output signal amplitude is larger than the desired amplitude, and counts down the up / down counter 7 by one, 3 the value of the output of the up-down counter 7 shown in FIG _{P 9} at the rising time of the clock CLK ₂ shown in FIG. 3 CLK ₂ is latched by the latch circuit 24, first
The signal shown in FIG. 3C is sent to decrease the gain of the line equalizer 1 in the figure by one step. If the count value n is 0 of the up-down counter 18 in the opposite, it is determined that the equalized output signal Fuhaba is less than the desired Fuhaba, the up-down counter 7 1 counts down, up shown in Figure 3 P ₉ The output value of the down counter 7 is latched by the latch circuit 24 and the third value is output.
At the rising edge of the clock CLK ₂ shown in the diagram CLK ₂ , a signal is sent to increase the gain of the line equalizer 1 in FIG. 1 by one step. The O, N detection circuit 19 uses the signal P shown in P ₈ of FIG.
₈ is sent to the counter 18 and the counter 18 is set to N / 2, and thereafter the up / down counter 18 continues counting.

If a pattern in which 0 levels preceding the 1 level continues N times is set as a pattern included in the frame synchronization pattern in the reception equalized signal, this pattern can be found without fail.

FIG. 4 is a block diagram of a circuit for selecting a pattern with a small 0 level before the 1 level when there is a demand to shorten the response time in the embodiment of the present invention.

In the figure, those having the same functions as those in FIG. 2 are indicated by the same symbols, 21 is a "01" pattern detection circuit, and 22 and 23 are switches.

Since it is necessary to shorten the response time when the frame period is not set, the frame synchronization signal in this case is set to 0, for example.
When the level and the frame synchronization signal are set to 1 level, the frame synchronization signal is input to the switches 22 and 23. When the frame synchronization signal is 0 level, the pattern detection circuit is set to "0".
If the "01" pattern detection circuit 15 is switched to the "01" pattern detection circuit 21, the response time can be shortened.

(f) Effect of the Invention As described in detail above, according to the present invention, a pattern in which N 0 levels preceding the 1 level continues is detected and only the peak value included in the pattern is used as the gain update information.
The number of stages of the counter can be small, and the hardware scale of the integrating circuit of the AGC circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a PCM relay transmission apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a digital control type adaptive AGC circuit for detecting a "001" pattern according to an embodiment of the present invention. FIG. 3 is a time chart of the waveform of each part of FIG. 2, and FIG. 4 is a case where there is a demand to shorten the response time of the embodiment of the present invention, a pattern with a small 0 level before the 1 level is selected. Block diagram of the circuit
The figure shows an isolated pattern and intersymbol interference. In the figure, 1 is a line equalizer having discrete equalization characteristics, 2 is a timing extraction circuit, 3 and 3'is a peak detection circuit, 4 is an initial pull-in circuit, 5 is an adaptive AGC circuit, 6 is a selector, and 7 is a selector. Up-down counter, 8 and 9 are comparators, 1
Reference numerals 0, 16, 20 are knot circuits, 11 and 12 are NAND circuits, 13 is an OR circuit, 14 is a shift register, 15 is a "001" pattern detection circuit, 17 is an AND circuit, 18
Is an up / down counter, 19 is an O / N detection circuit, 21
Is a "01" pattern detection circuit, 22 and 23 are switches,
Reference numeral 24 represents a latch circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshitaka Tsuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Kazuo Yamaguchi 1015 Kamedotaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Setsu Fukuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Akihiko Takada, 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kimura, Tadakatsu Kanagawa Prefecture 1839 Ono, Atsugi City, Atsugi Telecommunications Research Institute, Nippon Telegraph and Telephone Corporation (72) Masayuki Ishikawa, 1839, Ono City, Atsugi City, Kanagawa Prefecture

Claims (2)

[Claims] 1. An AGC equalizer of a PCM transmission device,
In the case of setting the level of the received equalized signal to 1 level when the received equalized signal has a desired amplitude or more after the timing extraction circuit extracts a clock in phase with the received equalized signal of the line equalizer having a discrete equalizing characteristic. There are M 0 levels before 1 level (M is 1
Digitally controlled adaptive A characterized in that the following pattern is detected and only the peak value contained in the pattern is used as information for updating the gain of the line equalizer.
GC method. 2. When the frame synchronization cannot be achieved and the response time is required to be shortened according to claim 1,
A digital control type adaptive AGC method characterized in that the pattern is automatically switched to a pattern having a small number of 0 levels before 1 level during adaptive AGC operation.