JPH0614528A - Substrate potential generation circuit - Google Patents

Abstract

PURPOSE:To reduce fluctuation of a substrate potential generated in a substrate potential generation circuit for stabilization. CONSTITUTION:The title circuit consists of a substrate potential detection part K11 with a substrate potential signal as an input, an oscillator part K12 with a signal from the substrate potential detection part K1 as input, and a substrate potential generation part K13 which outputs substrate potential with a signal from the oscillator part K12 as input. In the oscillator part K12, the gate potential of P-type transistors Q106, Q110, and Q114 or N-type transistors Q108, Q112, and Q116 is controlled to the substrate potential and the fluctuation of the substrate potential is minimized by controlling the frequency of the oscillator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a substrate potential generation circuit.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor integrated circuit includes a substrate potential detecting section K ₂₁ for inputting a substrate potential and an oscillator section K for inputting a signal from the substrate potential detecting section K ₂₁ as a switch signal. ₂₂ and a substrate potential generation unit K ₂₃ that inputs a signal from the oscillator unit K ₂₂ and outputs a substrate potential. Q ₂₀₁ , Q ₂₀₄ , Q ₂₀₆ , Q ₂₀₇ , Q
₂₁₀ , Q ₂₁₃ , Q ₂₁₄ , Q ₂₁₈ , Q ₂₁₉ , Q ₂₂₂ , Q ₂₂₃ , Q
₂₂₄ is a P-type transistor, Q ₂₀₂ , Q ₂₀₃ , Q ₂₀₅ ,
Q ₂₀₈ , Q ₂₀₉ , Q ₂₁₁ , Q ₂₁₂ , Q ₂₁₆ , Q ₂₁₇ , Q ₂₁₀ ,
Q ₂₂₁ and Q ₂₂₃ are N-type transistors. I ₂₁ , I ₂₂ ,
I ₂₃ , I ₂₄ , I ₂₅ , and I ₂₆ are inverters. C ₂₁ ,
C ₂₂ is a capacitance and R ₂₁ is a resistance.

Next, the operation will be described. The signal from the substrate potential detector K ₂₁ rises as the substrate potential rises. Then, the switch P of the oscillator K ₂₂ is
The type transistor Q ₂₁₀ and the N type transistor Q ₂₁₁ are turned on, and the oscillator section K ₂₂ is activated. Substrate potential generator K ₂₃
Receives the output of the oscillator section K ₂₂ and lowers the substrate potential. When the substrate potential is lowered to a certain level, the signal Φ ₂₁ drops, and the P-type transistor Q ₂₁₀ and the N-type transistor Q _{211, which} are the switches of the oscillator section K ₂₂ , become O.
FF and stops Oshureta section K _22, the substrate potential generating portion K ₂₃ with it stops the operation to lower the substrate potential. In this way, the substrate potential is controlled.

[0004]

In the conventional substrate potential generating circuit, the substrate potential is controlled by the operation of the oscillator section.
Since it is performed by N and OFF, the substrate potential becomes as shown in FIG. 4, and there is a problem that the amount of fluctuation of the substrate potential is large.

An object of the present invention is to provide a substrate potential generation circuit which suppresses fluctuations in the substrate potential and generates a stable substrate potential.

[0006]

In order to achieve the above object, a substrate potential generating circuit according to the present invention is a substrate potential generating circuit having a substrate potential detecting section, an oscillator section, and a substrate potential generating section. The substrate potential detection unit receives the substrate potential signal from the substrate potential generation unit and outputs a substrate potential detection signal, and the oscillator unit receives the signal from the substrate potential detection unit as an input and controls the frequency. The substrate potential control unit outputs a substrate potential control signal, and the substrate potential generation unit receives the signal from the oscillator unit and outputs the substrate potential signal.

[0007]

The oscillator section is configured to output the substrate potential control signal by frequency control. By controlling the frequency of this oscillator, the fluctuation of the substrate potential is suppressed to a small level.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIG. 1, the semiconductor integrated circuit of the present invention, the output of the substrate potential detection unit K ₁₁ which receives the substrate potential signal is input to the Oshureta section K _12, the output of Oshureta section K ₁₂ is the substrate potential generating portion K ₁₃ When input, the substrate potential generator K ₁₃
The output of is controlled to the substrate potential.

Next, details of the oscillator section K ₁₂ will be described. N-type transistor Q ₁₀₅ is the output signal [Phi ₁₁ is input substrate potential detection unit K ₁₁ to the gate, the source signal [Phi _12, ground potential to the drain is inputted.
P-type transistor Q ₁₀₄ is power, gate, drain signal [Phi ₁₂ is connected to the source, the resistor R ₁₁ is connected to the signal [Phi ₁₂ and the ground potential.

The signal Φ ₁₁ passes through the inverter I ₁₁ and the signal Φ _11
23 . The P-type transistor Q ₁₁₈ has a power source as its source,
The signal Φ ₂₃ is connected to the gate and the signal Φ ₂₂ is connected to the drain.
The type transistor Q ₁₁₉ has a source and a gate connected to the signal Φ ₂₂ , and a drain connected to the ground potential, and the resistor R ₁₂ is connected to the power supply and the signal Φ ₂₂ .

The P-type transistor Q ₁₀₆ has a power source as its source,
The signal Φ ₁₂ is connected to the gate, and the signal Φ ₁₃ is connected to the drain. The P-type transistor Q ₁₀₇ has the signal Φ ₁₃ connected to the source, the signal Φ ₂₁ connected to the gate, and the signal Φ ₁₄ connected to the drain. _A signal Φ ₁₀₄ is connected to the source of ₁₀₈ , a signal Φ ₂₂ is connected to the gate, and a signal Φ ₁₅ is connected to the drain. N-type transistor Q ₁₀₉ has a signal Φ _{15 at} the source, a signal Φ _{22 at} the gate, and a ground potential at the drain. It is connected.

The P-type transistor Q ₁₁₀ has a power source as its source,
The signal Φ ₁₂ is connected to the gate, and the signal Φ ₁₆ is connected to the drain. The P-type transistor Q ₁₁₁ has the source connected to the signal Φ ₁₆ , the gate connected to the signal Φ ₁₄ and the drain connected to the signal Φ _17, and the N-type transistor Q _112. Has a signal Φ ₁₇ connected to the source, a signal Φ ₁₄ connected to the gate, and a signal Φ ₁₈ connected to the drain.
The N-type transistor Q ₁₁₃ has a source connected to the signal Φ ₁₈ , a gate connected to the signal Φ ₂₂ , and a drain connected to the ground potential.

The P-type transistor Q ₁₁₄ has a power source as its source,
The signal Φ ₁₂ is connected to the gate and the signal Φ ₁₉ is connected to the drain, and P
The type transistor Q ₁₁₅ has a source connected to a signal Φ ₁₉ , a gate connected to a signal Φ ₁₇ and a drain connected to a signal Φ _21, and the N-type transistor Q ₁₁₆ has a source connected to a signal Φ ₂₁ and a gate connected to a signal Φ ₂₁ .
₁₇ , the signal Φ ₂₀ is connected to the drain, and the N-type transistor Q ₁₁₇ has a signal Φ _{20 at} the source and a signal Φ _{22 at} the gate.
Ground potential is connected to the drain. The signal Φ ₂₁ is input to the substrate potential generation unit K ₁₃ .

Next, the operation will be described. When the substrate potential rises, the signal Φ which is the output signal of the substrate potential detector K _11
11 also rises, turning on the N-type transistor Q ₁₀₅ and lowering the potential of the signal Φ ₁₂ , so that the P-type transistor Q _105
The current flowing through ₁₀₄ , Q ₁₀₆ , Q ₁₁₀ and Q ₁₁₄ is increased.

Similarly, when the potential of the signal Φ ₁₁ rises, the signal Φ ₂₃ falls, turning on the P-type transistor Q ₁₁₈ and lowering the potential of the signal Φ ₂₂ to reduce the potential of the N-type transistor Q _118.
The current flowing through ₁₀₉ , Q ₁₁₃ , Q ₁₁₇ , and Q ₁₁₉ is increased.
In other words, P-type transistor Q ₁₀₆ and P connected in parallel
Type transistor Q ₁₀₇ , N type transistor Q ₁₀₈ and N type transistor Q ₁₀₉ , P type transistor Q ₁₁₀ , P type transistor Q ₁₁₁ , N type transistor Q ₁₁₂ and N type transistor Q ₁₁₃ , P type transistor Q ₁₁₄ and P type transistor Q ₁₁₄ Type transistor Q ₁₁₅ and N type transistor Q ₁₁₆ and N type transistor Q
_The current flowing through ₁₁₇ increases, and signal Φ ₂₁ , signal Φ _14, and signal Φ
The frequency of ₁₇ increases. As the frequency of the signal Φ ₂₁ increases,
The number of operations of the substrate potential generator K ₁₃ increases, and the substrate potential is lowered.

When the substrate potential is lowered in this way, the potential of the output signal Φ ₁₁ of the substrate potential detector K ₁₁ is also lowered, and the signal Φ ₂₃ is raised to turn on the N-type transistor Q ₁₀₅ and the P-type transistor Q ₁₁₈ , respectively. The signal is turned off, the signal Φ ₂₁ is increased, and the signal Φ ₂₂ is decreased. As a result, the current flowing through the transistors connected in parallel decreases, the frequency of the signal Φ ₂₁ also decreases, and the number of operations of the substrate potential generating section decreases.

In this way, the substrate potential can always control the operation of the substrate potential generating section K ₁₃ and maintain a constant potential.

[0018]

As described above, according to the present invention, the operation of the substrate potential generation unit can be controlled by controlling the frequency of the oscillator unit by the output of the substrate potential detection unit, and as shown in FIG. The substrate potential can be maintained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a diagram showing a substrate potential according to the present invention.

FIG. 4 is a diagram showing a substrate potential according to a conventional circuit.

[Explanation of symbols]

 I₁₁, I₁₂, I₁₃, I₁₄, I_{twenty one}, I_{twenty two}, I_{twenty three}, I_{twenty four}, I
_{twenty five}, I₂₆ Inverter C₁₁, C₁₂, C_{twenty one}, C_{twenty two} Capacity K₁₁, K_{twenty one} Substrate potential detector K₁₂, K_{twenty two} Oscillator part K₁₃, K_{twenty three} Substrate potential generator R₁₁, R₁₂, R_{twenty one} Resistance Q₁₀₁, Q₁₀₄, Q₁₀₆, Q₁₀₇, Q₁₁₀, Q₁₁₁, Q₁₁₄，
Q₁₁₅, Q₁₁₈ , Q₁₂₀, Q₁₂₁, Q₁₂₁, Q₂₀₁, Q₂₀₄，
Q₂₀₆, Q₂₀₇, Q₂₁₀, Q₂₁₃, Q₂₁₄, Q₂₁₈, Q₂₁₉，
Q₂₂₂, Q₂₂₃, Q₂₂₄ P-type transistor Q₁₀₂, Q₁₀₃, Q₁₀₅, Q₁₀₈, Q₁₀₉, Q₁₁₂, Q₁₁₃，
Q₁₁₆, Q₁₁₇, Q₁₁₉, Q₂₀₂, Q₂₀₃, Q₂₀₅, Q₂₀₈，
Q₂₀₉, Q₂₁₁, Q₂₁₂, Q₂₁₅, Q₂₁₆, Q₂₁₇, Q₂₁₀，
Q₂₂₁ N-type transistor

Claims (1)

[Claims] 1. A substrate potential detection unit, an oscillator unit,
A substrate potential generation circuit having a substrate potential generation unit, wherein the substrate potential detection unit receives a substrate potential signal from the substrate potential generation unit and outputs a detection signal of the substrate potential, and the oscillator unit is The signal from the substrate potential detector is input to output a substrate potential control signal by frequency control. The substrate potential generator receives the signal from the oscillator unit and outputs the substrate potential signal. A substrate potential generation circuit characterized by the above.