JPH06140914A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To changeover a threshold value a chip itself in which the semiconductor integrated circuit is formed by selectively forming the circuit in which the rate of the threshold value differs from a level of a power supply voltage in response to the level of the power supply level. CONSTITUTION:An inverter 3 is connected between an input node 2 receiving an input signal and an output node 4. A switching circuit 5 and an N-channel MOS transistor (TR) 6 are connected in series between the output node 4 and a 2nd power supply node 7 receiving a ground potential. A potential discrimination circuit 9 is connected between a control signal input section of a switching circuit 5 and a 1st power supply node 8 receiving a power supply potential. When the potential discrimination circuit 9 discriminates the 1st power supply potential to be a prescribed level or over, the circuit comprising inverters and TRs is formed. When it is discriminated that the 1st power supply potential does not reach a prescribed level, the circuit comprising only inverters is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit formed on one chip and outputting a signal according to the level of an input signal.

[0002]

2. Description of the Related Art In an electric device equipped with a semiconductor integrated circuit, the semiconductor integrated circuit is generally operated by receiving a power supply potential as high as 5V. An input circuit such as an inverter, which is one of semiconductor integrated circuits and outputs a logic signal corresponding to the level of an input signal, has a low input signal level (for example, 0.8
In many cases, the threshold voltage for the operation is set to a value (TTL input level) as low as about ¼ of the power supply potential. Was becoming.

In recent years, electric equipment has become portable, and accordingly, the power supply potential tends to be lowered. In the input circuit, the TT whose threshold voltage corresponds to the power supply potential
Since it is set to a value corresponding to the L input level, when the power supply potential becomes a low potential as described above, the threshold voltage thereof becomes a very low value, so that the margin for input noise decreases. There is. Therefore, in the input circuit, when the power supply potential is low, it is necessary to set the threshold voltage to the CMOS input level (1/2 of the power supply potential).

In this way, the TTL input level or CM
To obtain an input circuit that can handle the OS input level,
There are two types of masks: a mask for a circuit that obtains a threshold voltage for a TTL input level and a mask for a circuit that obtains a threshold for a CMOS input level in a wafer process when manufacturing a chip that forms an input circuit. Prepare a mask,
Manufacture two types of chips or T on one chip
Circuit and CM for obtaining threshold voltage for TL input level
It has been necessary to manufacture an input circuit having a configuration in which the circuit can be switched to either a circuit that can obtain a threshold voltage for the OS input level.

The input circuit whose circuits can be switched as described above has a structure as shown in FIG. FIG. 9 is a circuit diagram showing a configuration of a conventional input circuit.

The following circuits are formed on the semiconductor chip 1. First power supply node 8 and output node 4 which receive the power supply potential
A P-channel MOS type transistor 31 is connected between and. An N-channel MOS transistor 32 and an N-channel MOS transistor 50, 6 are connected in series between the output node 4 and the second power supply node 7 receiving the ground potential.

Input node 2 through transistors 31, 3
An input signal is applied to each of the gates 2 and 6. In addition, a control signal input node 4 that receives a control signal from the outside
A control signal is applied from 0 to the gate of the transistor 50.

Next, the operation will be described. When the power supply potential received by the first power supply node 8 is low (for example, 3 V)
Is set to a low level by the control signal applied from the control signal input node 40 to the transistor 50,
0 turns off. As a result, the current drive capability ratio of the transistors of the input circuit becomes
Therefore, if the current drive capability ratio of this transistor is set to be 1: 1, the threshold voltage of this input circuit becomes 1.5 V, which is 1/2 of the power supply potential.

On the other hand, when the power supply potential received by first power supply node 8 is high (for example, 5 V), control signal input node 4
The control signal applied to the gate of the transistor 50 from 0 is set to the high level, and the transistor 50 is turned on. As a result, the current drive capability ratio of the transistors in the input circuit becomes transistor 31: (transistor 32 + transistor 50 + transistor 6), and this current drive capability ratio (where transistor 31: transistor 32 is 1:
1) is set to 1: 3, the threshold voltage of this input circuit becomes 1.25 V, which is ¼ of the power supply potential.

As described above, in the conventional input circuit, the threshold voltage is switched based on the control signal given from the outside of the semiconductor chip 1.

[0011]

However, as described above, in order to form a circuit having different thresholds in the manufacturing process,
When preparing different types of masks, there is a problem that the manufacturing cost of the circuit increases. This problem can be solved in the circuit of FIG. 9, but in the circuit for switching the threshold value based on an external control signal as in the case of FIG. 9, the chip itself in which the circuit is formed switches the threshold value. However, there is a problem in that an additional device for supplying a control signal is required.

The present invention has been made in order to solve such a problem, and provides a semiconductor integrated circuit capable of switching the threshold value on the chip itself on which the semiconductor integrated circuit is formed. The purpose is to

[0013]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit which is formed on one chip and outputs a signal according to a level of an input signal. It includes a second power supply node, an input node, an output node, an inverter, a transistor, a potential discriminating means and a connecting means. The first power supply node receives the first power supply potential. The second power supply node receives the second power supply potential. The input node receives the input signal. The inverter is connected between the input node and the output node. The transistor is controlled in response to the input signal.

The potential determining means determines whether or not the first power supply potential received by the first power supply node is at a predetermined level. The connection means connects the transistor between the output node and the second power supply node when the potential determination means determines that the first power supply potential is equal to or higher than a predetermined level.

The present invention according to claim 2 is a semiconductor integrated circuit which is formed on one chip and outputs a signal according to the level of an input signal, the first power supply node and the second power supply node. , Output node, inverter, transistor, potential discriminating means and connecting means.

The first power supply node receives the first power supply potential. The second power supply node receives the second power supply potential.
The input node receives the input signal. The inverter is
It is connected between the input node and the output node.
The transistor is controlled in response to the input signal.

The potential discriminating means discriminates whether or not the first power supply potential received by the first power supply node is equal to or higher than a predetermined level. The connecting means is the first of the potential discriminating means.
The transistor is connected between the output node and the first power supply node when it is determined that the power supply potential is above a predetermined level.

According to a third aspect of the present invention, the potential discriminating means according to the first aspect lowers the first power source potential received by the first power source node by a predetermined value. Discrimination result output means for outputting a signal showing a discrimination result as to whether or not the first power supply potential is at or above a predetermined level depending on whether or not the potential dropped by the potential dropping means is at or above a certain level, It is characterized by including a resistance means connected between a node between the potential lowering means and the discrimination result output means and the second power supply node.

According to a fourth aspect of the present invention, the potential discriminating means according to the second aspect lowers the first power supply potential received by the first power supply node by a predetermined value. Discrimination result output means for outputting a signal showing a discrimination result as to whether or not the first power supply potential is at or above a predetermined level depending on whether or not the potential dropped by the potential dropping means is at or above a certain level, It is characterized by including a resistance means connected between a node between the potential lowering means and the discrimination result output means and the second power supply node.

[0020]

According to the present invention, when the potential discriminating means discriminates that the power supply potential is equal to or higher than a predetermined level, the connecting means causes the transistor to operate as an output node and a second power supply node. The first circuit is composed of the inverter, the transistor and the connecting means. On the other hand, when it is determined by the potential determining means that the power supply potential is not higher than the predetermined level, the second only by the inverter.
Circuit is formed. Since the circuit configurations of the first circuit and the second circuit are different, the threshold voltage for the input signal is different. Therefore, the circuit itself formed on the chip can change the ratio of the threshold voltage to the first power supply potential according to the level of the first power supply potential.

According to the second aspect of the present invention, when the potential discriminating means discriminates that the power supply potential is equal to or higher than a predetermined level, the connecting means causes the transistor to be connected to the output node and the first power supply node. The first circuit is composed of the inverter, the transistor and the connecting means. On the other hand, when the potential determining means determines that the power supply potential is not higher than the predetermined level, the second circuit is formed by only the inverter. Since the circuit configurations of the first circuit and the second circuit are different, the threshold voltages for the input signals are different. Therefore, the ratio of the threshold voltage to the first power supply potential can be changed in accordance with the level of the first power supply potential in the circuit itself formed in the chip.

According to the present invention as set forth in claims 3 and 4, the resistance means is connected between the node between the potential lowering means and the discrimination result output means and the second power supply node. By this resistance means, excess charges accumulated in the parasitic capacitance of the discrimination result output means due to external noise are discharged from the second power supply node, so that the value of the input potential of the discrimination result output means is stabilized.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment First, a first embodiment of the present invention will be described. Figure 1
FIG. 3 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to the first embodiment. The following input circuit is formed on the semiconductor chip 1. This input circuit outputs a signal obtained by inverting the logic of the input signal.

Inverter 3 is connected between an input node 2 receiving an input signal and an output node 4. Output node 4
A switching circuit 5 and an N-channel MOS type transistor 6 are connected in series between and and a second power supply node 7 receiving the ground potential. Input node 2 and transistor 6
Is connected to the gate. A potential discriminating circuit 9 is connected between the first power supply node 8 receiving the power supply potential and the control signal input portion of the switching circuit 5. The potential discriminating circuit 9 includes a potential lowering circuit 91 which is a potential lowering means and a sense circuit 92 which is a discrimination result outputting means which are connected in series between the first power supply node 8 and the switching circuit 5.

Next, the detailed configuration of the input circuit of FIG. 1 will be described. FIG. 2 is a circuit diagram showing a detailed configuration of the input circuit of FIG.

Inverter 3 includes a P-channel MOS type transistor 31 and an N-channel MOS type transistor 32. Transistor 31 is connected between first power supply node 8 and output node 4. Transistor 32 is connected between output node 4 and second power supply node 7. An input signal is applied from the input node 2 to the gates of the transistors 31 and 32. Switching circuit 5
Is composed of an N-channel MOS type transistor 50.

The potential lowering circuit 91 is formed by connecting three N-channel MOS type transistors 911, 912, 913 in series to the first power supply node 8, and the gate of the transistor 911 is connected to the first power supply node 8. Is
The gate of the transistor 912 is the transistors 911 and 9
12 and the gate of the transistor 913 is connected to the node between the transistors 912 and 913. The sense circuit 92 includes two inverters 921, 9
Including 22. The inverters 921 and 922 are connected in series between the transistor 913 and the gate of the transistor 50.

Next, the operation of the input circuit of FIG. 2 will be described. In the circuit of FIG. 2, since the transistors 911, 112, and 913 are connected in series in the potential drop circuit 91 of the potential determination circuit 9, the power supply potential received by the first power supply node 8 is the threshold voltage of each transistor. Decrease the total value. Then, in the sense circuit 92 of the potential discriminating circuit 9, when the power supply potential lowered by the potential lowering circuit 91 is equal to or higher than the threshold voltage of the inverter 921, the output signal of the inverter 921 becomes low level and this low level signal is output. The output signal of the received inverter 922 becomes high level. This turns on the transistor 50 of the switching circuit 5.

On the other hand, when the power supply potential lowered by the potential lowering circuit 91 is smaller than the threshold voltage of the inverter 921, the output signal of the inverter 921 becomes high level, and the inverter 922 receiving this high level signal. The output signal becomes low level. As a result, the transistor 50 of the switching circuit 5 is turned off.

The operation of the potential discriminating circuit 9 will be described below with an example of concrete numerical values. Here, the threshold voltages of the transistors 911, 912, 913 are 0.7V, respectively, and the threshold voltages of the inverters 921, 922 are 1/2 of the power supply potential.

When the power supply potential received by the first power supply node 8 is 5 volts, the power supply potential is set to the transistors 911, 9
Since the total of the threshold voltages of 12, 913 drops, the input potential of the inverter 921 is 5V- (0.7V
× 3) = 2.9V. Since the threshold voltage of the inverter 921 becomes 2.5 V which is 1/2 of the power supply potential, the output signal of the inverter 921 becomes low level and the output signal of the inverter 922 becomes high level.

When the power supply potential received by the first power supply node 8 is 3V, the power supply potential is transistor 911.
Since the total value of the threshold voltages of 912 and 913 is lowered, the input potential of the inverter 921 is 3V- (0.
7V × 3) = 0.9V. Since the threshold voltage of the inverter 921 becomes 1.5 V which is 1/2 of the power supply potential, the output signal of the inverter 921 becomes high level,
The output signal of the inverter 922 becomes low level.

As described above, in the potential discriminating circuit 9, the signal applied to the gate of the transistor 50 is set to the low level when the power supply potential received by the first power supply node 8 is equal to or higher than the predetermined level, while the first power supply node 8 is When the received power supply potential is not higher than the predetermined level, the signal applied to the gate of the transistor 50 is set to high level.

When the transistor 50 is turned on because the power supply potential received by the first power supply node 8 is equal to or higher than a predetermined level, the current drive capability ratio of the transistors of the input circuit is as follows: transistor 31: (transistor 32 + transistor 5).
0 + transistor 6) and the current drive capability ratio is set to 1: 3 (where transistor 31: transistor 32 is 1: 1), the threshold voltage of the input circuit is It becomes 1/4 of the power supply potential and TT
This is the value for the L input level. For example, the power supply potential is 5V
Then the threshold voltage is 1.25V.

On the other hand, when the transistor 50 is turned off because the power supply potential received by the first power supply node 8 is not higher than the predetermined level, the current drive capability ratio of the transistors of the input circuit becomes transistor 31: transistor 32. If it is set in advance to be 1: 1, the threshold voltage of the input circuit becomes 1/2 of the power supply potential, which is a value for the CMOS input level. For example, when the power supply potential is 3V, the threshold voltage is 1.5V.
Becomes

As described above, in the input circuit configured as described above, the ratio of the threshold voltage to the power supply potential is automatically switched according to the level of the power supply potential.

Second Embodiment Next, a second embodiment of the present invention will be described. Figure 3
FIG. 4 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a second embodiment. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Hereinafter, differences from the input circuit of FIG. 1 will be described.

Switching circuit 5 and transistor 6
Is not connected between the output node 4 and the second power supply node 7; instead, the switching circuit 5 and the P channel MO are connected between the output node 4 and the first power supply node 8.
The S-type transistor 60 is connected in series. The gate of transistor 60 is connected to input node 2.

Next, the detailed configuration of the input circuit of FIG. 3 will be described. FIG. 4 is a circuit diagram showing a detailed configuration of the input circuit of FIG. 3. In FIG. 4, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. The difference will be described below.

As described above, the transistor 50 and the transistor 6 are not connected between the output node 4 and the second power supply node 7. Instead, output node 4
And a first power supply node 8 are connected in series with a P-channel MOS type transistor 51 constituting the switching means 5 and a transistor 60. Transistor 5
The gate of 1 is connected to the output terminal of the inverter 922.

Next, the operation of the input circuit of FIG. 4 will be described. When the power supply potential received by the first power supply node 8 is equal to or higher than the predetermined level, the inverter 922 causes the transistor 5
The signal applied to the gate of 1 becomes low level, which turns off the transistor 51. Transistor 51
When is turned off, the current drive capability ratio of the transistors of the input circuit becomes transistor 31: transistor 32. If the current drive capability ratio is preset to be 1: 3, the threshold voltage of the input circuit becomes , 1/4 of the power supply potential, which is a value for the TTL input level. For example, when the power supply potential is 5V, the threshold voltage is 1.25V.
Becomes

On the other hand, when the power supply potential received by the first power supply node 8 is not higher than the predetermined level, the signal applied from the inverter 922 to the gate of the transistor 51 becomes low level, and the transistor 51 is turned on. Transistor 5
When 1 is turned on, the current drive input ratio of the transistors of the input circuit becomes (transistor 31 + transistor 51 + transistor 60): transistor 32, and this current drive capability ratio is 1: 1 (however, transistor 31: transistor 32 is 1: 3. The threshold voltage of the input circuit becomes 1/2 of the power supply potential, which is a value for the CMOS input level. For example, when the power supply potential is 3V, the threshold voltage is 1.5V.
Becomes As described above, in the input circuit configured as described above, the ratio of the threshold voltage to the power supply potential is automatically switched according to the level of the power supply potential.

Third Embodiment Next, a third embodiment of the present invention will be described. Figure 5
FIG. 6 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a third embodiment. In FIG. 5, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Hereinafter, differences from the circuit of FIG. 1 will be described.

Resistance circuit 10 is connected between the node between potential lowering circuit 91 and sense circuit 92 and second power supply node 7.

Next, the detailed configuration of the input circuit of FIG. 5 will be described. FIG. 6 is a circuit diagram showing a detailed configuration of the input circuit of FIG. 5. In FIG. 6, the same parts as those of FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. Hereinafter, differences from the circuit of FIG. 2 will be described.

In the potential discriminating circuit 9, the potential lowering circuit 9
The resistor circuit 10 is connected between a node between the first transistor 913 and the inverter 921 of the sense circuit 92 and the second power supply node. The resistance circuit 10 is formed of an element having a predetermined resistance value such as a diffusion resistance, a polysilicon resistance, or a transistor having a low resistance value.

Next, the operation of the input circuit shown in FIG. 6 will be described. The operation of this input circuit is basically the same as the operation of the input circuit of FIG. 2 except that the input voltage of the inverter 921 is not unstable by the action of the resistance circuit 10 due to external noise. When excess charges are accumulated in the parasitic capacitance of the inverter 921 due to external noise, the excess charges make the input voltage unstable. In this embodiment, the resistor circuit 10 discharges excess charges to the second power supply node 7. As a result, the input voltage is stabilized.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described. Figure 7
FIG. 8 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a fourth embodiment. In FIG. 7, parts corresponding to those in FIG. Hereinafter, differences from the input circuit of FIG. 3 will be described.

In the potential discriminating circuit 9, the potential lowering circuit 91
And the sense circuit 92 and the second power supply node 7
The resistor circuit 10 is connected between the and.

Next, the detailed structure of the input circuit of FIG. 7 will be described. FIG. 8 is a circuit diagram showing a detailed configuration of the input circuit of FIG. 7. In FIG. 8, the same parts as those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted. Hereinafter, differences from the input circuit of FIG. 4 will be described.

In the potential discriminating circuit 9, the potential lowering circuit 9
The resistance circuit 10 is connected between a node between the first transistor 913 and the inverter 921 of the sense circuit 92 and the second power supply node 7.

Next, the operation of the input circuit of FIG. 8 will be described. The operation of this input circuit is basically the same as the operation of the input circuit of FIG. 4, and as described in the description of the operation of the input circuit of FIG. 6, the resistor circuit 10 changes the input voltage of the inverter 921 to external noise or the like. Stabilize regardless of.

In this embodiment, the transistor 6 is an N-channel MOS type transistor, but it is not limited to this, and this transistor may be another transistor as long as it is controlled in response to an input signal. Good. Similarly, although the transistor 60 is composed of a P-channel MOS transistor, the transistor 60 is not limited to this, and another transistor may be used as long as it is controlled in response to an input signal.

Further, the potential lowering circuit 91 is composed of N-channel MOS transistors, but the present invention is not limited to this, and the potential lowering circuit 91 may be any other element as long as it lowers the potential like the N-channel MOS transistor. You may use. Similarly, although the sense circuit 92 is configured by an inverter, the sense circuit 92 is not limited to this, and the sense circuit 92 may use another element as long as it performs the same operation as the inverter. Further, although the switching circuit 5 is composed of P-channel and N-channel MOS transistors, other elements may be used as long as they perform the same operation as these transistors.

[0056]

According to the present invention as set forth in claim 1, when the potential discriminating means discriminates that the first power supply potential is equal to or higher than a predetermined level, the operation of the connecting means causes the inverter, the transistor and the connection to be established. A circuit formed of the means is formed, and when it is determined that the first power supply potential is not higher than or equal to the predetermined level, the circuit including only the inverter is formed. These circuits are different in threshold setting method, and it is possible to selectively form, on one chip, a circuit in which the ratio of the threshold to the level of the power supply potential is different according to the level of the power supply potential.

According to the second aspect of the present invention, when the potential discriminating means discriminates that the first power source potential is equal to or higher than the predetermined level, the circuit of only the inverter is formed by the operation of the connecting means. If it is determined that the first power supply potential is not equal to or higher than the predetermined level, a circuit including the inverter, the transistor, and the connecting means is formed.
These circuits have different threshold setting methods.
A circuit in which the ratio of the threshold value to the level of the power supply potential differs depending on the level of the power supply potential can be selectively formed over the chip.

According to the present invention of claim 3, in the potential discriminating means of claim 1, between the node between the potential lowering means and the discrimination result outputting means and the second power supply node. Since the resistance means is connected and the potential to be determined is stabilized by the resistance means, in addition to the effect described in claim 1, the potential determination means can accurately determine the level of the first power supply potential.

According to a fourth aspect of the present invention, in the potential discriminating means according to the second aspect, between the node between the potential lowering means and the discrimination result outputting means and the second power supply node. Resistance means is connected, and by this resistance means,
Since the potential to be discriminated is stabilized, the potential discriminating means can discriminate the level of the first power supply potential accurately, in addition to the effect described in the second aspect.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a detailed description of the input circuit of FIG.

FIG. 3 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a second embodiment.

FIG. 4 is a circuit diagram showing a detailed description of the input circuit of FIG.

FIG. 5 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a third embodiment.

6 is a circuit diagram showing a detailed description of the input circuit of FIG.

FIG. 7 is a circuit diagram showing a configuration of an input circuit which is a semiconductor integrated circuit according to a fourth embodiment.

8 is a circuit diagram showing a detailed description of the input circuit of FIG.

FIG. 9 is a circuit diagram showing a configuration of an input circuit which is a conventional semiconductor integrated circuit.

[Description of Reference Signs] 1 semiconductor chip 2 input node 3 inverter 4 output node 5 switching circuit 6,60 transistor 7 second power supply node 8 first power supply node 9 potential determination circuit 10 resistance circuit 91 potential drop circuit 92 sense circuit

Claims (4)

[Claims] 1. A semiconductor integrated circuit which is formed on one chip and outputs a signal according to the level of an input signal, comprising: a first power supply node for receiving a first power supply potential; and a second power supply potential. A second power supply node for receiving, an input node for receiving the input signal, an output node, an inverter connected between the input node and the output node, and a transistor controlled in response to the input signal. A potential discriminating means for discriminating whether or not the first power source potential received by the first power source node is equal to or higher than a predetermined level; and the first power source potential is equal to or higher than a predetermined level by the potential discriminating means. A semiconductor integrated circuit comprising: connecting means for connecting the transistor between the output node and the second power supply node when determined. 2. A semiconductor integrated circuit which is formed on one chip and outputs a signal according to the level of an input signal, comprising: a first power supply node for receiving a first power supply potential; and a second power supply potential. A second power supply node for receiving, an input node for receiving the input signal, an output node, an inverter connected between the input node and the output node, and a transistor controlled in response to the input signal. A potential discriminating means for discriminating whether or not the first power source potential received by the first power source node is equal to or higher than a predetermined level; and the first power source potential is equal to or higher than a predetermined level by the potential discriminating means. A semiconductor integrated circuit comprising: connecting means for connecting the transistor between the output node and the first power supply node when determined. 3. The potential discriminating means lowers the first power supply potential received by the first power supply node by a predetermined value, and the potential lowered by the potential lowering means is above a certain level. Between the potential drop means and the discrimination result output means, and a discrimination result output means for outputting a signal showing a discrimination result as to whether or not the first power source potential is equal to or higher than a predetermined level. 2. The semiconductor integrated circuit according to claim 1, further comprising a resistance unit having a predetermined resistance value connected between a node and the second power supply node. 4. The potential discriminating means reduces the first power supply potential received by the first power supply node by a predetermined value, and the potential lowered by the potential lowering means is above a certain level. Between the potential drop means and the discrimination result output means, and a discrimination result output means for outputting a signal showing a discrimination result as to whether or not the first power source potential is equal to or higher than a predetermined level. 3. The semiconductor integrated circuit according to claim 2, further comprising: a resistance unit having a predetermined resistance value connected between a node and the second power supply node.