JPH06140385A - Manufacture of high dielectric constant dielectric thin film - Google Patents

Abstract

PURPOSE:To obtain SrTiO3 dielectric thin film with a high dielectric constant by depositing amorphous SrTiO3 thin film on a ground at a temperature which is lower than a specific value and then performing laser annealing or rapid thermal annealing of the amorphous SrTiO3 thin film for crystallization. CONSTITUTION:A ground 1 is prepared and then SrTiO3 thin film 2 is deposited on it in amorphous shape at 400 deg.C or less. Then, the SrTiO3 thin film 2 which is deposited at a low temperature is annealed by laser annealing from the surface side and the amorphous SrTiO3 thin film 2 is crystallized, thus obtaining a crystalline SrTiO3 thin film 2a. Only the surface part can be rapidly heated by annealing using light and can also be cooled rapidly, thus reducing the reaction between the SrTiO3 thin film 2a and the ground 1. The crystallized and high-quality SrTiO3 thin film 2a show a high dielectric constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a high dielectric constant dielectric thin film, and more particularly to a method for producing a SrTiO ₃ -based high dielectric constant thin film.

A dielectric film has an insulating property and is used as a medium for transmitting an electric field. For example, a capacitor dielectric film of a dynamic random access memory (DRAM) or an insulated gate field effect transistor (IGF).
ET) used as a gate insulating film.

In these applications, it is desired that the dielectric film have a dielectric constant as high as possible. For a dielectric film in a semiconductor device, SiO ₂ or Si ₃ N ₄ has been usually used. However, the dielectric constants of these dielectric films are not necessarily high, and dielectric films having a higher dielectric constant are required.

[0004]

2. Description of the Related Art For example, in DRAMs, higher integration is being advanced. The memory cell area of the 64 Mbit memory currently under development is about 1.5.
In addition to being μm ² , in order to suppress an increase in power consumption,
Low voltage operation is also required. In order to accumulate a desired amount of charge with a small area and low voltage, it is desired to increase the capacitance of the capacitor obtained with the same substrate surface area.

In DRAMs, it is necessary to prevent soft errors due to α rays. Since the amount of charge generated by the incidence of α rays is constant, the capacitance of the DRAM capacitor cannot be significantly reduced even if the cell area is reduced. The amount of signal charge that can be stored in the capacitor is the product of the electrostatic capacity and the operating voltage.
It is necessary to further increase the capacitance.

The capacitance C of a capacitor is determined by the electrode area S of the capacitor, the film thickness d of the dielectric film, and the relative permittivity ε _{d of the} dielectric.
And have the following relationship. C = ε _o ε _d S / d (1) where ε _o is the dielectric constant of vacuum. In this specification, the term "dielectric constant" simply means the relative dielectric constant.

In order to increase the capacitance of the capacitor, the electrode area S may be increased, the film thickness d of the dielectric film may be decreased, and the relative dielectric constant ε _d of the dielectric may be increased. Conventionally, mainly
SiO ₂ or Si ₃ N ₄ is used as the dielectric, and the capacitance of the capacitor has been increased by increasing the electrode area S of the capacitor and decreasing the film thickness d of the dielectric film.

However, the thinning of the capacitor dielectric film is facing a physical limit. In the case of the Si ₃ N ₄ / SiO ₂ laminated film which has been conventionally used, it is 5 in terms of SiO ₂ film.
If the film thickness is reduced to nm or less, the leak current increases. Therefore, it is extremely difficult to make the dielectric film of the capacitor thinner.

Therefore, there is a demand for a capacitor dielectric film which can be thinned to 4 nm or less in terms of SiO ₂ film. Based on this request, PZT, CaTiO ₃ , SrTiO 3
₃ , PbTiO ₃ , BaTiO ₃ , Bi ₄ Ti ₃ O ₁₂ ,
High dielectric constant thin films such as Sr ₂ Bi ₄ Ti ₄ O ₁₈ have been developed. The SrTiO ₃ -based dielectric thin film will be described below.

The dielectric constant of the SrTiO ₃ thin film formed on the Si substrate by MOCVD (metal organic chemical vapor deposition) or the like is significantly lower than that of bulk SrTiO ₃ . This is the process of depositing the SrTiO ₃ -based high dielectric constant oxide,
SiO ₂ with a low dielectric constant (3.8 to 3.9) on the Si substrate surface
Is considered to be formed. To avoid this,
There has been proposed a method of interposing a barrier metal such as Pt having a reaction preventing effect with Si.

When a barrier metal layer is formed on a Si substrate, the barrier metal layer is conductive, so that the barrier metal layer must be separated in order to separate each element. If the barrier metal layer is patterned before forming the dielectric film, a step due to the barrier metal layer occurs.

Since the SrTiO ₃ system dielectric has low step coverage, it is difficult to sufficiently cover the steps of the barrier metal layer. When the dielectric film and the barrier metal layer are patterned together after forming the dielectric film, the side surface of the barrier metal layer is exposed. When an electrode layer is further formed on this,
It is necessary to form another insulating film to insulate the side surface of the barrier metal layer.

[0013]

As described above,
If an SrTiO ₃ -based dielectric film is to be formed on a Si substrate, the dielectric constant of the obtained SrTiO ₃ -based dielectric film will be lower than that in the bulk state. Attempts to obtain a high dielectric constant complicate the manufacturing process.

An object of the present invention is to have Sr having a high dielectric constant.
It is an object of the present invention to provide a novel method for producing a TiO ₃ -based dielectric thin film.

[0015]

The method for producing a high dielectric constant dielectric thin film of the present invention comprises a step of depositing an amorphous SrTiO ₃ -based thin film on a substrate at a temperature lower than 400 ° C., and And crystallization of the SrTiO ₃ -based thin film by laser annealing or rapid thermal annealing to obtain an SrTiO ₃ -based thin film.

[0016]

Function: Amorphous Sr is formed on the substrate at a temperature lower than 400 ° C.
When the TiO ₃ -based thin film is deposited, it is possible to sufficiently suppress the reaction between the SrTiO ₃ -based dielectric and the base during deposition.

However, amorphous SrTiO _{3 in} this state
The system dielectric thin film shows only a low dielectric constant. Amorphous S
A high dielectric constant can be obtained by crystallizing SrTiO ₃ by subjecting the rTiO ₃ -based thin film to laser annealing or rapid thermal annealing. According to laser annealing or rapid thermal annealing, Sr
It is possible to reduce the reaction between the TiO ₃ -based thin film and the base.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows SrTi according to a basic embodiment of the present invention.
A method for manufacturing an O ₃ -based thin film will be schematically described.

As shown in FIG. 1A, first, a base 1 is prepared, and an SrTiO ₃ type thin film 2 is deposited on the base 1 at a temperature of 400 ° C. or lower. The base 1 is, for example, Si
It is a substrate and has a conductive surface. Base 1 is S on the surface
It may be a Si substrate on which the i-compound thin film 4 is formed.

By depositing the SrTiO ₃ -based thin film 2 at a low temperature, it becomes possible to minimize the reaction between the SrTiO ₃ -based dielectric and the base 1. However, with such deposition, the SrTiO ₃ -based thin film 2 cannot be sufficiently crystallized and becomes amorphous.

In the present specification, "amorphous" means a state in which the crystallinity is not sufficient, and does not necessarily mean a completely amorphous state. For example, it includes a state in which a certain degree of low-order peak is obtained by X-ray diffraction, but other peaks are not obtained.

As shown in FIG. 1B, the SrTiO ₃ -based thin film 2 deposited at a low temperature is annealed from the surface side by laser annealing to form an amorphous SrTiO ₃ -based thin film 2.
Is crystallized to obtain a polycrystalline SrTiO ₃ -based thin film 2a.

Instead of laser annealing, rapid thermal annealing may be performed by infrared heating using an infrared lamp or the like. According to the annealing using such light, only the surface portion can be rapidly heated and the cooling can be performed quickly, so that the reaction between the SrTiO ₃ -based thin film 2a and the base 1 can be reduced. The crystallized and high-quality SrTiO ₃ -based thin film 2a exhibits a high dielectric constant.

Next, referring to FIG. 2, the film forming temperature is SrT.
The effect on the iO ₃ -based thin film and the effect on the interface will be described. A SrTiO ₃ thin film was formed on a Si substrate at various substrate temperatures, and the X-ray diffraction and the layer thickness of the SiO ₂ layer generated at the interface were measured. Figure 2 (A) shows the data of X-ray diffraction of the SrTiO ₃ film obtained and the film forming temperature of SrTiO ₃ film. The film forming temperature shows the case where the temperature is changed from 200 ° C. to 600 ° C. at 100 ° C. intervals.

As is apparent from the figure, the substrate temperature is 600
In the case of ° C, (100) peak and (200) peak are clearly observed. Further, the (110) peak is sharply generated.

When the substrate temperature is lowered to 500 ° C. and 400 ° C., the (100) peak disappears and the (200) peak also sharply decreases. The (110) peak has a sharp decrease in height, but is clearly present. Conversely, 600
The existence was almost unknown at a substrate temperature of ℃ (11
1) The peak is growing.

When the substrate temperature is set to 300 ° C., (200)
The peak disappears almost completely. The (110) peak is almost unchanged, and the (111) peak grows slightly. If the substrate temperature is further lowered to 200 ° C,
Although traces of the (110) peak and the (111) peak are recognized, most of the X-ray diffraction peaks disappear.

From the results of such X-ray diffraction, it is understood that it is preferable to set the substrate temperature to about 600 ° C. or higher in order to obtain the SrTiO ₃ thin film having good crystallinity. At 400 ° C. or lower, for example, 300 ° C., the obtained SrTiO ₃ thin film does not have sufficient crystallinity and becomes amorphous.

FIG. 2B shows (20) shown in FIG.
₃ is a graph showing the relationship between the peak intensity of 0) peak and the SiO ₂ layer thickness generated at the interface between the SrTiO ₃ thin film and the Si substrate.

When the (200) X-ray diffraction peak is present,
It is clearly shown that the SiO ₂ layer is generated.
Further, as the intensity of the (200) X-ray diffraction peak increases, the SiO ₂ layer thickness also increases almost linearly.

From these data, SrT was formed at the interface between the SrTiO ₃ thin film and the Si substrate without generating a SiO ₂ layer.
It can be seen that in order to deposit the iO ₃ thin film, the SrTiO ₃ thin film should be deposited at a substrate temperature that does not generate a (200) X-ray diffraction peak.

That is, at a low temperature of 400 ° C. or lower, SrTi
By depositing the O ₃ -based thin film in an amorphous state, it is possible to prevent generation of a SiO ₂ layer at the interface between the SrTiO ₃ thin film and the Si substrate.

A more specific embodiment of the present invention will be described below. As shown in FIG. 1, the SrTiO ₃ thin film 2 is deposited on the Si substrate 3 by rf magnetron sputtering. As a target, SrTiO formed by sintering
_{Use 3} powders.

The condition of sputtering is that high frequency power is 2
00 to 400 W, supply gas flow rate ratio Ar / O ₂ = 4/1,
The pressure inside the sputtering equipment is 1.2 Pa, the substrate temperature is 2
The temperature is set to 00 to 300 ° C., and a 100 nm-thick SrTiO ₃ thin film is deposited. SrTiO 3 deposited at a substrate temperature of 300 ° C
_{The 3} thin films exhibited a dielectric constant of ε = 45. This value is Sr
The dielectric constant of TiO ₃ is extremely low.

Thus, the SrTiO ₃ thin film deposited at a low temperature is annealed by using the laser annealing apparatus shown in FIG. In FIG. 3, the sample 10 is a heater 52.
It is mounted on the XY stage 51 equipped with. The laser light emitted from the multi-line continuous wave Ar laser 55 is
It is guided to the mirror 57 via the filter 56,
The sample 10 is irradiated with the reflected light, which is condensed by the lens 58. By driving the XY stage 51, the laser light is scanned on the sample.

The sample 10 on which the SrTiO ₃ thin film was formed was
It is heated to room temperature of 300 ° C. by the heater 52, irradiated with Ar laser light in the atmosphere, and laser-annealed. The irradiation conditions are, for example, a laser power of 0.5 W, a focal length of the condenser lens 58 of 25 mm, and a scan speed of 15.
The feed width is 0 mm / sec and the feed width is 2 μm.

Amorphous Sr formed at a substrate temperature of 300 ° C.
The dielectric constant of the TiO ₃ thin film was 45.
As a result of laser irradiation of the O ₃ thin film at a substrate temperature of 300 ° C., the dielectric constant was improved to ε = 250.

For comparison, polycrystalline SrT is formed by rf magnetron sputtering at a substrate temperature of 650 ° C.
The dielectric constant obtained when forming an iO ₃ thin film is ε = 6
It was 0.

The substrate temperature during laser irradiation is 400 ° C.
Then, the dielectric constant decreased to ε = 200. It is considered preferable that the substrate temperature during laser irradiation is not higher than the substrate temperature during SrTiO ₃ film formation.

As described above, the X-ray (200)
-Free SrTiO at low temperature ₃When a film is formed,
Si substrate and SrTiO₃SiO at the film interface₂There are layers
Not SrTiO₃A film can be obtained and this SrTiO 3
₃Promote crystallization by laser annealing the film
It is possible to increase the dielectric constant.

Although the case where the annealing process is performed by laser annealing has been described, the same effect can be expected by rapid thermal annealing. In addition, SrTiO ₃
When the film is laser annealed, the composition of the film after processing is
Ti becomes insufficient as compared with Sr. This phenomenon can be considered as follows.

SrTiO₃Is two binary oxides, Sr
O and TiO₂Can be thought of as a compound. But,
SrO and TiO₂Have different physical properties. SrO is T
iO ₂Higher melting point and higher boiling point (SrO mp 243
0 ° C, TiO₂M. p. 1855 ° C).

For this purpose, laser annealing or RTA
Then, when the surface temperature of the SrTiO ₃ film rises, TiO ₂ evaporates during the annealing process, and the film composition that should be SrTiO ₃ changes to lack Ti.

In order to prevent the composition of the film after annealing from deviating to Ti deficiency, Ti is previously determined by stoichiometry.
It is considered that the composition should be deposited at a low temperature with an excessive composition. Using SrTi _{1 + x} O ₃ powder target sintered and molded,
A SrTi _{1 + x} O ₃ film was rf-sputtered (low temperature deposition) on the Si substrate 3. Substrate temperature during sputtering is 3
00 ° C, gas flow ratio Ar / O ₂ = 4/1, pressure 1.2P
a, high frequency power is 200 to 400W. Deposited Sr
The film thickness of Ti _{1 + x} O ₃ was 100 nm. The composition of the deposited film is almost the same as the composition of the source.

Next, the sample was taken out into the atmosphere, and the SrTi _{1 + x} O ₃ film was heat-treated using the laser annealing apparatus shown in FIG. The laser is a multi-line continuous wave Ar ion laser, and after passing through a spatial filter, a heater is used.
The sample heated to 0 ° C. was irradiated. The irradiation conditions were such that the laser power was 0.5 W, the focal length of the condenser lens was 25 mm, the scan speed was 150 mm / sec, and the feed width was 2 μm.

FIG. 4 shows the relative permittivity ε _d of the obtained sample after laser annealing as the composition of the source or deposited film SrTi.
_It is shown as a function of the Ti amount (1 + x) with respect to Sr1 of _{1 + x} O ₃ .

FIG. 4 shows that when the composition (1 + x) is about 1.1,
It shows that the relative permittivity ε _d reaches the peak value. The peak value is about 290. The reason why ε _d sharply decreases in the region of (1 + x)> 1.2 may be that the rutile phase (TiO ₂ ) is precipitated in addition to the SrTiO ₃ phase.

The dielectric constant ε _d of the SrTi _{1 + x} O ₃ film before laser annealing is about 100. The crystallinity of the sample after laser annealing is found to be improved from the X-ray diffraction data. Significant improvement in ε _d is due to low temperature deposition SrTi _{1 + x} O ₃
It is considered that the crystallinity of the film was improved by laser annealing. It is considered possible to use RTA instead of laser annealing.

Also, the low temperature deposition Sr of the previously described embodiment
Compared with the dielectric constant (250) of the TiO ₃ film after laser annealing, the ε _d (290) after laser annealing of this low temperature deposited Ti-excessive SrTi _{1 + x} O ₃ film was improved because it evaporated during the annealing process. It is considered that the effect of supplementing TiO ₂ in advance appeared.

Now, the highly reactive SrTiO ₃ -based thin film 2
In order to more completely prevent the chemical reaction (SiO ₂ formation) during the deposition of the film with the Si substrate 3 or during the heat treatment process, it is effective to interpose an appropriate Si chemical thin film 4 as a buffer layer. The Si compound has good compatibility with Si and is likely to be a relatively stable compound. Appropriate S
Metal silicide and bismuth silicate can be used as the i compound.

As a metal for silicide, a refractory metal which forms a relatively stable compound with Si, such as Pt or T, is used.
Preferred is a, Ti or W. When these metal layers are simply deposited as a barrier metal on a Si substrate and patterned for electrical isolation, the SrTi formed thereon is formed.
Since the O ₃ high dielectric constant insulating film has a poor step coverage, it is difficult to sufficiently cover the side surface of the barrier metal layer.

Then, there is a problem that the side surface of the barrier metal layer needs to be further covered with another insulating film.
Further, even if the SrTiO ₃ high dielectric constant insulating film was deposited on the barrier metal layer, the dielectric constant of the entire sample did not become so large.

In this embodiment, after the barrier metal layer is once deposited, it is removed by dry etching or the like, leaving only the metal silicide layer formed at the interface between the Si substrate and the barrier metal. The thickness of these metal silicide layers is extremely thin, 10 A or less, and the presence thereof can almost completely suppress the reaction between the SrTiO ₃ -based thin film and the Si substrate.

FIG. 5 is a sectional view showing the main part of the step of forming the high dielectric constant SrTiO ₃ thin film 8 on the platinum silicide layer 6. As shown in FIG. 5 (A), Pt is formed by rf magnetron sputtering using the Si substrate 3 as a base.
Deposit layer 5. The sputtering was performed using a Pt target under the conditions of high frequency power of 200 to 400 W, Ar atmosphere (pressure 0.5 Pa), and Si substrate temperature of room temperature.
The Pt layer 5 has a thickness of about 10 nm. In this process, the platinum silicide layer 6 is formed at the interface between the Si substrate 3 and the Pt layer 5.

Next, as shown in FIG. 5B, the sample is transferred to an etching apparatus, and HBr gas is flown to perform plasma etching to remove the Pt layer 5 once deposited on the Si substrate 3. The platinum silicide layer 6 functions as an etching stopper, and the platinum silicide layer 6 is exposed on the surface of the Si substrate 3. The platinum silicide layer 6 has a thickness of 10 A or less.

The sample 10 having the silicide layer formed in this manner was used as the vacuum chamber 1 of the MONBE apparatus shown in FIG.
2 Installed on the central susceptor 14. A heater 28 is provided in the susceptor 14 to heat the sample to a desired temperature.

In the MOMBE apparatus schematically shown in FIG. 6, the chamber 12 has a reflection high energy electron diffraction (R
Electron gun 22 and screen 23 for performing HEED)
Are provided corresponding to the position of the susceptor 14. Next to the susceptor 14, a film thickness meter 25 such as a crystal oscillator is also arranged. Further, a nuclear quadrupole mass spectrometer 26 is provided behind the susceptor 14.

In the chamber 12, vessels 16a and 16b, a Knudsen cell 20, and a source gas supply source are provided.
A gas nozzle 18 having an ECR (electron cyclotron resonance) structure is connected.

Further, each vessel 16 is provided with a heater 17 so that the inside of the vessel can be heated to a desired temperature. Although not shown, a vacuum exhaust system is connected to the chamber 12 so that the chamber 12 can be exhausted to a desired degree of vacuum.

As shown in the figure, Sr uses the elemental metal contained in the K (Knudsen) cell 20 as a source,
The i-source is housed in the vessel 16b, and the metal complex tetraisopropoxy titanium Ti (i-
OC ₃ H ₇ ) ₄ was used.

When this metal complex was used, it was mixed with the heater by 5
It is heated to 0 ° C. and introduced into the growth chamber with 2 sccm of Ar gas. Oxygen is supplied from an oxygen plasma using an electron cyclotron resonance (ECR) structure. The Bi source vessel 16a contains triphenylbismuth Bi (p
h) ₃ is contained, but is not used in this embodiment.

A substrate (sample) temperature of 300 ° C., an oxygen partial pressure of 1 to 9 × 10 ⁻⁵ Torr, and a K cell temperature of 480 ° C. were used.
A TiO ₃ film 7 was deposited. The film thickness control was performed using a quartz oscillator that was calibrated in advance. Obtained SrTiO
The relative permittivity ε _d of the sample including the ₃ film 7 was 55, but SiO was found at the interface between the platinum silicide layer 6 and the SrTiO ₃ film 7.
₂ is not generated.

Next, the sample was taken out into the atmosphere, and the SrTiO ₃ thin film 7 was irradiated with the laser beam 8 as shown in FIG. 5D to perform laser annealing. The laser annealing may be performed using a laser annealing device as shown in FIG.

Laser annealing was performed at a sample temperature of 300.
℃, laser power 0.5W, scanning speed 15
The condition was 0 mm / sec and the feed width was 2 μm. The obtained SrTiO ₃ film 7 was crystallized (higher quality), and when the dielectric constant of the sample containing the SrTiO ₃ film 7 was measured, the relative dielectric constant ε _{d of the} dielectric region was 320.

This value is further improved as compared with the case of direct film formation on the Si substrate 3 (after low temperature deposition, laser annealing) (ε _d = 250) described with reference to FIG. I understand.

When Ti is used as the silicide metal, the titanium silicide layer is more effective because it also acts as an evaporation supplement source of the TiO ₂ component generated in the laser annealing process as described above.

Next, an example using bismuth silicate as a buffer layer different from the metal silicide layer 6 will be described.
The Si substrate 3 is introduced into the sample position of the MOMBE apparatus shown in FIG. In this embodiment, triphenylbismuth and Bi (ph) ₃ are used as the Bi raw material. Bi (ph) ₃ in the vessel 16a is heated to 120 ° C., and the Bi complex is introduced into the chamber 12 using Ar gas as a carrier.

At this time, by keeping the Si substrate 3 at 650 ° C. and reacting with oxygen ECR plasma, S
Bi (ph) ₃ generated on the i-substrate 3 by thermal decomposition
And Si and oxygen are combined, and a bismuth silicate Bi ₁₂ SiO ₂₀ film is deposited on the Si substrate 3. The film thickness was 10 to 20A.

Next, the supply of Bi (ph) ₃ was stopped, the sample temperature was lowered to 300 ° C., and Ti (i) heated to 50 ° C.
Ar of 2sccm the -OC ₃ H _{7) 4} for vessel 16b
To introduce the Ti complex into the chamber 12.

Oxygen ions are generated by ECR plasma,
Simultaneously, when the Sr molecular beam is emitted from the K cell (480 ° C.), the SrTiO ₃ film is formed on the Bi ₁₂ SiO ₂₀ film. The film thickness was about 10 nm.

The Bi ₁₂ SiO ₂₀ film is a Si compound formed by reacting with the base and is well compatible with the Si substrate.
Moreover, since the film thickness is sufficiently thin, even if the SrTiO ₃ film is deposited on the film, there is little problem in step coverage.

The obtained SrTiO 3₃The membrane to the device of Figure 3
Laser annealing under the same conditions as before will crystallize
To improve the quality. When the dielectric constant of this sample is measured,
Relative permittivity ε of electric field_dOf about 290 was obtained.
Bi₁₂SiO₂₀/ SrTiO ₃SiO on the interface₂The existence of
Not observed.

As described above, in addition to the low temperature deposition of the SrTiO ₃ system thin film and the optical annealing treatment, the Si substrate and the S
It is understood that the formation of SiO ₂ can be more completely suppressed and the dielectric constant can be more effectively improved by interposing a sufficiently thin buffer layer of a Si compound between the rTiO ₃ -based thin films.

As the Si base, not only single crystal but also polycrystal can be used. Moreover, Sr of SrTiO ₃
By substituting a part of at least one of Ba and Ca, the dielectric constant can be further improved.

Next, with reference to FIG. 8, a capacitor of a planarized stack type memory cell using a SrTiO ₃ dielectric thin film obtained by a two-step processing method of low temperature deposition and laser annealing will be described.

A field oxide film 32 is selectively formed on the surface of the p-type Si substrate 31. Two MOSFEs are formed in the active area surrounded by the field oxide film 32.
T is formed. That is, the polycrystalline gate electrodes 33a and 33a are formed on the region to be the channel via the gate oxide film.
b is formed, and n ⁺ type regions 34 serving as source regions and n ⁺ type regions 35a and 35b serving as drain regions are formed on both sides thereof.

An n ⁺ type polycrystalline Si region 37 functioning as a diffusion source is formed on the n ⁺ type regions 35a and 35b,
n ⁺ -type region 34 on the even n ⁺ -type polycrystalline Si regions 38 are formed. A metal electrode 39 serving as a data line is formed on the polycrystalline Si region 38.

After covering the metal electrode 39 with an insulator, an interlayer insulating film 41 is formed, and an opening is provided on the polycrystalline Si region 37. An electrode 43 serving as an extraction electrode is provided in this opening.
Are buried and are flattened together with the surface of the interlayer insulating film 41.

A Pt layer 45 to be a lower electrode is selectively formed on the flattened surface, and SrTiO ₃ is formed on the Pt layer 45.
The capacitor dielectric thin film 46 formed in 1. is formed. A metal electrode 48 serving as a plate electrode is formed on these.

That is, in the illustrated structure, MOSFETs are formed on both sides of the central source region 34 and each M
The OSFET is connected to the capacitor connected to the plate electrode 48. These capacitors have a high capacitance because the capacitor dielectric film is made of a SrTiO ₃ -based dielectric having an extremely high dielectric constant.

Since a relative permittivity that is about two orders of magnitude higher than that of the conventional Si ₃ N ₄ / SiO ₂ dielectric is obtained, the required accumulated charge amount can be secured even with a small-area two-dimensional capacitor. Therefore, the cell structure can be simplified.

Although the configuration example of the DRAM has been described, the high dielectric constant thin film described above can be used as a gate insulating film of a thin film transistor (TFT), an electroluminescent (EL) element insulating film, or the like.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.

[0084]

As described above, according to the present invention,
It is possible to form a high-quality, high-dielectric-constant SrTiO ₃ -based thin film.

Even when the SrTiO ₃ thin film is formed on the Si substrate, generation of SiO ₂ can be suppressed and a high dielectric constant can be obtained. As a result, megabit integrated DRAM
For example, it is possible to form a capacitor having a large amount of accumulated charge even in a small area on a high-density mounted Si element.

[Brief description of drawings]

FIG. 1 is a sectional view showing a basic embodiment of the present invention. Figure 1
1A shows a step of depositing a SrTiO ₃ -based thin film at a low temperature on a base, and FIG. 1B shows a step of laser annealing the SrTiO ₃ -based thin film deposited at a low temperature.

FIG. 2 is a graph showing the influence of the film forming temperature of a SrTiO ₃ thin film. FIG. 2A is an X-ray diffraction data, FIG.
(B) shows the relationship between the (200) peak intensity of X-ray diffraction and the production of SiO ₂ on the Si substrate surface.

FIG. 3 is a perspective view showing a configuration of a laser annealing apparatus.

FIG. 4 SrT after laser annealing with respect to Ti amount (1 + x) when laser annealing of SrTi _{1 + x} O ₃ thin film
₃ is a graph showing the relationship of relative permittivity ε _d of a sample containing an iO ₃ -based thin film.

FIG. 5 is a cross-sectional view showing a process of forming a SrTiO ₃ thin film on a platinum silicide buffer layer according to an embodiment of the present invention.

FIG. 6 is a sectional view showing a schematic configuration of a MONBE device.

FIG. 7 is a cross-sectional view showing a configuration example of a flattening stack cell using a high dielectric constant SrTiO ₃ thin film.

[Explanation of symbols]

1 Underlayer 2 SrTiO ₃ system thin film 3 Si substrate 4 Si compound thin film 5 Pt layer 6 Platinum silicide layer 7 SrTiO ₃ system thin film 8 Laser light

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/04 C 8427-4M

Claims (10)

[Claims] 1. At a temperature lower than 400 ° C. on the substrate (1)
Amorphous SrTiO ₃A step of depositing a thin film (2) of the system, and the amorphous SrTiO 3₃Laser annealing of thin film (2)
Or rapid thermal annealing to crystallize,
SrTiO₃High dielectric including a step of obtaining a thin film (2a)
Method of manufacturing a dielectric thin film. 2. The substrate (1) is a Si substrate (3), and the depositing step is performed at a temperature at which a SiO ₂ layer is not substantially generated at the interface between the SrTiO ₃ -based thin film and the Si substrate. A method for producing a high-k dielectric thin film as described. 3. The method for producing a high dielectric constant dielectric thin film according to claim 1, wherein the underlayer (1) has a Si compound thin film (4) on its surface. 4. The method for producing a high dielectric constant dielectric thin film according to claim 3, wherein the Si compound thin film (4) is a metal silicide layer or a bismuth silicate (Bi ₁₂ SiO ₂₀ ) layer. 5. The method further comprises the steps of depositing a metal layer on a Si substrate (3) and forming a metal silicide layer at the interface, and removing the metal layer to prepare the base (1). The method for producing a high dielectric constant dielectric thin film according to claim 1. 6. The method for manufacturing a high dielectric constant dielectric thin film according to claim 5, wherein the metal layer is made of at least one selected from the group consisting of Pt, Ta, Ti and W. 7. The high dielectric constant dielectric thin film according to claim 1, wherein the SrTiO ₃ -based thin film (2) has a composition in which a part of Sr is substituted with at least one of Ba and Ca. Method. 8. The SrTiO ₃ -based thin film (2) comprises Sr
The method for producing a high dielectric constant dielectric thin film according to any one of claims 1 to 7, which has a Ti excess composition containing 1 to 1.2 atoms of Ti per atom. 9. An electron having a Si substrate (3), a silicide thin film (4) formed on the Si substrate, and an SrTiO ₃ -based high dielectric constant thin film (2a) directly formed on the silicide thin film. parts. 10. A Si substrate (3), a bismuth silicate layer (4) formed on the Si substrate, and a SrTiO ₃ -based high dielectric constant thin film (2a) directly formed on the bismuth silicate layer. And an electronic component having.