JPH0614015A - Time division multiplexer - Google Patents

Abstract

PURPOSE:To improve the utilization efficiency of a data bus of a master station by not using the data bus of the master station for multiple access through a high speed digital private line and for communication between branch stations at a branching circuit. CONSTITUTION:Transmission data (1), (3) from a line are stored in a transmission data buffer 13 via a transmission/reception section 15. A data bus output control section 14 sets the address of the buffer 13 to its address and a data bus input control section 10 sets the address of a reception data buffer 12 to its address simultaneously. Moreover, the loopback bit 11 of the address of the control section 10 is set. Thus, a loopback control section 16 does not output the data of the address of the buffer 13 to a data bus 9, but loops back the data and transfers the data to the buffer 12. Then the data of the address in the buffer 13 are stored in the address of the buffer 12. Consequently, the data B of the buffer 12 are outputted to a channel (1) and data A are outputted to a channel (3). Thus, the operating efficiency of the data bus of the master station is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication network in which a master station and a plurality of branch stations are connected by a high-speed digital line and communication is performed by a multiple access line or a branch line, not only between the master station and the branch stations but also between the branch stations. The present invention also relates to a time division multiplexer.

Communication between branch offices in such a communication network is carried out via a master station without providing a line directly connecting the branch offices.

[0003]

2. Description of the Related Art Conventionally, in such communication between branch offices, a master station temporarily outputs data received by an interface unit to a data bus in a device, and the interface unit receives the data from the data bus again and the line side I am trying to output to.

FIG. 8 shows the configuration of a conventional time division multiplexer. In the figure, 200 is a parent station (C station), 201 is a branch station (A station), 202 is a branch station (B station), and 203 is a time division multiplexing apparatus C (time division multiplexing apparatus of C station 203). Two
Reference numeral 04 is a line interface unit, 205 is another interface (an interface with the PBX, etc.), and 206 is a data bus.

In the time division multiplexer C (203),
Reference numeral 210 is a data bus input control unit that determines an address of a reception data buffer 212 (described later).
A data bus output control unit 211 determines an address of a transmission data buffer 213 (described later).
Reference numeral 212 denotes a receive data buffer, which is a data bus 20.
The data sent from 6 is stored and sequentially output to the line as channel data (slot data) in the order of addresses. A transmission data buffer 213 stores the data of the channel (slot) from the line in order of address and outputs the data to the data bus 206. Reference numeral 214 is a transmission / reception unit. A bus control unit 215 outputs the data in the transmission data buffer 213 to the data bus 206 and transfers the data from the data bus 206 to the reception data buffer 212. Two
Reference numeral 06 is a data bus, and 220 is a branching device. Reference numeral 221 denotes a time division multiplexer A (time division multiplexer of the branch A201), and 222 is a time division multiplexer B (time division multiplexer of the branch 202).

In the time division multiplexing apparatus C (203) shown in the figure, a control unit (CPU) for controlling the whole, a control bus and the like are omitted. D placed between each station and the line
The SU (Digital Service Unit) is also omitted.
A PBX, a terminal device, etc. are connected to each station.

The operation of the configuration shown in the figure will be described for the case where communication is performed between the A station (201) and the B station (202). The data bus output control unit 211 has a transmission data buffer 213.
(For example, the address of the transmission data buffer 213 is set to the address 1 of the data bus output control unit 211, and the transmission data buffer 21 is set to the address 3).
Set the address of 3). Then, the data bus input control unit 210 sets the address of the reception data buffer 213 (for example, the address of the transmission data buffer is set to the address 1 and the address of the transmission data buffer is set to the address 3).

Then, the bus control unit 215 takes out the address (data of channel A) of the transmission data buffer 213 according to the information stored in the data bus output control unit 211 and the data bus input control unit 210, and outputs it to the data bus 206. The data is output, and then the data is input from the data bus and written to the address of the reception data buffer 212. Similarly, the data at the address of the transmission data buffer 213 (channel B data) is taken out and written to the address of the reception data buffer.

As a result, the data transmitted from the station B (202) is added to the channel (slot) of the station A from the transmitter / receiver 214, and the channel (slot) of the station B is added.
The data transmitted from the A station (201) is added to and is output to the line.

[0010]

In the conventional time division multiplexing system, the data bus must be used in the master station even in the case of communication between the branch stations in the multiple access line and the branch line. Therefore, the use of the data bus for performing other processing was limited in the master station accordingly.

It is an object of the present invention to provide a time division multiplexing apparatus capable of communicating via a master station without using a data bus in inter-branch communication.

[0012]

FIG. 1 is a basic configuration of the present invention.
Indicates (1). The figure shows the basic configuration for communication between branch stations by providing a loopback bypass path at the master station.

In the figure, 1 is a master station (C station), 2 is a branch station (A station), and 3 is a branch station (B station). In the master station 1 (station C), 4 is a time division multiplexer C. In the A station (2), 5 is a time division multiplexer A. 6 at station B (3)
Is a time division multiplexer B.

In the time division multiplexer 4, 7 is a line interface unit, 8 is another internal device (PBX interface, etc.), and 9 is a data bus. In the line interface unit 7, 10 is a data bus input control unit,
For example, it is configured by a RAM and stores the address of a reception data buffer that stores the data sent from the data bus 9. Further, it has a loopback bit for instructing loopback of data for inter-branch communication (for example, address 1 designates the address (data of A) of the receive data buffer, and address 3 designates the address of the transmit data buffer 3 ( (Data of A) is specified, and turn-back bits of address 1 and address 3 are turned on). Reference numeral 11 is a folding bit. Reference numeral 12 is a receive data buffer, which stores the data sent from the data bus 9 under the control of the data bus input control unit 10,
The address is sequentially read to the line side. Thirteen
Is a transmission data buffer for sequentially storing the data transmitted from the line in the order of addresses and reading it to the data bus 9 under the control of the data bus output control unit 14. Reference numeral 14 is a data bus output control unit, which is composed of a RAM and stores the address of the transmission data buffer 13 (for example, the address (data of A) of the transmission data buffer 13 is stored in the address 1 and the address is stored). 3 stores the address (data of B) of the transmission data buffer 13). Reference numeral 15 is a transmission / reception unit, and 16 is a loopback control unit. Reference numeral 17 is a branching device.

The operation of the configuration shown in the figure will be described later (see operation).
FIG. 2 shows the basic configuration (2) of the present invention. The figure shows the basic configuration when the call is returned at the master station.

In the figure, the same reference numerals as in FIG. 1 represent the same parts. In the figure, the configurations of the data stored in the data bus output control unit 14 and the data bus input control unit 10 are different.

For example, the data bus output control unit 14 stores the address (data A) of the transmission data buffer 13 at address 1 and the address (data B) of the transmission data buffer 13 at address 3, for example. . Then, the data bus input control unit 10 has the same address as the data bus output control unit 14 at the same address as the data bus output control unit 1.
The same address as the address of the transmission data buffer set by 4 is set. For example, the address 1 stores the address of the reception data buffer 12 (data A), and the address 3 stores the address of the reception data buffer 12 (data B). Then, the folding bits of the address 1 and the address 3 of the data bus input control unit 10 are turned on.

The operation of the configuration shown in the figure will be described later (see operation).
FIG. 3 shows the basic configuration (3) of the present invention. The figure shows the basic configuration when the call is returned at the master station.

In the figure, the same numbers as in FIG. 1 represent the same parts. The drawing is different from FIG. 1 in that an all-one sending unit 16 ′ is provided, and the configurations of data stored in the data bus output control unit 14 and the data bus input control unit 10 are different.

In the configuration shown in the figure, the data bus input control section 10 has information for setting all 1s in the reception data buffer 12. Then, the data bus output control unit 14 stores, for example, the address (data A) of the transmission data buffer 13 at address 1 and the address (data B) of the transmission data buffer 13 at address 3. The data bus input control unit 10 has the same address as the data bus output control unit 14 at the same address.
Set the same address as the send data buffer address set by. For example, the address 1 stores the address of the reception data buffer 12 (data A), and the address 3 stores the address of the reception data buffer 12 (data B). Then, the folding bits of the address 1 and the address 3 of the data bus input control unit 10 are turned on, and the all 1 setting bit of the address 3 is set to 1.

The operation of the configuration shown in the figure will be described later (see operation).

[0022]

The operation of the basic configuration (1) of FIG. 1 will be described. The figure is
Shown is the case of communication between station A (2) and station B (3). Station A
(2) uses channels (slots), and station B (3) uses channels (slots).

The transmission data from the line is sequentially stored in the addresses of the transmission data buffer 13 in the order of slots via the transmission / reception unit 15. That is, the channel (A data) is stored in the address, and the channel (B data) is stored in the address. On the other hand, the data bus output control unit 14 sets the address of the transmission data buffer 13 at the address 1 and sets the address of the transmission data buffer 13 at the address 3.
Set the address of. At the same time, the data bus input control unit 10 sets the address of the received data buffer 12 at address 1 and the address of the received data buffer 12 at address 3. In addition, the data bus input control unit 10
The wrap bit of addresses 1 and 3 of
Set "1").

As a result, the loopback control unit 16 does not output the address of the transmission data buffer 13 and the address data to the data bus 9, but loops back the data and transfers it to the reception data buffer 12. Then, the data at the address of the transmission data buffer 13
The data of the address of the transmission data buffer 13 is stored in the address of the reception data buffer 12. Therefore, via the transceiver 15,
The address data (B data) of the reception data buffer 12 is output to the channel (slot), and the address data (A data) is output to the channel (slot).

The transmission data from the C station (1) is sent to the branching device 17
The channel (slot) is sent to station A (2), and the channel (slot) is sent to station B (3). The operation of the basic configuration (2) of FIG. 2 will be described.

The figure shows a case where the A station (2) and the B station (3) respectively perform loopback communication at the C station (1) (the loopback communication is usually performed for a device test). The transmission data from the line is sequentially stored in the addresses of the transmission data buffer 13 in the order of slots via the transmission / reception unit 15. That is, the channel (A data) is stored in the address, and the channel (B data) is stored in the address. And
The data bus output control unit 14 sets the address of the transmission data buffer 13 at address 1 and the address of the transmission data buffer 13 at address 3. At the same time, the data bus input control unit 10 sets the address of the received data buffer 12 at address 1 and the address of the received data buffer 12 at address 3. Further, the return bits of the address 1 and the address 3 of the data bus input control unit 10 are turned on (for example, "1" is set).

As a result, the loopback control section 16 does not output the address of the transmission data buffer 13 and the address data to the data bus 9, but loops back the data and transfers it to the reception data buffer 12. Then, the data of the address of the transmission data buffer 13 is stored in the address of the reception data buffer 12, and the data of the address of the transmission data buffer 13 is stored in the address of the reception data buffer 12. Therefore, the address data (data A) of the reception data buffer 12 is output to the channel (slot) and the address data (B data) is output to the channel (slot) via the transmitting / receiving unit 15.
Is output to.

The transmission data from the C station (1) is sent to the branching device 17
The channel (slot) is sent to station A (2), and the channel (slot) is sent to station B (3). The operation of the basic configuration (3) in FIG. 3 will be described.

In the figure, station A (2) performs loopback communication (loopback test), and station C (1) outputs to station B (3) all 1 bits indicating that it is under test. Indicates.
The transmission data from the line is sequentially stored in the addresses of the transmission data buffer 13 in the order of slots via the transmission / reception unit 15. That is, the channel (A data) is stored in the address, and the channel (B data) is stored in the address. Then, the data bus output control unit 14 sets the address 1
The address of the transmission data buffer 13 is set with, and the address of the transmission data buffer 13 is set with address 3. At the same time, the data bus input control unit 10 sets the address 1
The address of the received data buffer 12 is designated by and the address of the received data buffer 12 is designated by address. Further, the return bit of the address 1 and the address 3 of the data bus input control unit 10 is turned on (for example, "1" is set), and the all 1 setting bit of the address 3 is turned on.

As a result, the loopback control section 16 does not output the data of the address of the transmission data buffer 13 to the data bus 9, but loops back the data and transfers it to the reception data buffer 12. Then, the data of the address of the transmission data buffer 13 is stored in the address of the reception data buffer 12. Further, the data of the address of the transmission data buffer 13 is not output to the data bus 9, and the address of the reception data buffer 12 is set to all 1. Then, the address data (data A) of the reception data buffer 12 is output to the channel (slot) and the address data (all 1s) is output to the channel (slot) via the transmission / reception unit 15. C
The transmission data from the station (1) is branched by the branching device 17, the channel (slot) is sent to the A station (2), and the channel (slot) is sent to the B station (3).

In the above description, the case where the return information and the all-1 setting information are provided in the data bus input control section has been described, but they may be provided in the data bus output control section.

[0032]

FIG. 4 shows an embodiment of the line interface section of the present invention. In the figure, 60 is a line interface unit,
61 is an internal data bus, 62 is a data bus input control R
AM and 63 are data bus output control RAMs, which correspond to the data bus input control unit and the data bus output control unit in FIGS. 1, 2 and 3, respectively. Reference numeral 64 is a reception data buffer, and 65 is a transmission data buffer. 66
Is a data bus input section, which is composed of a buffer, for example, a low level signal,
Is output to the folding unit 68. 67 is a data bus output unit, which is composed of a buffer,
For example, the data of the transmission data buffer 65 is output to the in-device data bus 61 by a low level signal and is not output at a high level. Reference numeral 68 denotes a loopback unit (corresponding to the loopback control unit in FIGS. 1, 2, and 3), which loops back the data in the transmission data buffer at the address where the loopback bit is set in the data bus input control RAM 62 and receives the received data. The data is transferred to the buffer 64. Reference numeral 69 denotes an all-one sending unit which sets all-1s in the slot of the address where the all-sending bit is set in the data bus input control unit RAM 62 in the return test.

The operation of the configuration shown in the figure will be described later. FIG. 5 shows a data bus output control RAM and a data bus input control RA of the present invention.
An example of M is shown (the figure shows an example in the case of performing communication between A station and B station).

(A) shows the data structure of the data bus output control RAM, and (b) shows the data structure of the data bus input control RAM. In (a), the address of the data bus output control RAM corresponds to the slot address of the in-device data bus 61, and the address of the transmission data buffer is stored as internal data. For example, the address 9 of the transmission data buffer is stored in the address 2, and the address 19 of the transmission data buffer is stored in the address 4.

Each address has a transmission valid bit (for example, 0 is invalid and 1 is valid). By disabling the transmission valid bit, the data bus output unit 67 shown in FIG.
Therefore, the data of the address is prevented from being input to the in-device data bus 61.

In (b), the data bus input control RAM
Corresponds to the slot address of the in-device data bus 61, and stores the address of the reception data buffer as internal data. For example, the address 2 stores the address 19 of the reception data buffer, and the address 4 stores the address 9 of the reception data buffer.

The data bus input control RAM (b) is all
It has a '1' sending bit (for example, 0 is invalid, 1 is valid), a return bit (for example, 0 is invalid, 1 is valid), and a reception valid bit (0 is invalid, 1 is valid). All 1
All 1s are set in the channel (slot) of the address of the reception data buffer in which the transmission bit 1 is designated. The data of the transmission data buffer is folded back to the channel (slot) of the address of the reception data buffer in which the folding bit 1 is designated, and is stored in the reception data buffer without being output to the data bus. No data is input from the in-device data bus input unit 66 to the address of the reception data buffer having the reception valid bit 0.

The operation of FIG. 4 will be described with reference to FIG.
In the transmission data buffer 65, the data from the line is sequentially written into the addresses in the order of slots. Then, the data of the address of the transmission valid bit 1 (valid) in the data bus output control RAM is output to the in-device data bus 61 via the data bus output unit 67, and is transmitted to the transmission data buffer 65 of the transmission bit 0 (invalid). The address is not output to the in-device data bus 61. Data bus input control RA
No data is input from the in-device data bus 61 to the address of the receive data buffer 64 with the receive valid bit 0 (invalid) of M62, and the data of the address of the transmit data buffer 65 in which the loopback bit is set is looped back. The data is input to the unit 68, selected by the loopback unit 68, and transferred to the reception data buffer 64 via the all-1 setting unit 69. At this time, if the all 1 selection bit 1 (valid) of the data bus input control RAM 62 is set, all 1 is set to that address of the reception data buffer 64.

It is now assumed that slot 9 (channel 9) is station A and slot 19 (channel 19) is station B. Therefore, the data of station A (data A) is stored at address 9 of the transmission data buffer 65, and the data of station B (data B) is stored at address 19 of the transmission data buffer 65. The data at address 9 of the transmission data buffer 65 is
Since the transmission valid bit is invalid in the data bus output control RAM 63, it is not output to the in-device data bus 61 in the data bus output section 67, and the folding bit is valid at that address in the data bus input control RAM 62. Therefore, the folding part 68
Is selected by and input to the all-1 sending unit 69. Since the all 1 setting bit is invalid, all 1 is not output from the all 1 sending unit 69, and the data of address 9 of the transmission data buffer 65 is designated by the same address of the data bus input control RAM 62. It is written in the address 19 of the reception data buffer 64. At this time, since the reception valid bit of the data bus input control RAM 62 is invalid, the data from the internal data bus is not written in the reception data buffer 64. Similarly, the data (data A) at address 19 of the transmission data buffer 65 is written at address 9 of the reception data buffer 64.

FIG. 6 shows the data bus output control RAM of the present invention.
An embodiment (2) of a data bus input control RAM is shown. The figure shows the data structures of the data bus output control RAM and the data bus input control RAM when both the A station and the B station perform a bidirectional loopback test at the C station. Station A has 9 slots, and station B has 19 slots.

(A) shows a data bus output control RAM data structure, and (b) shows a data bus input control RAM data structure. In (a), the address 9 of the transmission data buffer is set to the address 2 of the data bus output control RAM, and the address 19 of the transmission data buffer is set to the address 4. Each transmission valid bit is 0. Then, the address 9 of the reception data buffer is set to the address 2 of the data bus input control RAM, and the address 19 of the reception data buffer is set to the address 4. Each reception valid bit is 0. And data bus input control R
The folding bit of the address 2 and the address 4 of the AM is 1. The all 1 setting bit is 0.

As a result, the data at address 9 and address 19 of the transmission data buffer are folded back at the folding section and stored at addresses 9 and 19 of the reception data buffer, respectively.

The address 9 of the transmission data buffer
The data (data A) transmitted to (slot 9) is returned and output from the line at address 9 (slot 9) of the reception data buffer 64. Similarly, the data transmitted to the address 19 (slot 19) of the transmission data buffer is folded back and output to the line at the address 19 (slot 19) of the reception data buffer 64.

FIG. 7 shows the data bus output control RAM of the present invention.
An embodiment (3) of the data bus input control RAM is shown. The figure shows a configuration in which station A performs a loopback test at station C, and loops back and outputs all 1 bits indicating that the test is in progress to station B.

(A) shows a data bus output control RAM data structure, and (b) shows a data bus input control RAM data structure. In (a), the data bus output control RAM sets the address 9 of the transmission data buffer at address 2 and the address 19 of the transmission data buffer at address 4. Each transmission valid bit is 0. Then, the address 9 of the reception data buffer is set to the address 2 of the data bus input control RAM, and the address 19 of the reception data buffer is set to the address 4. Each reception valid bit is 0. Then, the data bus input control RA
The folding bit of address 2 and address 4 of M is 1. Then, the all 1 setting bit of the address 2 of the data bus input control RAM 62 is set to 0, and the all 1 setting bit of the address 4 is set to 1.

As a result, the data at the address 9 in the transmission data buffer 65 is folded back by the folding unit 68 and stored at the address 9 in the reception data buffer. Further, the data at address 19 of the transmission data buffer 65 is not selected by the all-1 sending unit, but all-1 is selected and all-1 is set at the address 19 of the reception data buffer 64.

In this way, the data transmitted to the address 9 (slot 9) of the transmission data buffer is folded and output from the address 9 (slot 9) of the reception data buffer 64 to the line. For station B, all 1s are set in slot 19 (address 19) of the receive data buffer 64 and output to the line. for that reason,
Station B can recognize that Station A is under test.

[0048]

According to the present invention, it is possible to perform communication between branch stations without using the data bus of the master station in multiple access by a high-speed digital leased line and branch lines. Therefore, the usage efficiency of the data bus in the master station can be improved. In addition, bidirectional and unidirectional loopback tests can be easily set.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration (1) of the present invention.

FIG. 2 is a diagram showing a basic configuration (2) of the present invention.

FIG. 3 is a diagram showing a basic configuration (3) of the present invention.

FIG. 4 is a diagram showing an embodiment of a line interface unit of the present invention.

FIG. 5 is a diagram showing an embodiment (1) of a data bus output control RAM and a data bus input control RAM of the present invention.

FIG. 6 is a diagram showing an embodiment (2) of a data bus output control RAM and a data bus input control RAM of the present invention.

FIG. 7 is a diagram showing an embodiment (3) of the data bus output control RAM and the data bus input control RAM of the present invention.

FIG. 8 is a diagram showing a conventional time division multiplexing apparatus.

[Explanation of symbols]

 1: parent station (C station) 2: branch station (A station) 3: branch station (B station) 4: time division multiplexer C 5: time division multiplexer A 6: time division multiplexer B 7: line interface Part 8: Other interface 9: Data bus 10: Data bus input control unit 11: Return bit 12: Receive data buffer 13: Send data buffer 14: Data bus output control unit 15: Transmit / receive unit 16: Return control unit 17: Branch apparatus

Claims (4)

[Claims] 1. In a time division multiplexing device in a time division multiplexing communication network in which a parent station (1) and a plurality of branch stations (2), (3) are connected by lines, the parent station (1) is a branch station. A transmission data buffer (13) that receives the transmission data from (2) and (3) and stores it in association with a channel and address, and a reception data buffer (12 that stores the data that is output to the line in association with a channel and address). ), A data bus output control unit (14) for storing the address of the transmission data buffer (13), a data bus input control unit (10) for storing the address of the reception data buffer (12), and a transmission data buffer (13 ) Data from the inter-branch communication is returned to the data bus
A data bus output control unit including a loopback control unit (16) for transferring to the reception data buffer (12) without going through the (9)
Either (14) or the data bus input control unit (10) stores the return information, and the return information is written in the data bus output control unit (14) or the data bus input control unit (10). In this case, the loopback control section (16) loops back the data in the transmission data buffer (13) at the address in which the loopback information is written, and receives the data buffer (1) without passing through the data bus (9).
A time-division multiplexing device having a function of transferring to 2). 2. Station A (2) and station B (3) according to claim 1.
When performing inter-branch communication between stations, the data bus output control unit (1
4) specifies the address of the transmission data buffer (13) that stores the channel data of station A (2) and station B (3), and the data bus input control unit (10) controls the data bus output control unit (14). Received data buffer (12) for station B channel at specified address of transmit data buffer (13) for station A channel
A time division multiplexing apparatus characterized in that the address of the reception data buffer of the station A is specified at the address of the channel data of the station B is specified. 3. Station A (2) and station C (1) according to claim 1.
, And when performing bidirectional loopback communication between station B (3) and station C (1), specify the address of the transmit data buffer of the channel of station A of the data bus output control unit (14) to the specified address. The address of the receive data buffer (12) of the channel of station A of the data bus input controller (10) is stored, and the address of the transmit data buffer (13) of the channel of station B is stored at the specified address. 10) A time division multiplexing apparatus characterized by storing an address of a reception data buffer (12) of a channel of station B. 4. The data bus output control unit (14) or the data bus input control unit (12) according to claim 3, having all 1 setting information for writing all 1s to channel data. , When all-one sending part (16 ') for writing all-one to the specified address of the receive data buffer based on all-one setting information is provided to enable all-one sending at one-way return Division multiplexing equipment.