JPH06139682A - Method for making low power consumption of disk driving device - Google Patents

Abstract

PURPOSE:To prolong the life of a battery by suppressing power consumption in a disk device of a battery system under the nonselecting state of the disk device by the side of a host. CONSTITUTION:Under a standby mode of nonreceiving of a selecting command from the host side H, an idling mode or a sleeping mode, a CLK selecting signal S is outputted by a microcomputer circuit 11 to a gate array part 10. Then, the built-in programmble frequency divider is set for a frequency dividing ratio corresponding to each mode by the gate array part 10, and operating clocks for individual modules (mainly a C-MOS circuit configuration) 8, 9, 11 and 12 are changed over to that obtained by frequency-dividing a reference clock R respectively. Since power consumption of the C-MOS is proportional to the frequency of the operating clock, the power consumption can be reduced by using the frequency clocks. In addition, the frequency dividing ratios are set under the individual modes within ranges of spare time for executing tasks on the individual modules 8, 9, 11 and 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing power consumption in a disk drive device, which is applied to a drive device for an optical disk or a magnetic disk, and the operation of the drive device when the host side does not select the disk device. The present invention relates to a method for reducing power consumption by lowering a clock frequency within a range that does not affect a control operation.

[0002]

2. Description of the Related Art Conventionally, a hard disk device has been used as an external storage device of a computer, but it has been generally used due to its large capacity, high-speed access, and drastic improvements in downsizing, weight reduction and thinning. Personal computer
Not only (personal computer) but also palm-top type and notebook type personal computers are often installed. In particular, recently, the development of hard disk devices mounted on notebook PCs etc. has been remarkable, 2.5 inch type and 1.8 inch type devices are being put to practical use, and semiconductor disk devices (EEPROM) in the field of external storage devices. Among them, there are situations where they are cutting down on the memory capacity and price.

When the disk device is applied to a notebook type personal computer or the like, it naturally uses a battery drive system, so that it is necessary to prolong the life of the battery, and the reduction of power consumption thereof becomes a big problem.

For example, in the case of a practically used 2.5-inch hard disk drive, a disk drive spindle motor (SPM: DC brushless motor) is rotated at a normal rotation speed (3600 rpm). The power consumption is 0.8W, and the breakdown is that the current flowing to the SPM coil is 60mA, the current required for the control module including the microcomputer circuit is 100mA, and 5V is used as the power supply voltage. The total power consumption is the above value. In other words, the essential function of the hard disk drive is to rotate the disk and control its rotation, but the electric power for controlling the rotation is larger than the electric power for rotating the motor.

Further, the control module of the hard disk device not only rotates the SPM, but also transmits / receives R / W data and control signals to / from the host side, and
A rotary actuator equipped with a head for recording is controlled by a voice coil motor (VCM) to control tracking operations on the disk, but the mechanical part of the actuator also rotates by reducing the weight of the arm and magnetic head. The moment of inertia and load force are made extremely small, and the average access time can be set to 12 msec or less, and it is suppressed to 3.0 W or less even at the time of disk startup, which consumes the most power.

[0006]

By the way, according to the above-mentioned breakdown in the normal rotation state of the SPM, the total power consumption is 0.
Of the 8 W, 0.5 W is consumed by the control module, but most of the control module's circuit is in C-MOS configuration to reduce power consumption and is proportional to the number of switching times. Then, the power consumption becomes large. That is, in each control module that operates in synchronization with the operation clock, as the frequency of the clock increases, the total amount of current flowing during a unit time increases and power consumption increases. The situation is similar not only in the C-MOS circuit but also in the circuit that operates in synchronization with the clock.

On the other hand, when the host side has not selected the hard disk device and each control module is simply waiting for a command from the host side, task execution of each module in the control cycle for the SPM, magnetic head, etc. The time is shortened, and as a result, there is a time margin in each control cycle. In other words, in various modes in which the hard disk drive is not selected by the host, it is possible to reduce the operating clock frequency of each control module within the range that does not hinder the control of the SPM, magnetic head, etc. Electric power can be reduced.

Therefore, the present invention provides a method for reducing power consumption in a disk drive device based on the above-mentioned point of interest, and thereby prolongs the life of a battery of a notebook computer equipped with the disk device. Was created as.

[0009]

According to the present invention, there is provided rotation control means for controlling the rotation of a disk, and actuator control means for controlling the relative position of a read / write portion provided on an actuator with respect to the disk surface. Communication means for transmitting and receiving data and control signals to and from the host side, and data transfer means for performing reversible transfer of data while having a buffer function between the read / write unit and the communication means, A disk drive device comprising a mode control means for setting an operation mode of each of the means based on a control signal from the host side obtained from the communication means, and a clock generator for generating a reference clock for each of the means. In the above, in the non-selected state of the disk device, the clock is generated within the time margin for task execution that occurs in each of the above means. Frequency dividing means for dividing the reference clock is provided, and when the communication means confirms the non-selected state of the disk device by the host side, the dividing clock by the frequency dividing means is divided into all or one of the respective means. The present invention relates to a method for reducing power consumption in a disk drive device, which is used as an operation clock for a unit.

Further, it is assumed that the frequency division ratio of the frequency division means is not fixed and a plurality of frequency division ratios can be selectively set, and the frequency division is performed in correspondence with the setting of each operation mode by the mode control means. The frequency division ratio of the means may be selected.

Further, regarding the switching from the reference clock to the divided clock, there is provided timer means for starting the time measurement when the mode control means detects the non-selected state of the disk device by the host side, The switching may be executed when the timer means measures a certain time.

[0012]

According to the present invention, in the non-selected state of the disk device by the host side, the divided clock obtained by dividing the normal reference clock to lower the frequency is used in each means of the disk drive device.
(Rotation control means, actuator control means, communication means,
It is supplied as an operation clock for the data transfer means and mode control means). And most of the above means
It is often configured with a circuit such as C-MOS that consumes more power as the frequency of the operating clock increases, and it is in a non-selected state compared to the case where a constant reference clock is always used. Power consumption can be reduced.
However, even in the non-selected state in which the divided clock is used as the operation clock, each of the above means must be able to normally execute the task required in that state, and the division ratio of the frequency dividing means is in the non-selected state. It is set within the range of time margin for task execution that occurs in each of the above means.

There are various modes even in the non-selected state of the disk device, but the margin time for task execution varies depending on the mode. Therefore, if the frequency division ratio of the frequency dividing means can be selectively set and the frequency division ratio is set according to each mode, more efficient and effective power consumption reduction can be achieved.

[0014]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 1 shows a system circuit diagram of a hard disk device applied to a notebook computer. In the figure, 1 is a disc, 2 is a disc 1 is rotated 3
SPM, a brushless DC motor with a phase coil and 8-pole magnet, 3 is an actuator equipped with a R / W head 3a, 4
Is an SPM driver that performs commutation control of the drive current for each coil of SPM2, and 5 is the position control of the head 3a by controlling energization of the voice coil of the actuator 3.
VCM driver, 7 R / W amplifier for amplifying R / W signal of head 3a, 8 R / W for controlling R / W state while setting window time by incorporating pulse detector 8a and data separator 8b The controller 9 is a communication interface with the host side (not shown), and a hard disk that controls data transfer while caching read data and temporarily storing write data based on R / W commands from the host side. Controller (HDC), 10 is a gate array unit that incorporates an oscillator, timing generation circuit, programmable frequency divider, etc. to generate the operating clock of the system, 11
Is a microcomputer circuit, 12 is a servo control unit, 13 is a battery that is the power source for the entire notebook computer, and 14 is a power source circuit. Here, the microcomputer circuit 11 is
The SPM driver 4 and V calculates the R / W position by the head 3a based on the R / W data obtained from the data separator 8b and the HDC 9 and the burst signal described later obtained from the servo control unit 12.
Executes control of CM driver 5, and R / W as another task.
It manages the operation timing and data format. Further, the servo control unit 12 controls the VCM driver 5 based on the index signal and the gray code in the servo signal obtained from the pulse detector 8a to control the head.
Coarse positioning of 3a is executed, and A / B in the servo signal is
Obtain (A + B), (AB) from the burst signal.
Output to.

The R / W in the above system circuit
Most of the modules such as the controller 8, the HDC 9, the gate array unit 10, the microcomputer circuit 11, and the servo circuit 12 are configured as C-MOS circuits with low power consumption, and the power consumption of the entire system is suppressed to reduce the battery. The consumption of 13 is reduced.

By the way, in the hard disk drive of this embodiment, the gate array section 10 has a programmable frequency dividing function on the side of the disk drive, and the reference clock is divided in addition to the reference clock. Multiple divided clocks can be selectively output, and the microcomputer circuit 11 stores the operation clock management program, and the microcomputer circuit 11 sends the selection command of the disk device sent from the host side to the HDC 9. It is characterized in that the gate array unit 10 is controlled and the reference clock is switched to the divided clock by confirming the presence or absence thereof.

FIG. 2 shows how the internal circuits of the gate array section 10 and the microcomputer circuit 11 are connected to the buses and control lines. The gate array unit 10 includes a bus control circuit 21 including a latch circuit, a glue logic circuit 22, a timing pulse generation circuit 23, an erase gap detection circuit 24, a gray code detection circuit 25, an index detection circuit 26, and a sector. A counter 27, a crystal oscillator 28, and two programmable frequency dividers 29, 30 are provided. The oscillation frequency of the crystal oscillator 28 is divided by the frequency dividers 29, 30 to operate the internal circuit and various external modules. A clock is applied, and in particular, the present embodiment is characterized in that the frequency division ratios 29 and 30 of the frequency divider are not fixed and are programmable.
Since the data separator 8b of the R / W controller 8 needs to be always controlled at a high frequency, the output frequency of the crystal oscillator 28 is used as it is as the frequency of the operation clock.

On the other hand, the microcomputer circuit 11 includes a CPU 41, a timer 42, a ROM 43, a RAM 44, a bus control circuit 45 including a latch circuit, a D / A converter 46, a multiplexer 47, and an A / D converter. 48 and a pulse modulation circuit 49 built-in circuit configuration, CPU41 while taking in the counter electromotive voltage generated in each coil at the time of SPM2 rotation and the signal of servo control unit 12, and command data and R / W data. Controls the SPM driver 4 and the VCM driver 5 by executing the program stored in the ROM 43. In particular, in connection with the above features, ROM
The clock control program is stored in 43, and CPU4
1 confirms whether the host side selects the hard disk device by command data obtained from the system bus and controls the programmable frequency divider 29, 30 of the gate array section 10 in each mode in the non-selected state To switch the output clock.

Next, the operation of the hard disk device will be described with reference to the flow chart of FIG. 3 (rotation speed control procedure of SPM2),
The sector format and the time division related to the module control in each mode will be described with reference to FIG. First, in FIG. 1 and FIG. 2, the microcomputer circuit 11 sends a disk device selection command from the host side via a bus.
It monitors whether or not it is transmitting to the HDC9, and executes (A) SPM2 start mode / (B) actuator 3 seek mode / (C) head 3a R / W mode when the selection command is received. It will be (S1). Here, in this device, the average access time by the head 3a for the disk 1 is set to 12 msec or less, and the transfer rate of the R / W data is correspondingly increased, and the rotation speed of the disk 1 (SP
The rotation speed of M2) is set to 3600 rpm. Therefore, the time required for one revolution of the disk 1 is 16.67 msec, and assuming that the number of sectors of the disk 1 is 96, the time per sector is 173.6 μsec, and the servo signal time therein is 16 μse.
c. In this hard disk device, the gate array circuit 10 sets the reference clock to 30 MHz and supplies it as an operation clock to each module of the disk drive device.

The present embodiment is characterized in that the reference clock is divided and supplied to each module as described above.
In each of the modes (A), (B), and (C), the reference clock is used as it is for the reason described below. (A) Start-up mode [Refer to (A) of FIG. 4]: In this mode, the microcomputer circuit 11 connects the multiplexer 47 to the SPM driver 4 side, and changes the counter electromotive voltage generated in the three-phase coil of SPM2. It is taken in via the A / D converter 48, and by detecting the phase of the back electromotive force with the timer 42, it is detected whether or not SPM2 has reached the rated speed, and until the rated speed is reached Energization control is executed. Therefore, in order to shorten the time required for start-up and bring the disk 1 to the rated rotation speed quickly, it is necessary to execute control in synchronization with the fast operation clock, and it is necessary to use the reference clock as it is.

(B) Seek mode [see (B) of FIG. 4]: In this mode, the actuator 3 is operated via the VCM driver 5.
Is controlled to seek the head 3a to the disk 1 which has reached the rated rotation speed, the microcomputer circuit 11 takes in the sector signal obtained from the head 3a, and
The rotation position of SPM2 is detected by resetting with the index signal obtained for each rotation, and the detection signal
The energization control for the 3-phase coil of SPM2 is executed to maintain the rotation at the rated rotation speed. Specifically, the commutation control for the SPM driver 4 is performed by counting the detection cycle of each sector signal with the timer 42 of 0.1 μsec cycle and comparing the count number with 1736 corresponding to the specified cycle to obtain the error. The timing of is corrected and the rotational speed of SPM2 is adaptively controlled. Therefore, the task execution time required for controlling SPM2 is shorter than that in the startup mode. However, regarding seek control of the actuator 3, the microcomputer circuit 11 determines that the position and speed control signals are VCM based on the servo signals intermittently obtained with the multiplexer 47 switched to the input state from the servo control unit 12. It is necessary to output to the driver 5, and although there is some time margin, it is necessary to execute control with a fast operation clock, and it is necessary to use the reference clock as in the above.

(C) Read / write mode [see (C) of FIG. 4]: In this mode, the VCM driver 5 is controlled based on intermittent servo signals while controlling the SPM2 to the rated speed. In the state, the control task time related to SPM2 and VCM5 does not become so long. However, in this mode, R / W
The controller 8 sets the R / W mode, and the HDC 9 communicates and transfers the R / W data transferred from the head 3a and the host side while performing time management that makes full use of the buffer function. Considering that, there is almost no time margin. Therefore, similarly to the above, control must be performed by the fast operation clock, and the reference clock must be used as it is.

Therefore, the microcomputer circuit 11 sets, in the RAM 44, data in which the frequency division ratio is "1/1" as the clock control data, the correction gain value is "1", and the specified cycle is "1736". S
4), Output a CLK selection signal with a division ratio of 1/1 to each programmable divider 29, 30 of the gate array circuit 10, set the reference clock (30MHz) as it is as the operation clock, and use it as the microcomputer circuit. 11 and other modules 8, 9, 10, 12 are output (S5). Regarding the control of the SPM2 by the microcomputer circuit 11, as described above, the rotation cycle of the SPM2 is measured from the sector signal, the error is calculated by comparing it with the specified cycle set in the RAM44, and the gain for correction is added to the error. The energization timing correction data is created by multiplying by, and the correction data is output to the SPM driver 4 to control the SPM2 to rotate in a regular cycle (S6 to S10). The procedure is repeated in each of the modes (A), (B), and (C) that are switched sequentially, and the HDC
It is executed until the non-selection command is received from the host side at 9 (S11 → S6).

On the other hand, in the case where the non-selection command is transferred from the host side and the disk device is in the non-selection state,
There are (D) standby mode (the head 3a is on the disk 1 and is waiting for a selection command from the host side), (E) idling mode, and (F) sleep mode. However,
In the present embodiment, the mode determination in those non-selected states is not immediately performed at the stage when the non-selected command is received by the HDC 9, but the timer circuit 42 is activated when the microcomputer circuit 11 confirms the reception of the non-selected command by the HDC 9. It is activated and it is considered that the state has shifted to the non-selected state when a certain time (for example, 5 seconds to 30 seconds) has passed (S12). This is because selection and non-selection of the disk device are often repeated in a very short time, and executing the switching control of the operation clock, which will be described later, at each time makes the response speed of the disk device slow. Further, even if the operation clock is switched within such a time, it does not contribute much to the reduction in power consumption.

Hereinafter, the control procedure in each mode in the non-selected state of the disk device will be sequentially described. (D) Standby mode [Refer to (D1) and (D2) in Fig. 4]: In this mode, the actuator 3 keeps the head 3a on the disk 1 while maintaining the rated rotation state of SPM2. It is waiting for the selection command from the side, and as shown in (D1), the task execution time of the HDC9 is short, so there is a time margin. Therefore, the microcomputer circuit 11 confirms this mode (S12 → S13 → S15), and as the clock control data, the division ratio is "1/1" and "1/2", the correction gain value is "2", Set the specified cycle to "868" and set the data in RAM44.
(S15 to S17), the CLK selection signal (a) with a division ratio of 1/1 and the CLK selection signal (b) with a division ratio of 1/2 are each programmable dividers 29 of the gate array circuit 10. And output to 30. Then, the frequency divider 29 supplies the operation clock of the reference clock (30 MHz) as it is to the glue logic circuit 22, the erase gap detection circuit 24 and the gray code detection circuit 25 which are the internal circuits of the gate array circuit 10, and the frequency divider 30 is a 15 MHz operation clock obtained by dividing the reference clock (30 MHz) by half, the microcomputer circuit 11, the servo control unit 12, the HDC 9, and the R / W controller 8
Output to the pulse detector 8a (S5). In this case, to supply the clock of 30 MHz as it is from the frequency divider 29 to the glue logic circuit 22 or the like is that those circuits have a function of determining the absolute time such as R / W timing and the like in the standby mode. This is because even if there is, it is necessary to synchronize them with a fast clock.

By the way, the head 3a is on the disk 1 and reads the sector signal of the disk 1. In this case, the 1/2 divided clock is supplied to the microcomputer circuit 11 and the servo controller 1.
Since it is used as the operation clock for 2 and HDC9,
As shown in (D2) of FIG. 4, this is the time for one sector 173.
The control time of the SPM driver 4, VCM driver 5, and HDC 9 doubles within 6 μsec. Then, the rotation control of SPM2 is executed by the feedback procedure as in the case of selecting the disk device described above (S6 to S10, S11 → S6), but the frequency of the operation clock is 1/2.
Therefore, the specified cycle and the correction coefficient of the rotation speed are different. That is, the specified cycle: 868 is compared with the actual rotation cycle to obtain an error, and the error is multiplied by the correction gain value of 2 to create the energization timing correction data. In this case, the frequency of the operating clock is halved, which causes a delay in the rotation control of SPM2, causing a slight decrease in rotation accuracy.
(Wow and flutter increases by about 0.01%) In this standby mode, the R / W operation is not executed, so a slight decrease in rotational accuracy is not a problem.

Further, the control time in the servo control section 12 is doubled, and the actuator is also used in the microcomputer circuit 11.
Since the speed at which the control data of 3 is calculated decreases, a phase delay occurs in the following control signal of the actuator 3, but in practice it does not cause much problem, and if necessary, reduce the closed loop gain of that control. Can be dealt with by a method. Furthermore, the control time of the HDC 9 that is in the command reception standby state is doubled, and if the response is delayed, there is a possibility that a communication-disabled state with the host side may occur. This problem can be solved by interrupting the HDC 9 command waiting several times during the control time zone of the VCM driver 5.

By taking such measures, the normal operation of each module in this mode can be maintained even if the frequency of the operation clock is reduced to 1/2, and as a result, the power consumption is reduced to 1/2. Can be converted.
In the above control, the frequency divider 29 is fixed at a frequency division ratio of 1/1, but only the servo control time in each sector is set to 1/1 and switched to 1/2 in other time zones. Even so, VCM
It does not hinder the control of the driver 5 and HDC9, and by performing such switching, the gate array unit 10
Since the power consumption in the system can be reduced, the power consumption of the entire system can be further reduced.

(E) Idling mode [(E1) and (E
2)]: In this mode, actuator 3 is head 3
a is retracted to the shipping area and locked (Fig. 1
2), the microcomputer circuit 11 detects the rotational position of the SPM2 from the phase of the counter electromotive voltage generated in the three-phase coil and maintains the rated rotational speed, as in the above-mentioned start-up mode. While outputting the control signal to the SPM driver 4, HD
Waiting for a command to C9. And
Even in this mode, it is necessary to continue sampling the phase signal of the back electromotive force at a constant cycle, but it is sufficient if SPM2 rotates stably at almost the rated speed. 4 does not need to be controlled, and as shown in (E1), it is sufficient to execute control of the SPM driver 4 at a relatively long cycle while interrupting the command wait for the HDC 9 an appropriate number of times. That is, it is not necessary to perform control while detecting the accurate rotation speed of SPM2 with a fast operation clock,
In this mode, the control time of the SPM2 and the control time of the HDC9 due to an interrupt are inserted intermittently through the pause time of 4 times or more that in the start mode within the time of one sector. Is occurring.

Therefore, in this embodiment, the microcomputer circuit 11 confirms this mode (S12 → S13 → S14 → S1
8), The division ratio is "1/1" and "1 /" as clock control data.
4 ”, the gain value for correction is“ 4 ”, and the specified cycle is“ 1736 ”. Set the data in RAM44 (S18 to S20) and set the division ratio to 1/1.
CLK selection signal (a) and CLK selection signal (b) with a division ratio of 1/4
To the programmable frequency dividers 29 and 30 of the gate array circuit 10, respectively. Here, the division ratio is set to 1/1, even in this mode, as in the case of the standby mode, the glue logic circuit 22 or the like to which the clock of the frequency divider 29 is supplied is set to the reference clock ( This is because it needs to be operated at 30 MHz).

On the other hand, the set division ratio: 1/4 is the frequency divider 30.
The frequency divider 30 corresponds to the microcomputer circuit 11 and HD.
Since the operation clock is supplied to the C9 and the servo control unit 12, each control time of the SPM driver 4 and HDC9 is four times as long as when the reference clock is used. Then, the rotation control of SPM2 is executed by a feedback procedure (S6 to S10, S
11 → S6), the correction coefficient of the rotation speed is different because the frequency of the operation clock is 1/4. That is, in this case, the specified cycle: 1736 is compared with the actual rotation cycle to obtain an error, and the error is multiplied by the correction gain value of 4 to create the energization timing correction data. Here, the specified cycle is set to 1736 because the rotation cycle of SPM2 is
It is 16665.6 μsec (= 173.6 μsec × 96 sectors), and when SPM2 has the structure of an 8-pole magnetized rotor with a 3-phase coil, it is necessary to switch energization 24 times per revolution, so that switching The cycle is 694.4 μsec (= 16665.6 μsec / 24 times),
Since the 1/4 frequency-divided clock is supplied to the microcomputer circuit 11 as the operating clock, the timer 42 has 0.4 μsec (1 μse)
This is because counting is possible only in the cycle of c × 4), and as a result, 1736 (= 694.4 μsec / 0.4 μsec) corresponds to the specified period.

Further, the operation clock of the microcomputer circuit 11 is 1 /
Since it becomes the clock divided by 4, the control data (PWM pulse) output from the pulse modulation circuit 49 to the SPM driver 4 also has a width of 4 times as shown in (E2), and the delay causes the rotation of SPM2. The control accuracy will be slightly reduced,
Similar to the standby mode, it does not run R / W, so there is almost no problem.

Therefore, the frequency of the operation clock supplied to each module can be reduced to 1/4 of the reference clock, and the power consumption in the idling mode can be reduced to about 1/4.

(F) Sleep mode [Refer to (F1) and (F2) in FIG. 4]: In this mode, the actuator 3 fixes the head 3a to the shipping area and completely stops the SPM2,
Waiting for the select command to be sent from the host to the HDC9. Therefore, the control target of the microcomputer circuit 11 is only the HDC 9, and as shown in (F1), the command standby is only inserted several tens of times within the time of one sector, and a large time margin is produced. Further, since it is not necessary to control the SPM driver 4 and the VCM driver 5, it is not necessary to supply the operation clock to the glue logic circuit 22, the erase gap detection circuit 24, and the gray code detection circuit 25 in the gate array circuit 10.

Therefore, the microcomputer circuit 11 confirms this mode (S12 → S13 → S14 → S21) to stop the clock output from the frequency divider 29 (S21) and to divide the frequency by 1 /
"20" is set, and the operation clock supplied from the frequency divider 30 is switched to a cycle of 2 μsec (S22, S23). As a result, the frequency of the operating clock of the microcomputer circuit 11 and HDC9 is 1/20 (1.5 MHz).
z), and each control time of the HDC9 becomes longer as shown in (F2), but since it is command standby control, no problem occurs.

As a result, in this mode, the power consumption can be reduced to about 1/20 as compared with the case where the reference clock (30 MHz) is supplied to each module as it is. By stopping the operation of the timer 43, the A / D converter 48, the D / A converter 46, the pulse modulation circuit 49, etc., which does not require the operation inside, it is possible to suppress the power consumption below that. . Moreover, if the supply of the operation clock to the microcomputer circuit 11 is stopped and the system is started by outputting a reset signal from the host side when shifting to the start-up mode, the oscillator 28 and the bus control circuits 21, 45
Power consumption is also eliminated, and it becomes possible to make a state in which almost no power is consumed.

[0037]

The method for reducing power consumption in the disk drive device of the present invention has the above-mentioned configuration,
It has the following effects. According to a first aspect of the invention, in the non-selected state of the disk device, an operation clock obtained by dividing the reference clock for each module included in the disk drive device within a range that does not hinder each module from executing its task. Therefore, the power consumption in the non-selected state can be reduced by a ratio substantially corresponding to the division ratio.
This makes it possible to significantly extend the life of the battery of a notebook computer equipped with a hard disk device.
According to a second aspect of the present invention, the frequency division ratio is changed in correspondence with each mode such as the command standby mode, the idling mode, the sleep mode, etc. in the non-selected state of the disk device, and the more efficient reduction of power consumption is realized. . According to the third aspect of the present invention, when the disk device shifts to the non-selected state, the divided clock is supplied only when a certain time has elapsed, and the disk device is frequently selected / non-selected within a short time. In this case, the power consumption can be reduced without lowering the response speed of the disk device.

[Brief description of drawings]

FIG. 1 shows a system circuit diagram of a hard disk device (installed in a notebook computer) to which a method for reducing power consumption in a disk drive device of the present invention is applied.

FIG. 2 is a block circuit diagram showing a connection mode of a gate array section, a built-in circuit of a microcomputer circuit, a bus, and a control line.

FIG. 3 is a flowchart showing a rotational speed control procedure of a disk driving SPM.

[Fig. 4] Sector format and 1 in each mode
It is a figure which shows the time division regarding the module control per sector.

[Explanation of symbols]

1 ... disk, 2 ... SPM (spindle motor: 3-phase coil, 8
Pole magnetized magnet type brushless DC motor), 3 ... Actuator, 3a ... R / W head, 4 ... SPM driver, 5 ... VCM driver for actuator drive, 7 ... R / W amplifier, 8 ... R / W controller, 8a ... Pulse detector, 8b ... Data separator, 9 ... HDC (hard disk controller), 10 ... Gate array section, 11 ... Microcomputer circuit, 12 ... Servo control section, 13 ... Battery, 14 ... Power supply circuit, 21,45 ... Latch circuit Built-in bus control circuit, 22 ... glue logic circuit,
23 ... Timing pulse generation circuit, 24 ... Erase gap detection circuit, 25 ... Gray code detection circuit, 26 ... Index detection circuit, 27 ... Sector counter, 28 ... Oscillator, 29, 30
… Programmable frequency divider, 41… CPU, 42… Timer, 43… R
OM, 44 ... RAM, 46 ... D / A converter, 47 ... Multiplexer, 48
… A / D converter, 49… Pulse modulation circuit.

Claims (3)

[Claims] 1. A rotation control means for controlling rotation of a disk, an actuator control means for controlling a relative position of a read / write portion provided in an actuator with respect to the disk surface, and data and Communication means for transmitting and receiving control signals, data transfer means for performing reversible data transfer while having a buffer function between the read / write unit and the communication means, and the host obtained from the communication means In a disk drive device comprising a mode control means for setting the operation mode of each means based on a control signal from the side and a clock generation part for generating a reference clock for each means, the non-selected state of the disk device. In the above, the reference clock of the clock generator is frequency-divided within a time margin for task execution that occurs in each of the above means. A frequency dividing means is provided, and when the communication means confirms the non-selected state of the disk device by the host side, the frequency dividing clock by the frequency dividing means is used as an operation clock for all or a part of the respective means. A method for reducing power consumption in a disk drive device characterized. 2. The frequency dividing means is capable of selectively setting a plurality of frequency dividing ratios, and the frequency dividing ratio of the frequency dividing means is selected corresponding to the setting of each operation mode by the mode control means. A method for reducing power consumption in a disk drive device according to item 1. 3. A mode control means is provided with timer means for starting time measurement when the host side confirms the non-selected state of the disk device, and when the timer means measures a certain time, the frequency division means 3. The method for reducing power consumption in a disk drive device according to claim 1, wherein the divided clock is used as an operation clock.