JPH06139184A - Multi-bus master cache system - Google Patents

Abstract

PURPOSE:To assign a cache memory of the store-in system to a shared area of a main storage device by only adding a simple circuit in the system which uses a bus master which does not have a retry sequence. CONSTITUTION:A cache system informs a wait control part 6, a buffer control part 7, and a command control part 9 that a hit block does not have consistency with data in a main memory 5. The wait control part 6 makes a bus master 10 execute the wait cycle, and the buffer control part 7 intercepts a bus 4, and the command control part 9 prolongs command transmission from the bus master to the main memory 5 till transfer of the latest data in a cache memory 2 to the main memory 5, and the bus master 10 is permitted to access the main memory 5 after the block of the main memory 5 is latest, and therefore, the latest data can be accessed without degrading the throughput of the whole of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bus master cache system having a multi-bus master function and using a store-in type cache memory.

[0002]

2. Description of the Related Art Conventionally, a store-in type cache memory has been used on a local bus of a central processing unit in order to improve the processing speed of an information processing device having a multi-bus master function. In this case, it is necessary to sufficiently guarantee the data consistency between the cache of each bus master and the main memory.

As a method of guaranteeing data consistency between each cache and main memory, a method of limiting the address space to be cached to a private space of the central processing unit other than the global space, and a method of caching the address space to the global space There is also a method of snooping the allocated memory bus. In the former case, since the cached address is limited to the private space, the processing speed is limited. In the latter case, the global space can be cached so that high-speed processing is possible, but conventionally, bus snooping is performed using the retry sequence of the bus master.

[0004]

As described above, it is advantageous to adopt the snoop method in order to realize high-speed processing by using the cache memory of the store-in method in the information processing apparatus having the multi-bus master mechanism. The outline of the conventional bus snoop operation using the retry sequence of the bus master will be described below.

When the cache memory adopts the store-in method, the cache memory has a copy of a memory block in the global space on the main memory,
In addition, there may be a state where a part of the data of the block is updated only on the cache memory. That is, there is a state in which the central processing unit performs a write operation on a block in the cache memory and the data is not written in the main memory. At this time, the latest data corresponding to the write address exists only in the cache memory and is inconsistent with the data in the main memory. If another bus master accesses an inconsistent memory block on the main memory in this state, the cache cannot be accessed because the latest data cannot be accessed and the cache is accessed by the bus master. Monitors whether the cache has a copy of the block in which it resides and whether the copy data and main memory data are coherent. When it is determined that the bus master access is made to a block that is inconsistent with the copy of the cache memory, the cache interrupts the bus master access and performs a write-back operation to the main memory of the corresponding block. ,
The bus master cycle is re-executed while the latest block exists in the main memory to end the snoop operation.

In order to perform the above bus snoop operation,
In the conventional method, since the bus cycle retry sequence of the bus master that becomes snoopy is used, the bus master without the retry function cannot be connected to the global memory bus of the information processing device that supports the multi-bus master mechanism. In other words, the store-in type cache memory could not be adopted as it is for the local bus of the central processing unit of the system in which the bus master which cannot execute the retry sequence is connected on the memory bus.

As a method of solving this problem, conventionally, the memory space to be cached is limited to the private area of the central processing unit as described above, or the cache of the global address space is externally controlled so as to adopt a store-through method. Things were being done. However, these methods limit the processing speed of the store-in cache memory and are not a good idea.

For this reason, a cache dedicated to the store-through method, which does not require a complicated circuit but has a lower processing speed than the store-in method, is generally used in a personal-use small-scale information processing apparatus. Is used for.

[0009]

The present invention addresses these problems.
The central processing unit and the main memory
Store-in type cache via a local bus between
Cache memory connected, each bus master and central processing unit
And an address space that shares data with the memory bus
Multi-bus master having main memory connected in parallel
In a cache system, the bus master is the main
The contents of the main memory when the memory is accessed
If the contents of the cache memory do not match, the main memory
Until the contents of is transferred to the cache memory
Data from the memory bus and wait for the bus master.
To the main memory by inserting a cycle signal
Access to multiple buses is delayed
Provide the stem.

[0010]

The present invention thus provides that when the cache memory has a copy of a block of main memory, and there is no consistency between the data in that block and the data in main memory, another bus master will be assigned to that block. When accessed, the cache system snoops the access and notifies the wait controller, buffer controller, and command controller that the hit block is inconsistent with the data in main memory. The wait control unit causes the bus master to execute a wait cycle, the buffer control unit cuts off the bus, and the command control unit delays transmission of the command from the bus master to the main memory. During this time, the cache memory reflects the change of the memory block in the main memory. After that, the command control unit starts transmitting the command to the main memory, the buffer control unit connects the bus, and the wait control unit withdraws the wait cycle execution request, thereby permitting the bus master to access the main memory. . With the above operation, the bus master can access the latest data without reducing the throughput of the entire system.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a multi-bus master cache system showing an embodiment of the present invention, FIG. 2 is a flow chart showing an operation explanation of a multi-bus master cache system showing an embodiment of the present invention, and FIG. 3 is a timing chart for explaining a control operation of the multi-bus master cache system showing the embodiment.

In FIG. 1, the multi-bus master cache system of the present invention comprises a central processing unit 1, a local bus 3 connected to the central processing unit 1, and a cache memory 2 connected to the local bus 3. , A weight control unit 6, a buffer control unit 7, a bus master 10 for accessing the main memory 5, and a command control unit 9 for controlling a command from the bus master 10.
And a data buffer 8.

The cache memory 2 is the main memory 5
Cache memory 2 has a copy of a block of the block, and if another bus master 10 accesses the block while the data of the block is inconsistent with the data of the main memory, the cache memory 2 hits the block. Is inconsistent with the data in the main memory 5, the wait controller 6, the buffer controller 7, and the command controller 9
To notify. The wait control unit 6 causes the bus master 10 to execute a wait cycle, the buffer control unit 7 shuts off the bus, and the command control unit 9 delays the transmission of the command from the bus master 10 to the main memory 5. During this time, the cache memory 2 reflects the change of the memory block in the main memory 5. After that, the command control unit 9 starts transmitting a command to the main memory 5, the buffer control unit 7 connects the bus, and the wait control unit 6 withdraws the execution request of the wait cycle, whereby the main memory of the bus master 10 is withdrawn. Allow access to 5.
With the above operation, the bus master can access the latest data without reducing the throughput of the entire system.

In FIG. 3, MRDC # is the bus master 1
0 is a memory read command signal for accessing the main memory 5, IOCHRDY is a signal for the wait controller 6 to request the bus master 10 to add a wait cycle, and HITM # is an address output from the bus master 10 by the cache memory system 2. A signal indicating that a cache hit has occurred as a result of snooping, and the contents of the cache block have been updated, and is inconsistent with the data in the main memory, MRDCYC is a command for transmitting the MRDC # output from the bus master 10 to the main memory 5. The output signal of the control unit 9, MDOE # is a control signal for enabling / disabling the output of the data buffer 8 by the buffer control unit 7, and SNPADS # is the consistency between the cache memory 2 and the cache memory and the main memory 5. Snu on a block that doesn't exist Puhitto a result, the start signal of a bus cycle to write back the latest cache data in the main memory 5, RAS # and CAS # each main memory 5
Row address strobe and column address strobe signals for accessing the other DRAM, WEN # is DRA
M write enable signal, DATA is main memory 5
Is a data bus signal that is input / output to / from.

The operation will be described below with reference to FIGS. 2 and 3. In response to the bus master 10 outputting SA (31-0) and MRDC # to start access to the main memory 5, the command control unit 9 shuts off MRDC # and inputs the access command to the main memory 5. Prevent.
Next, the cache memory 2 snoops SA (31-0) (step 10) and, as a result, hits the memory block in which the data is updated on the cache memory (step 20), and thus activates HITM #. . The wait controller 6 receives the HITM # to instruct the bus master 10 to execute the wait cycle by deactivating IOCHRDY (step 30), and the buffer controller 7 receives the HITM # and shuts off the data buffer 8. As a result, the memory bus 4 is brought into a floating state (step 40). After that, cache memory 2
Indicates the start of a write-back cycle to the main memory 5 of the latest hit block by outputting SNPADS # (step 50). Main memory 5 receives SNPADS # and outputs an access signal to main memory DRAM to update the memory block. After all the latest data is written back, the command control unit 9
YC is output to the main memory 5 to restart the memory access of the bus master 10, and the wait controller 6 makes the IOC
Withdraw the inactive output of HRDY (Step 7
0), the buffer controller 7 brings the data buffer 8 into conduction (step 60) to restart the main memory access by the bus master 10 (step 80).
Main memory 5 receives MRDCYC and outputs an access signal to the DRAM. By the above operation, the bus master 10 can surely access the latest target data.

[0016]

As described above, according to the present invention, when the inconsistent memory block is hit between the cache memory and the main memory, the snoop result is input to the wait control unit, the buffer control unit and the data control unit. Since it takes a short time to start each operation, it is suitable for a system using a cache memory for the purpose of speeding up.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-bus master cache system showing an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation explanation of a multi-bus master cache system showing an embodiment of the present invention.

FIG. 3 is a timing chart for explaining a control operation of the multi-bus master cache system showing the embodiment of the present invention.

[Explanation of symbols]

 1 central processing unit 2 store-in type cache memory 3 local bus 4 memory bus 5 global main memory 6 wait control unit 7 buffer control unit 8 data buffer 9 command control unit 10 bus master 11 memory access command signal

Claims (1)

[Claims] 1. A store-in type cache memory is connected between a central processing unit and a main storage unit via a local bus, and an address space where each bus master and the central processing unit share data is connected via a memory bus. In a multi-bus master cache system having main memories connected to each other, if the contents of the main memory and the contents of the cache memory do not match when the bus master accesses the main memory, A multi-bus master cache system, characterized in that the access to the main memory is postponed by disconnecting the bus master from the memory bus until a content is transferred to the cache memory and inserting a wait cycle signal into the bus master.