JPH0613827A - Signal compession/expansion switching circuit - Google Patents

Abstract

PURPOSE:To compress and expand the signals in a small circuit scale by outputting the signal selected by a switch means as a rectified current in response to the signal level and converting the input signal into a current signal corresponding to the rectified current. CONSTITUTION:A differential amplifier circuit consisting of the NPN transistor TR QN1 and QN2 works as an expanding circuit when an action changeover switch 4 is switched toward a terminal EXP of the expanding action side. Under such conditions, the differential amplifier circuit outputs the input current signal as a voltage signal and the switch 4 selects an input signal or an output signal. Then, a rectifying circuit 2 rectifies the selected signal and outputs this signal as a rectified current in response to the signal level. Furthermore, a gain cell 1 converts the input signal VIN into a current signal I0 corresponding to the rectified current IRECT and inputs the signal I0 to an I/V converting amplifier 3. Thus, an expanding action is carried out and a compressing action is carried out when the switch 4 is switched to the COMP side. In such a constitution, the circuit scale can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal compression / expansion switching circuit, and in particular, is suitable for use in an integrated circuit for a radio telephone used in the communication field, that is, a compander integrated circuit for compressing and expanding a signal. A signal compression / expansion switching circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a decompression circuit of a conventional compression / expansion switching circuit. As shown in FIG. 4, the input signal V
IN1 is connected to the gain cell 1 through the input resistor RGIN1.
1 and is input to the rectifier circuit 21 through the input resistor RRIN1. A capacitor C1 is connected to the rectifying circuit 21, and the rectifying current IREC1 is applied to the gain cell 11. Output current I of gain cell 11
O1 is output to the inverting input terminal of the current-voltage conversion amplifier 31. The current-voltage conversion amplifier 31 has a feedback resistor RAMP1 connected between the inverting input terminal and the output terminal. The reference voltage VREF1 is applied to the non-inverting input terminal. The output voltage VOUT1 is output from the output terminal of the current-voltage conversion amplifier 31.
As a result, the expanded signal is output.

The operation of the above arrangement will be described below.

The input signal VIN1 is input to the rectifier circuit 21. When the conversion gain of the rectifier circuit 21 is k11, IREC1 = k11 · VIN1 (AVE) / RRIN1 (1) Further, the gain cell 11 outputs a current of IO1 = k12 · IRECT1 · (VIN1 / RGIN1) (2). Here, k12 is the gain cell 11
Is a coefficient of. Then, from the current-voltage conversion amplifier 31 to which this current is applied, a voltage VOUT1 = IO1.RAMP1 (3) is output. Formula (1), Formula (2), Formula (3)
Therefore, the input / output characteristics of the decompression circuit of FIG. 4 are: VOUT1 / VIN1 = k11.RAMP1.VIN1 (AVE) k12 / {RRIN1.RGIN1} (4)

As described above, the input signal VIN1 is expanded and output as the output voltage VOUT1.

FIG. 5 is a block diagram of a compression circuit of a conventional compression / expansion switching circuit. As shown in FIG. 5, the input signal V
IN2 is given to the inverting input terminal of the current-voltage conversion amplifier 32 through the input resistor RIN2. The output current I from the gain cell 12 is applied to the inverting input terminal of the current-voltage conversion amplifier 32.
O2 is added and the feedback resistor RAMP2 is connected. The reference voltage VREF2 is applied to its non-inverting input. A capacitor C2 is connected between the intermediate tap of the feedback resistor RAMP2 and the ground. To the output terminal of the current-voltage conversion amplifier 32, the gain cell 12 is connected via the input resistor RGIN2, and the rectifier circuit 22 is connected via the input resistor RRIN2. In the rectifier circuit 22,
The capacitor C1 is connected. The rectification circuit 22 provides the rectification current IRECT2 to the gain cell 12.

The operation of the above arrangement will be described below.

Now, assuming that the conversion gain of the rectifier circuit 22 is k21, the rectified current IREC2 of the rectifier circuit 22 becomes IECT2 = k21.VOUT2 (AVE) / RRIN2 (5). Further, the output current IO2 of the gain cell 12 is IO2 = k22.IRECT. (VIN2 / RGIN2) (6). On the other hand, the signal current IIN2 flowing through RIN2 is as follows: IIN2 = VIN2 / RIN2 = −IO2 (7) From the equations (5), (6) and (7), the input / output characteristics of the compression circuit of FIG. 5 are: VOUT2 / VIN2 = {RRIN2.RGIN2 / (K21.K22.RRIN.VIN2 (AVE)} ... 8), and a so-called compression operation of 1/2 power of VIN2 is performed.

[0009]

In the conventional compression / expansion switching circuit device, the expansion circuit shown in FIG. 4 and the compression circuit shown in FIG. 5 are separately configured as described above. RA of formula (4) and formula (8)
MP1, RAMP2 and input resistors RGIN1, RGI
If the same value is entered in N2, the equation (4) becomes the reciprocal of the square of the equation (8) and represents the decompression operation.
5 and FIG. 5 have many common functions.

The present invention has been made on the basis of the knowledge of the present inventor, and an object thereof is to share a main part of a compression circuit and a decompression circuit to enable compression / decompression of a signal with a small circuit scale. To obtain a signal compression / expansion switching circuit.

[0011]

A signal compression / expansion switching circuit according to the present invention selects current-voltage conversion / amplification means for outputting an input current signal as a voltage signal and one of the input signal and the output signal. Switch means, rectifier means for rectifying the signal selected by the switch means, and outputting as a rectified current according to the level of the signal, and the current signal by converting the input signal into a current signal corresponding to the rectified current And a gain changing means for inputting to the converting and amplifying means.

[0012]

The input current signal is converted into a current by the gain means, and is sent out as an output signal through the current-voltage conversion / amplification means. At this time, either the input signal or the output signal of the current-voltage conversion amplification means is selected by the switch means. The rectifying means gives the selected signal to the gain means as a rectified current corresponding to the level. In the gain means, the input signal is converted into a current signal corresponding to the rectified current and given to the current / voltage conversion / amplification means. Thereby, when the switch means selects the input signal, the expanded output is obtained as the output signal, and when the switch means selects the output signal, the compressed output is obtained as the output signal.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. As shown in FIG. 1, the input signal VIN is input to the gain cell 1 via the input resistor RGIN. The output current IO of the gain cell 1 is given to the inverting input terminal of the current-voltage conversion amplifier 3. The output voltage VOUT of the current-voltage conversion amplifier 3 is delivered as the final output. The output of the current-voltage conversion amplifier 3 is fed back to its inverting input terminal via the feedback resistor RAMP. In addition, the current-voltage conversion amplifier 3
The reference voltage VREF is applied to the non-inverting input terminal of the.
On the other hand, in the gain cell 1, the rectified current I from the rectifier circuit 2
RECT is given. The rectifier circuit 2 has a capacitor C
1 is connected. The rectifier circuit 2 has an input resistor RR.
The input current IRR is supplied via IN. The operation changeover switch 4 is connected to the input resistor RRIN. The input signal VIN is applied to the expansion operation side terminal EXP of the operation changeover switch 4, and the output voltage VOUT is applied to the compression operation side terminal COMP.

FIG. 2 shows a detailed configuration example of the rectifier circuit 2 of FIG. As shown in FIG. 2, the input signal VIN is given to the base of the NPN transistor QN1, and the output voltage VOU
T is input to the base of the NPN transistor QN3.
NPN transistor QN1 and NPN transistor QN3
Of the PNP transistors QP are commonly connected.
1 collector. PNP transistor QP1
Is connected to its base, and its emitter is connected to the power supply VCC through the resistor R1. The emitter of the NPN transistor QN1 is at the expansion operation side terminal EXP of the operation changeover switch 4, and the emitter of the NPN transistor QN3 is at the compression operation side terminal COMP of the operation changeover switch 4.
Connected respectively. Also, the NPN transistor QN1
Is also connected to the emitter of NPN transistor QN2, and the emitter of NPN transistor QN3 is NP
It is also connected to the emitter of N transistor QN4. NP
The collectors of the N transistor QN2 and the NPN transistor QN4 are commonly connected and connected to the collector of the PNP transistor QP2. The base of the PNP transistor QP2 is connected to the base of the PNP transistor QP1,
The emitter of the PNP transistor QP2 is connected to the power supply VCC through the resistor R2. PNP transistor QP
2. The collectors of NPN transistors QN2 and QN4 are
It is connected to the base of an NPN transistor QN5 whose collector is connected to the power supply VCC. NPN transistor Q
The emitter of N5 is an NPN transistor QN2, QN4.
Of the NPN transistor QN7 through the input resistor RRIN. The emitter of the NPN transistor QN7 is connected to the constant current source I2 and the emitter of the NPN transistor QN6. The reference voltage VREF is connected to the base of the NPN transistor QN6, and its collector has P
The collector and base of the NP transistor QP3 are connected. The emitter of the PNP transistor QP3 is connected to the power supply VCC through the resistor R3. PNP transistor Q
The base of P3 has an emitter connected to a power source VC through a resistor R4.
It is connected to the base of a PNP transistor QP4, which is connected to C. The collector of the PNP transistor QP4 is N
It is connected to the collector of the PN transistor QN7 and to the bases of the NPN transistors QN8 and QN9. The emitter of the NPN transistor QN8 is a constant current source I
3 and the base of the PNP transistor QP5. The base of the NPN transistor QN7 is the NPN transistor QN9 and the PNP transistor Q.
It is connected to the emitter of P5. NPN transistor QN
The collector of 9 is the collector of PNP transistor QP6,
It is connected to the base, the base of the PNP transistor QP7, and the collector of the NPN transistor QN11. The emitter of the PNP transistor QP6 is the power source V via the resistor R5.
Connected to CC. The collector of PNP transistor QP5 is connected to the collector and base of NPN transistor QN10 and the base of NPN transistor QN11. The emitter of the NPN transistor QN10 is a resistor R7.
Grounded through. The emitter of the NPN transistor QN11 is grounded via the resistor R8. The emitter of the PNP transistor QP7 is connected to the power supply VCC through the resistor R6, the collector thereof is connected to the capacitor C1 and the collector and base of the NPN transistor QN12 and the base of the NPN transistor QN13 through the resistor R9. The emitter of the NPN transistor QN12 is grounded. Also, the NPN transistor QN1
The emitter of 3 is grounded and the collector has a rectified current IRE
CT is sent out.

FIG. 3 is a circuit diagram showing an example of a detailed configuration of the gain cell 1 of FIG. As shown in FIG. 3, the input signal V
IN is an NPN transistor Q via an input resistor RGIN.
N22 base, NPN transistor QN23 base, collector and PNP transistor QP15 collector, NPN transistor QN25 collector and P
It is connected to the collector of the NP transistor QP12 and the bases of the NPN transistors QN26 and QN27. NPN
The emitter of the transistor QN22 is a constant current source I4 and NP.
It is connected to the emitter of N transistor QN21. NP
The reference voltage VREF is applied to the base of the N-transistor QN21.
Is connected to the collector of the PNP transistor QP1.
1 collector, base and PNP transistor QP1
2 connected to the base. PNP transistor QP11
The emitter of is connected to the power supply VCC through the resistor R11. The collector of NPN transistor QN22 is connected to the collector and base of PNP transistor QP13 and the base of PNP transistor QP14. The emitter of the PNP transistor QP13 is connected to the power supply VCC via the resistor R12. The emitter of the NPN transistor QN23 is grounded together with the emitter of the NPN transistor QN24 via the resistor R21. PNP transistor Q
The emitter of P12 is connected to the power supply VCC through the resistor R13. The emitter of the PNP transistor QP14 is connected to the power supply VCC via the resistor R14, and the collector thereof is the collector and base of the NPN transistor QN24 and the base of the NPN transistor QN25, and further N.
It is connected to the base of the PN transistor QN28. PN
The emitter of the P transistor QP15 is connected to the power supply VCC through the resistor R15, and its base is connected to the base and collector of the PNP transistor QP16 and the collector of the NPN transistor QN26. The emitter of the PNP transistor QP16 is connected to the power source VC via the resistor R16.
Connected to C. NPN transistors QN25, QN2
The emitters of 6 are commonly connected to an NPN transistor QN.
Connected to 30 collectors. NPN transistor QN
The emitter of 30 is grounded through a resistor R23, and its base is the base and collector of an NPN transistor QN29 and the collector of PNP transistor QP21 and PNP.
It is connected to the collector of the transistor QP23. NPN
The emitter of the transistor QN29 is grounded via the resistor R22. The emitters of the NPN transistors QN27 and QN28 are commonly connected and the NPN transistor QN32 is connected.
Connected to the collector. NPN transistor QN32
The emitter of is grounded via a resistor R25. The base of the NPN transistor QN32 is the NPN transistor QN.
31 base, collector and PNP transistor QP
22 is connected to the collector of the PNP transistor QP24. The emitter of the NPN transistor QN31 is grounded via the resistor R24. The collector of the NPN transistor QN27 is connected to the collector of the PNP transistor QP17 and also to the current-voltage conversion amplifier 3, and outputs the output current IO. The emitter of the PNP transistor QP17 is connected to the power supply VCC through the resistor R17, the base of which is the base and collector of the PNP transistor QP18 and the PNP transistor QP18.
Connected to the collector. NPN transistor QN18
Is connected to the power supply VCC via the resistor R18. The bases of the PNP transistors QP21 and QP22 are connected to the constant voltage source V. Also, the PNP transistor Q
The switching signal of the operation changeover switch 4 is input to the bases of P23 and QP24. This signal is the operation changeover switch 4
Is given at the H level when it is switched to the compression operation side terminal COMP, and at the L level when the operation changeover switch 4 is switched to the expansion operation side terminal EXP. The emitters of the PNP transistors QP21 and QP24 are commonly connected and connected to the collector of the PNP transistor QP20. The emitters of the PNP transistors QP22 and QP23 are commonly connected and connected to the constant current source I5. The emitter of the PNP transistor QP20 is connected to the power source VCC via the resistor R20, and the base thereof is supplied with the rectified current IREC from the rectifier circuit 2 together with the base and collector of the PNP transistor QP19. PNP transistor Q
The emitter of P19 is connected to the power supply VCC through the resistor R19.

The operation of the above-mentioned structure will be described below.

The operation changeover switch 4 is connected to the extension operation side terminal E.
At the same time as switching to the XP side, the input of the rectifier circuit 2 is the input signal VIN. This causes this circuit to operate as a decompression circuit. On the other hand, the operation changeover switch 4 is switched to the compression operation side terminal COMP side and the input of the rectifier circuit 2 is set to the output voltage VOUT. As a result, this circuit operates as a compression circuit. Therefore, by switching the input of the rectifier circuit 2 and the rectified current IREC to the gain cell 1 by the operation changeover switch 4, it becomes possible to switch between the operation as the expansion circuit and the operation as the compression circuit.

Now, a case where the circuit of FIG. 1 operates as a decompression circuit will be described. In this case, the operation changeover switch 4 is changed over to the extension operation side terminal EXP side, and NP
The differential amplifier circuit composed of N transistors QN1 and QN2 operates. The rectified current IRECT of the rectifier circuit 2 at this time is given by IREC (EXP) = k · VIN (AVE) / RRIN (9), where k is the conversion gain of the rectifier circuit 2. In the gain cell, the PNP transistors QP23 and QP24 are turned on, the current of the constant current source I5 flows through the PNP transistor QP30, and the rectified current IRECT flows through the NPN transistor QN32. Therefore, the output current IO (EXP) of the gain cell 1 is IO (EXP) = {IRECT (EXP) / I5}. (VIN / RGIN) (10). Then, from the current-voltage conversion amplifier 3 to which this current is applied, a voltage VOUT = IO (EXP) .RAMP (11) is output. Formula (9), Formula (10), Formula (1
From 1), the input / output characteristics of the expansion circuit are as follows: VOUT / VIN = {k.RAMP.VIN (AVE)} / (I5.RRIN.RGIN) (12).

As described above, the input signal VIN is expanded and output as the output voltage VOUT.

On the other hand, when the circuit of FIG. 1 operates as a compression circuit, the operation changeover switch 4 has the compression operation side terminal COMP.
To the NPN transistor QN3, QN4
The differential amplifier circuit composed of is operated. The rectification current IREC of the rectification circuit 2 at this time is given by IREC (COMP) = kVOUT (AVE) / RRIN (13), where k is the conversion gain of the rectification circuit 2. In the gain cell 12, the PNP transistors QP21 and QP22 are turned on, the rectified current IREC flows through the NPN transistor QN30, and the current of the constant current source I5 flows through the NPN transistor QN32.
Therefore, the output current IO (COMP) of the gain cell 1
Becomes IO (COMP) = {I5 / IRECT (COMP)}. (VIN / RGIN) (14). On the other hand, the output voltage VOU of the current-voltage conversion amplifier 3
T becomes VOUT = IO (COMP) .RAMP (15). From the equations (13), (14) and (15), the input / output characteristics of the compression circuit are: VOUT / VIN = [(I5 · RRIN · RAMP) / {k · RGIN · VIN (AVE)}] ^{1 / 2} (16) and the compression operation of 1/2 power of the VIN level is performed.

Feedback resistor RAMP = input resistor RGI
When N, the equation (12) becomes the reciprocal of the square of the equation (16), and the decompression operation is performed.

As described above, the circuit of FIG. 1 can be operated as both a compression circuit and a decompression circuit simply by switching the operation changeover switch 4 between the expansion operation side terminal EXP and the compression operation side terminal COMP.

According to the above embodiment, it is possible to obtain a circuit for performing both compression and decompression with a small number of elements, which is obtained by adding an input switching circuit to the conventional decompression circuit.

[0025]

As described above, according to the present invention, one circuit is compressed by switching the signal input to the rectifier circuit between the input signal to the gain cell and the output signal of the current-voltage conversion amplifier. Also, it can be operated as a decompression circuit, and thus both compression and decompression operations can be realized by almost a common circuit, and the number of elements and pins can be reduced and cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of the rectifier circuit of FIG.

FIG. 3 is a circuit diagram of the gain cell of FIG.

FIG. 4 is a block diagram of a decompression circuit of a conventional compression / expansion switching circuit.

FIG. 5 is a block diagram of a compression circuit of a conventional compression / expansion switching circuit.

[Explanation of symbols]

 1 Gain cell 2 Rectifier circuit 3 Current-voltage conversion amplifier 4 Operation changeover switch 11 Gain cell 21 Rectifier circuit 31 Current-voltage conversion amplifier 12 Gain cell 22 Rectifier circuit 32 Current-voltage conversion amplifier

Claims (1)

[Claims] 1. A current-voltage conversion / amplification means for outputting an input current signal as a voltage signal, a switch means for selecting one of the input signal and the output signal, and a rectification of the signal selected by the switch means, Rectifying means for outputting a rectified current according to the level of the signal, and gain varying means for converting the input signal into a current signal corresponding to the rectified current and inputting the current signal into the current-voltage conversion / amplifying means. Characteristic compression / expansion switching circuit device.