JPH06138188A - Register suited for self test - Google Patents

Abstract

PURPOSE:To facilitate the test of a sequential circuit by changing the register structure in a circuit when testing a digital system including the sequential circuit. CONSTITUTION:A system configuration diagram with a pseudo random test pattern as the input to a sequential circuit 100 for testing it is shown. The circuit 100 includes a logic network 110, a memory element 190 of a non- corrected register, and at least one corrected trap cell 120. Input data are applied to a main input block 180 and the response of the circuit corresponding to it can be observed in the main output block 160. By introducing the register structure in this configuration, the function of the register is monitored and the output bias can be changed periodically so that it becomes random, namely logic's 1 and 0 occur at a generation ratio of approximately 0.5. The internal state can be changed when testing the sequential circuit and the test can be performed fully according to applied patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method using a random or weighted random pattern sequence for a sequential circuit of a complicated digital system.

[0002]

BACKGROUND OF THE INVENTION Digital circuits respond to the application of their input lines and output the result on their output lines. A combination of input signals to a circuit is called an "input vector" or "input pattern" for this circuit, and similarly, a combination of corresponding output values is called an "output vector" or "output pattern". A combinatorial circuit is a circuit that does not include a memory element, so its output depends only on the input pattern input to that circuit. On the other hand, since the sequential circuit contains memory elements therein, its output is affected by the sequence of states within the sequential circuit. This means that an input vector with a special sequence is needed to put the sequential circuit in a special state.

A typical method for testing faults in sequential circuits is to apply an input test pattern with a special sequence. The method of sequential circuit test that is often performed at present is to test the circuit under test (this is CUT:
circuit under test) is a method of storing a test pattern that is facilitated in advance outside and providing a test unit having a function of applying this to a circuit under test. This is referred to below as a stored pattern or stored test.

By using the pseudo random pattern generation method, it is possible to reduce the functional or storage capacity requirement of the external test unit. Linear feedback shift register (LFSR)
eedback shift register) and cellular automata (CA:
It is well known how to realize test pattern generation in hardware using a relatively simple sequential machine such as cellular automata). In this case, the generated pattern generates logic 1 and logic 0 with almost the same probability. Such patterns are called random test patterns (actually pseudo test patterns).

The point to be improved in random pattern generation is to improve the pattern generator so that the generation ratio of logic 1 is higher than the generation probability of logic 0. In some cases, the probability of occurrence of logic 0 is increased. This is called "weighting" generation. A series of signal values on a certain signal line is called a bit series. The "weighting" or "bias" of a bit sequence is the ratio of one logic state in the sequence to another logic state (i.e., a logic 1 to a logic 0). "Weight distribution" is an ordered set of biases for the output lines of a pattern generator having a weighting function. Weighted random number pattern generation has been shown to be effective in testing combinatorial circuits.
It is possible to mix the storage pattern and the pseudo pattern test method described above. For example, the stored pattern may be used to complement a pseudo-test pattern sequence and the stored pattern may be used as part of the pseudo-random test pattern generation.

[0006]

In order to fully test a sequential circuit, it is necessary to generate all possible states or operations of the sequential circuit in the sequential circuit, but unlike the retractable pattern method, The pseudo-random test pattern method cannot produce sufficient circuit operation to effectively test sequential circuits. This is due to the lack of the ability to fully control the operation of memory elements and observe them.

As a solution to this, LSSD (Le
There is a method of changing the circuit structure using a test facilitation method DFT (Design For Testability) such as vel Sensitive Scan Design).

Another test facilitation method DFT is to reduce the complexity of the implementation as a part of a built-in self-test (BIST) system sufficiently and place it on the CUT. There is a pattern generator that can do this.

A test mechanism incorporated on such a circuit can reduce the complexity of the physical inspection when testing and the cost required when using an external test unit.

However, on the other hand, such a BIST
The disadvantage of the system that adopts the method is that it may increase the area or decrease the speed by creating a test structure in the circuit. In particular, when BIST is considered as a test for a sequential circuit, it is pointed out that the area inside the circuit required by the conventional retractable test pattern becomes relatively large.

It is an object of the present invention to propose a BIST test method for a sequential circuit which can solve the above problems.

[0012]

SUMMARY OF THE INVENTION The present invention introduces a pseudo-random test pattern that can be applied only to the main inputs of a sequential circuit to produce a level of circuit operation sufficient to test the sequential circuit. We propose possible registers.

The register according to the invention consists of a flip-flop that can be set or reset, a mode selection logic, a combinatorial logic network which functions as a 1 or 0 detector (but not both). 1 or 0 detectors are either register output or register input,
Investigate whether or not a bit value is generated, which is convenient so that the circuit operation can be sufficiently performed. By mode selection, the register input to the flip-flop and the output of the detector are intermittently coupled into the flip-flop data input.

The purpose of this is to monitor the operating function of the register and check the frequency of appearance of logic 1 and logic 0 in the output value (
In the present invention, the term "bias" is periodically changed to be random, that is, close to 0.5.

[0015]

According to the present invention, when testing a sequential circuit, it is possible to easily change the internal state, and therefore, it is possible to create a pseudo-random circuit state, and it is possible to obtain a sufficient test pattern depending on the applied test pattern. You will be able to test.

[0016]

In the following, the basic concept of the present invention will be described first, and then detailed examples will be described with reference to the drawings.

In the present invention, it is defined that the internal state of the circuit is determined by the value of the memory element contained therein.

It is difficult to guarantee the randomness in the output line of the register element only by applying the test pattern by the pseudo-random method, because it is difficult to access the memory element and the memory element does not operate sufficiently. Is.

The present invention introduces a new register structure and register control system, and periodically changes the bias of the register output so as to be close to 0.5, so that the natural sequence operation of the CUT can be used. To
In comparison with a CUT that does not have such a change, when a pseudo random number test pattern is applied to the changed CUT,
It is possible to make the circuit state or the circuit operation in a wider range.

Further, in the present invention, an outline of a hardware generation system using the new register structure and applicable to both the chip built-in type (that is, the method realized on the chip) or the stored type test by the pseudo random system is also given. Describe.

The first point of the present invention is a register modification that creates a new register structure. This new register structure is called a Trap Cell. In the present invention, the trap cell is used to observe the circuit operation caused by the application of the pseudo-random pattern, and increase the ratio of the time when the state of the register becomes the desired state.

The trap cell consists of: (1) a flip-flop with set and reset input terminals (2) mode selection logic (3) the desired state in either the register output sequence or the data input sequence in the normal circuit. A circuit that detects whether it has occurred. This logic circuit is called trap logic. An event is when a desired state occurs.

The trap logic in a particular trap cell performs one of the following functions on the input sequence.

(A) The occurrence of the above event is detected and a logic 1 is returned, or (b) The occurrence of the above event is detected and a logic 0 is returned.

The mode select logic is responsive to the first logic state of the mode select signal to cause the flip-flop to receive the data input of a conventional logic circuit as if its register had not been modified. The second logic state of the mode select signal causes the flip-flop to receive as its input the result of the register output and the input by the normal circuit processed by the trap logic. In this way, when the mode selection signal is in the second logic state and the output of the register or the normal data input has the desired bit state, the desired bit state is forcibly detected and held. Of. Upon detecting the desired bit state, the register accepts and forces this logic value while the mode select signal is in the second logic state. Hereinafter, a desired bit state of data is referred to as FBS (favored bit state).

The register in the trap cell described above facilitates periodic modification of the normal bias of the register by increasing the percentage of time that a particular bit state occurs at the register output. The bias of a register here is the bias of the output of the register when the register is not replaced by a trap cell, or the bias of the data input to the register.

Another point of the present invention resides in a designing method which makes it possible to place all or part of the hardware test pattern generator on the CUT. The hardware test pattern generator has the following three elements.

(1) A general pseudo-random type pattern generator used to supply a test pattern to the CUT input (2) A control logic block and a signal distribution network corresponding to the new register structure. This provides a mode select signal to the trap cells described above.

(3) An internal state generator consisting of all unmodified registers and the registers modified as described above (ie an internal state generator consisting of all registers in the circuit containing at least one trap cell). vessel).
The output of this generator is distributed across the CUT.

The pseudo random pattern generator may be placed outside the circuit as part of the external test unit, or B
It may be placed in the circuit as part of the IST system.
Similarly, the global control logic described above may be outside or inside the circuit.

Of the registers in the circuit, the bias is 0.
Registers that differ significantly from five are replaced by trap cells. The mode selection signal equalizes the degree of occurrence of the bit state so that the bit state is convenient for the trap cell. The mode selection signal is applied to a weighted sequence, a random sequence or a sequence with a fixed structure and duration. Such a sequence is a cycle in which the mode selection signal of the first logic state has at least one cycle, and then the mode selection of the second logic state continues for n cycles.

In order to enable the internal circuit to assume various states, the mode selection signal is generated as follows. The bias of the output line of the trap cell is such that the bias is within a threshold of 0.5 when the mode selection is measured at the end of each time interval of the first logic state. This allows the non-random internal state to be in a state with a bias close to 0.5.

The contents of the invention will be described below with reference to examples.

FIG. 1 shows a system configuration diagram of a type in which a pseudo random test pattern for testing a sequential circuit (circuit 100) is applied to the input of the circuit. The circuit 100 includes a signal distribution combinatorial logic network 110, an unmodified register type memory element 190, and at least one modified register 120, which is referred to as a trap cell. Input data is applied to the main input block 180,
The corresponding circuit response is observable in the main output block 160.

FIG. 2 is a block diagram of the trap cell 120. Each modified register 120 comprises a flip-flop 150, a 2-input 1-output selector 140, and a trap logic block TLB (Trap Logic Block) 130. TLB is a signal state (1 or 0) when an event occurs in an arbitrary input bit sequence 132, 133.
To detect.

The flip-flop 150 has an input 153 for set control and an input 154 for reset control. The first logic state of the set input 153 is the flip-flop 150.
Of the output 153 of FIG. The first logic state of reset input 154 causes output 151 of flip-flop 150 to be a logic zero value. Neither the second logic state of set or reset determines the output 151 of the flip-flop to a specific value, nor does it affect the operation of the flip-flop 150. When the first logic state of set and reset is given at the same time, the output of the flip-flop 150 is determined depending on the logic state specific to the flip-flop used to realize this flip-flop.
CO is the data output 151 of the flip-flop 150 and is equal to the data output of the trap cell.

The output 141 of the selector 140 is connected to the data input 152 of the flip-flop 150. TR
The AP_CTL line (this is the mode select signal) is connected to the select input 144 of the selector 140. Data inputs 142 and 143 are the output 131 of the trap logic block 130 and the data input CI to the circuit, respectively.
It is connected to the. The CI data line is coupled to the data input 152 of the flip-flop 150 when TRAP_CTL is in the first logic state. The output 131 of the trap logic 130 is coupled to the data input 152 of the flip-flop 150 when TRAP_CTL is in the second logic state.

Input 13 to Trap Logic Block 130
2 is connected to the non-zero output 151 of the flip-flop.
The input 133 to the trap logic block 130 is connected to the circuit's original data input CI. The function of the trap logic block 130 is to detect when the desired logic state (1 or 0) occurs on the input 132 or 133 and output the value of the current logic state on the output 131. The output 131 of the trap logic is connected to the input 142 of the selector 140 and serves as a data input to the flip-flop 150 instead of CI.

The trap logic block 130 present in a particular trap cell 120 performs the following functions on the bit sequence of the input to it: (a) Detects when a logic 1 occurs on the input line 132 or 133. , And returns that value to line 131.

(B) When a logical 0 occurs on the input line 132 or 133, it is detected and the value is returned to the line 131.

The trap cell 120 can be converted into an equivalent combinational circuit without using the trap logic 130 and the selector 140.

The logic circuit block 300 of FIG. 3 shows an implementation example of the trap cell 120. Trap cell 3
00 is an example of a case where the trap logic block returns a logic 1 when detecting an event occurring on the line 132 or 133. Logic circuit block 400 of FIG.
Shows another implementation example of the trap cell 120. Trap cell 400 is an example of a case where the trap logic block returns a logic 0 when it detects an event occurring on line 132 or 133.

In FIG. 3, a combinational logic network 340 representing a trap logic and a mode selection logic function is composed of an AND-OR, the output of which is the output 323 of the OR gate 320 and the data of the built-in flip-flop 330. It is connected to the input 332. The OR gate 320 acts as a detector for detecting a logical one in the bit sequence to the input pins 321 and 322. AND gate 3 when TRAP_CTL is logic 1
10 is the register output 331 and the input 3 of the OR gate 320
To 21. In this way, the OR gate 320
It provides the function of detecting a logical 1 event at the input that combines line 331 with the data input CI originally defined in the circuit. The result is connected to the input 332 of flip-flop 330. When TRAP_CTL is a logic zero, feedback from output 331 of flip-flop 330 is suppressed and CI is coupled to data input 332 of flip-flop 330.

The combinatorial logic network 440 of FIG.
Performs logic 0 detection and mode selection function. AND gate 420 acts as a detector that detects a logical zero for the bit sequence at inputs 421 and 422. The result of this function (ie the output 423 of AND 420) is the data input 432 of the internal flip-flop 430.
Connected to. When TRAP_CTL is logic 1, the positive output 431 of flip-flop 430 is inverted and NAND
It is fed back via the first input 411 of gate 410 and coupled to the input 421 of AND gate 420. AND gate 420 thus detects a logical 0 event on the register output and CI. TRAP
When _CTL is logic 0, CI is flip-flop 4
30 inputs 432.

If the desired bit state FBS (logic 1 in FIG. 3, logic 0 in FIG. 3) is detected for the trap cells of FIGS. 3 and 4, the trap cell accepts this value and TRAP--CTL has a logic 1 This value is held for as long as (i.e., during the second logic state).

Now all registers are modified to logic 1
It should be noted that it does not detect and retain a logical zero. In FIG. 2, the unmodified register (190 of FIG. 1) does not introduce the functionality of the selector at the input of the trap logic block and flip-flop. In this case, CI is directly connected to the input of the flip-flop.

As shown in FIG. 1, in circuit 100, the response of the circuit applied to main input 180 is observable at main output block 160. The pseudo-random test pattern data is a pseudo-random generator (P
RTG) 200 and applied to the main input via data bus 201. In the original BIST scheme, the pseudo-random generator PRTG200 is implemented as part of the circuit 100. As an alternative, PRTG is circuit 1
00 may be in a test mechanism external to the device.

In testing a sequential circuit, the circuit 100
Is observed at the main output block 160 and
It is transferred to the output analyzer OA (Output Analyser) block 170 via 171 and compared with a reference value. OA17
0 may be implemented as part of circuit 100, or some or all of it may be external to circuit 100.

Unmodified register 190 and trap cell 1
20 are connected via the corresponding CI and CO terminals. The TRAP_CTL line of each trap cell 120 is connected to the TRAP_CTL bus 221. The group of trap cells is a common T branching from the bus 221.
The RAP_CTL signal may be shared. Global trap control block TCB 220 generates the TRAP_CTL signal, and like PRTG 200 and OA 170, TCB 220 may be internal to circuit 100, or part or all external to circuit 100.

In the circuit 100, in the normal operation,
The TRAP_CTL bus 221 is brought to the first logic state and the register 120 coupled to it performs the same function as the original unmodified register. That is, C
I is coupled to the data input of the flip-flop in the corresponding trap cell 120. In this configuration, the combinational logic 110 and the memory functions required for normal operation of the overall circuit 100 are provided.

When testing circuit 100 in pseudo-random fashion, a test pattern is generated in PRTG 200 and applied only to main input block 180. Either set or reset the registers to force the registers in the circuit to either a logical 1 or a logical 0 first.
Create a test pattern that begins with a short test pattern that causes the bits corresponding to (but not both) to be in the first logic state. If register set or reset is not triggered successfully by the circuit's inherent function, the initial sequence is followed by an unmodified register set or reset input and a trap cell input of 1.
The test pattern is generated such that it is activated in a sequence with a bias close to 00% and the set / reset is in a convenient second logic state. If such a biased sequence applies only to one of the controls (set or reset) of these flip-flops, the other controls lock in the second logic state.

To apply the test pattern, the CO of the register is brought to a logic 1 or logic 0 state, switching between this value. When the time comes, the value of the output CO of each register will reflect the ratio of the time of logic 1 and the time of CO being logic 0. Such a ratio is called the bias of each register.

Further, in testing circuit 100, all signals on TRAP_CTL bus 221 operate while the corresponding signal is in the first logic state or the corresponding signal is in the second logic state. . When the function of the trap cell performs essentially the same function as the unmodified register, or the trap logic in the trap cell
The TRAP_CTL bus 221 adds trap cells to a particular signal on the TRAP_CTL bus 221 while detecting and holding a convenient bit value in the CI sequence of an individual trap cell or the CO sequence of a trap cell.

Application of the pseudo random test data described above to the main input block 180, and the TCB 15 described above.
0 and the processing of the TRAP_CTL bus 221 and the circuit 1 according to a predetermined test pattern sequence.
It is also possible to complement the pseudo-random test with a test mode of 00.

The signal on the TRAP_CTL bus can be generated corresponding to a weighting sequence or a sequence having a fixed pattern structure. For example, a repeating sequence in which the second logic state of a particular TRAP_CTL continues for n cycles, followed by TRAP_CTL having at least one cycle of the first logic state.

To predict how many clocks (n clocks) will elapse while the input of an individual trap cell is in the second logic state, the bias p of the normal data input CI of that register is required. . Once this value p is known (ie, either directly observable, or by analogy with information about each register associated with another observed signal line), the value for n is determined as follows: To be The CO bias of the register measured at the end of the section in which the TRAP_CTL of the register was operating in the second logic state and before the register output corresponds to the first logic state of the TRAP_CTL of the register is 0 in the range specified by the user. Decide to fit within 5. That is, [0.5−x] / p <n <[0.5 + y] / p where x and y are values that determine the range. x and y usually take small values (for example, 0.2). by this,
The overall bias of the CO bit value measured at the above timing is sufficiently close to the random pattern bias (0.5). The bias of the vector measured in the above measurement interval is called "forced bias".

Given a sequential circuit, the memory elements therein are unmodified registers. FIG. 5 shows an outline of an uncorrected register detection and correction method by the repeated simulation method. The register to be detected and modified here is replaced by a trap cell so that the given circuit conforms to the form shown in FIG. 1 and allows testing with a pseudo-random type sequence.

Fault-free simulation is performed by using some patterns selected from the pseudo-random test patterns, and the input bias pi of the register in the circuit is obtained.
If the input bias value of the unmodified register is outside the user-specified range of 0.5, the trap control signal is calculated as described above (ie, the register is forced to the threshold range). TR to
The approximate length of time to keep AP_CTL in the second logic state is calculated). The node is then replaced with the trap cell. If not, that is, if the bias corresponds to a trap cell, the existing forced bias is calculated and referenced by using the already existing TRAP_CTL before considering register remodification. Compare with the range of values. This series of processing is continued until all the nodes are within the acceptable range.

The special correction procedure shown in FIG. 5 is not necessary for register loop detection. Rather than explicitly manipulating register independence from each other by resimulation after each memory element has been modified, by considering each register independently in each iteration of the procedure Omit the trouble. That is,
In a single iteration of the modification procedure, treat all registers as the complement of the modification or remodification.

Although the circuit 100 is a single circuit under test in FIG. 1, for testing purposes, the circuit 100 is
0 may be divided into several partial circuits, or may itself be considered as the result of dividing a larger circuit.

[0061]

As described above, it is difficult to access the memory element and the randomness of the output line of the register element is guaranteed only by applying the test pattern by the pseudo-random method. Is difficult.

In the present invention, a new register structure and register control system are introduced, and by periodically changing the register output bias so as to be close to 0.5, it is possible to use the natural sequence operation of the CUT. To
Compared with a CUT that does not have such a change, when a pseudo random test pattern is applied to the changed CUT, it is possible to make the circuit state or the circuit operation in a wider range.

[Brief description of drawings]

FIG. 1 is a block diagram of an entire hardware generation system for internal bias conversion.

2 is a block diagram of the generated circuit register used in FIG. 1. FIG.

FIG. 3 is a block diagram of a trap cell holding a logic 1 event.

FIG. 4 is a block diagram of a trap cell holding a logic 0 event.

FIG. 5 is a diagram showing a method of inserting a trap cell and a method of determining trap control.

[Explanation of symbols]

100 ... Sequential circuit to be tested, 110 ... Signal distribution combination logic network, 120 ... Correction register (trap cell), 130 ... Trap logic, 140 ... Selector, 15
0 ... Flip-flop, 160 ... Main output block, 17
0 ... Output analyzer, 180 ... Main input block, 190 ... Unmodified register memory element, 200 ... Pattern generator, 2
20 ... Trap control block, 300 ... Trap logic implementation example, 400 ... Trap logic implementation example

Claims (11)

[Claims] 1. A settable or resettable flip-flop and a logic 1 at a data input, which is detected to output that a logic 1 event has occurred, or a logic 0 at the data input, which is output. A trap logic comprising a combinational circuit for detecting and outputting either of the occurrences of a logic 0 event and the output of the trap logic as the data input is coupled to the data input of the flip-flop. A register having mode selection logic for switching between coupling to the data input of the flip-flop. 2. The data input to the trap logic is
The register according to claim 1, comprising a data input from the outside of the register and an output of the flip-flop. 3. The register according to claim 2, wherein the trap logic detects whether either the data input from the outside or the flip-flop is in a logic 1 state. 4. The register according to claim 2, wherein the trap logic detects whether either the data input from the outside or the output of the flip-flop is in a logic 0 state. 5. The combination of the trap logic and the mode selection logic is an AND gate which receives an output of the flip-flop and a mode selection signal, a data input to the register from the outside, and the AN described above.
4. The register according to claim 3, comprising an OR gate having the output of the D gate as an input, and the output of the OR gate being connected to the data input of the flip-flop. 6. The combination of the trap logic and the mode selection logic is a NAND gate which receives a signal obtained by inverting the output of a flip-flop and a mode selection signal, a data input from the outside to the register and the NAND described above.
The register according to claim 4, comprising an AND gate having an output of the gate as an input, and an output of the AND gate is connected to a data input of the flip-flop. 7. A circuit state generator resident in the circuit under test, wherein the resident register comprises the register of claim 1. 8. The method of testing a digital system, wherein a pseudo-random test pattern is applied.
A method of changing the circuit state by changing the appearance frequency of the logical value 1 and the logical value 0 of the register output line using the described structure. 9. The method of claim 8, wherein the mode selection signal is generated as a weighted random sequence. 10. The method of claim 8, wherein the mode select signal is in the second logic state for n consecutive cycles of the input clock to the trap cell, followed by at least one clock cycle for mode select. Signal is first
A mode selection signal generation method that generates a sequence that has a repetitive and almost fixed configuration that results in one logic state. 11. A pseudo-random generator according to claim 8, wherein a random weighting operation is performed, a test sequence is generated according to a plurality of weight distributions, and these weight distributions are randomly selectable.