JPH0613587A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of transistors employed and constitute a large- scale exclusive circuit for reading with a few number of transistors by a method wherein the number of bits, constituted by a reading exclusive memory circuit or 4-bit data pattern groups, which are constitutable, are selected and read out. CONSTITUTION:A transistor 101, put on when a word line 108 is selected, supplies the potential of VDD to one diffusion area and connects the other diffusion area to the transistor row selecting wire 119 of N-channel transistor row, which constitutes the data of (0, 0, 0, 0). Another transistor 102, put on when another word line 109 is selected, supplies the potential of VSS to one diffusion area and connects the other diffusion area to the transistor row selecting wire 120 of a P-channel transistor row, which constitutes the data of (1, 0, 0, 0). By this method, necessary data can be read out with the number of transistors, which is fewer than the same so far.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device, and more particularly to a structure for writing and reading read data when forming a read only memory circuit of the device.

[0002]

2. Description of the Related Art Currently, when a logic including a read-only memory circuit is constructed in a master slice type semiconductor integrated circuit device which realizes a dedicated logic by manufacturing the basic cell first and changing a wiring process. And (1) a method of replacing the basic cell with a dedicated read-only memory circuit basic cell in which read data is written only in an area of the read-only memory circuit, (2) the basic cell without using the read-only memory circuit dedicated basic cell There is a method of writing data by electrically connecting the power supply wiring layer with a metal wiring.

When the method (1) and the method (2) are compared, in the method (1), the read data of the read-only memory circuit differs depending on the logic of the integrated circuit to be formed, and the read data is dedicated to each logic circuit. A read-only memory circuit area in which read data is written is required. Therefore, it is impossible to realize a dedicated logic by changing only the wiring process, and a master slice type semiconductor integrated circuit device characterized by realizing a dedicated integrated circuit in a short period only by changing the wiring process. A suitable method is (2). In the case of (2), an N-channel transistor which constitutes the basic cell,
Alternatively, the read data is written by supplying the first potential (hereinafter, VDD) or the second potential (hereinafter, VSS) which is read data to one diffusion region of the P-channel transistor. A basic cell of a master slice type semiconductor integrated circuit device is usually composed of one or more P-channel transistors and one or more N-channel transistors, and the P-channel transistors and the N-channel transistors are regularly arranged. Therefore, the writing of the read data does not depend on the P-channel transistor and the N-channel transistor, and the potential VDD is applied to the diffusion region of the transistor.
Alternatively, when the read-only memory circuit is configured, the potential VSS can be supplied, which is desirable in terms of cell arrangement in the circuit.

FIG. 6 shows an example of a circuit diagram of a read-only memory circuit in a conventional master slice type semiconductor integrated circuit device. In FIG. 6, reference numerals 601, 602, ..., 608 denote N-channel transistors and P-channel transistors which form the basic cell. 609, 610, 611, 6
12 is a read-only memory circuit device word line;
Reference numeral 614 is a bit line of the read-only memory circuit device.
When the word line 609 is selected, the N-channel transistors 601, 605 are turned on, and the word lines 610, 611, 6
The N-channel transistors and P-channel transistors 602 to 604 and 606 to 608 connected to 12 are turned off, VSS is applied to the bit line 613 and V is applied to the bit line 614.
The potential of DD is output.

FIG. 7 shows a layout example of the read-only memory circuit shown in FIG. In FIG. 7, 701 and 702 are N
Channel transistors, 703 and 704 are P-channel transistors, 705, 706, 707 and 708 are word lines, 724 and 725 are bit lines, 709 is power supply wiring of the first metal wiring layer having a VSS potential, and 710 is a VDD potential. 2 shows a power supply wiring of a first metal wiring layer having a. The word line 705 corresponds to 609 in FIG. Similarly word line 7
07, 706 and 708 correspond to 610, 611 and 612, and bit lines 724 and 725 correspond to 613 and 614. When writing LOW data to the N-channel transistor corresponding to 601 in FIG. 6, the power supply wiring 709 having the potential of VSS and the diffusion region of the N-channel transistor are first
Via 715 for electrical connection. In addition, 6 in FIG.
In the case of writing HI data in the N-channel transistor corresponding to 03, the power supply wiring 710 having the potential of VDD and N
The diffusion region of the channel transistor is electrically connected via the first via 716, the first metal wiring layer 722, the second via 719, the second metal wiring layer 723, and the second via 720. The written data is output to the bit line 724 of the second metal wiring layer via the first via 717, the first metal wiring layer 721, and the second via 718 when the data is selected. Data is written and read in the P-channel transistor with the same structure.

[0006]

However, the conventional method requires one or more transistors for each bit of data. Therefore, only the memory area (number of words) x
(Bit number) transistor. This increases the number of mounted gates and limits the number of random logic mounted gates in the current master slice type semiconductor integrated circuit device mounting a large scale memory. In addition, when a large-scale memory and a large-scale random logic gate are mounted, the area of the chip is increased and the cost is increased.

Further, when the potential of VDD is supplied to the N-channel transistor, even if the N-channel transistor is turned on, the potential of the bit line connected to the N-channel transistor is N-channel due to the operating principle of the N-channel transistor.
It rises only up to the potential dropped by the threshold potential of the channel transistor. Similarly, when the VSS potential is supplied to the P-channel transistor, the potential of the bit line to which the P-channel transistor is connected falls only to the potential increased by the threshold potential of the P-channel transistor. Therefore, current flows and power consumption increases.

Further, due to the difference in driving ability between the P-channel transistor and the N-channel transistor, Hi data, Lo
It is difficult to make the reading speed of w data uniform and high speed. The present invention solves the above-mentioned problems, and in a master slice type semiconductor integrated circuit device, a structure and power consumption for efficiently using the transistors in a basic cell to configure a large-scale memory with a small number of transistors are provided. It is an object to provide a structure that suppresses and facilitates increasing the reading speed.

[0009]

A basic cell composed of one or more N-channel transistors and one or more P-channel transistors forming logic on a semiconductor substrate, and an input / output basic cell and package forming input / output logic are provided. In a master slice type semiconductor integrated circuit device in which input / output terminals directly electrically connected are regularly arranged, reading is performed on an arbitrary metal wiring layer of a logic circuit metal wiring layer formed by the semiconductor integrated circuit device. A dedicated word line exists, a read-only bit line exists in any metal wiring layer of the logic circuit metal wiring layer, and at least one gate electrode of the N-channel transistor forming the basic cell is connected. By connecting one or more of the gate electrodes of the N-channel transistor array or the P-channel transistor of the basic cell. There is a P-channel transistor array configured by the above, one of the diffusion regions of the N-channel transistors in the N-channel transistor sequence has a potential of VSS or VDD, and the other diffusion region is electrically connected to the bit line. Connection, one of the diffusion regions of the P-channel transistors in the P-channel transistor array is VSS or V
The other diffusion region having a potential of DD is electrically connected to the bit line, and the word line is electrically connected to a gate electrode of an N-channel transistor or a P-channel transistor forming the basic cell, One diffusion region of the N-channel transistor or the P-channel transistor is supplied with the potential of VDD and the other diffusion region is connected to the gate electrode of the N-channel transistor row, or
One of the diffusion regions of the channel transistor or the P-channel transistor is supplied with the potential of VSS, the other diffusion region is connected to the gate electrode of the P-channel transistor array, and the bit line is the first support bit line and the second support bit line. One of the diffusion regions of the N-channel transistors, which is formed of a support bit line and constitutes the N-channel transistor train, has the potential of VSS, and the other diffusion region of the N-channel transistor is the first or second support bit. One of the diffusion regions of the P-channel transistors connected to a line or constituting the P-channel transistor array has a potential of VDD, and the other diffusion region of the P-channel transistor is connected to the first or second sub bit line. An inverted signal of the first support bit line that is connected and constitutes the bit line is input to the second support bit line. And an inversion signal of the second support bit line forming the bit line is input to the first support bit line, and two or more word lines are provided in one or more word lines of the word lines. The gate electrodes of the N-channel transistors or the two or more P-channel transistors are electrically connected, and one diffusion region shared by the two or more N-channel transistors or the two or more P-channel transistors is VDD. The other diffusion region which is supplied with and shared with the electric potential is electrically connected to the gate electrode of the N-channel transistor array, or one diffusion shared by the two or more N-channel transistors or the two or more P-channel transistors. The other diffusion region to which the region is supplied with the potential of VSS and is shared is electrically connected to the gate electrode of the P-channel transistor array. Or the gate electrodes of the two or more P-channel transistors in which the bit lines or the first (second) support bit lines are connected in parallel or the two or more N-channel transistors in parallel. It is electrically connected to the gate electrode of.

A basic cell composed of one or more N-channel transistors and one or more P-channel transistors forming logic on a semiconductor substrate, an input / output basic cell forming input / output logic, and a package are directly electrically connected. In a master slice type semiconductor integrated circuit device in which input / output terminals are regularly arranged, a read-only word line exists in an arbitrary metal wiring layer of a logic circuit metal wiring layer formed by the semiconductor integrated circuit device. However, a read-only bit line exists in any metal wiring layer of the logic circuit metal wiring layer, and an N-channel transistor formed by connecting at least one gate electrode of the N-channel transistor forming the basic cell is formed. Channel transistor row or P that constitutes the basic cell
There is a P-channel transistor array formed by connecting one or more of the gate electrodes of the channel transistors, and one of the diffusion regions of the N-channel transistors in the N-channel transistor array has a potential of VSS or VDD. The other diffusion region is electrically connected to the bit line,
One of the diffusion regions of the P-channel transistors in the P-channel transistor array has a potential of VSS or VDD, and the other diffusion region is electrically connected to the bit line,
Independent of the word line unit, the two independent cells that form the basic cell
Gate electrodes of at least two N-channel transistors or at least two independent P-channel transistors are electrically connected, and the at least two independent N-channel transistors or at least two independent P-channel transistors are independent. One of the diffusion regions is supplied with the potential of VDD and the other diffusion region is connected to the gate electrode of the N-channel transistor array, or the two or more independent N-channel transistors or the two or more independent P-channel transistors. Independently, one of the diffusion regions is supplied with the potential of VSS, the other diffusion region is connected to the gate electrode of the P-channel transistor array, and the bit line is the first support bit line and the second support bit. One of the diffusion regions of the N-channel transistors which are formed by lines and constitute the N-channel transistor array The other diffusion region of the N-channel transistor having the potential of VSS is connected to the first or second support bit line, or one of the diffusion regions of the P-channel transistors forming the P-channel transistor row is VDD. The other diffusion region of the P-channel transistor having a potential is connected to the first or second support bit line, and an inversion signal of the first support bit line forming the bit line is applied to the second support bit line. An inversion signal of the second supporting bit line which is inputted to the bit line and which constitutes the bit line is inputted to the first supporting bit line, and is independently connected in units of the word line. The independent two or more N-channel transistors share the diffusion region in units of the transistors and one or more N-channel transistors are connected in parallel, or Of the two or more independent P-channel transistors that are independently connected in line units, the diffusion region is shared by the transistor units, and one or more P-channel transistors are connected in parallel, One is supplied with the potential of VDD and the other shared diffusion region is connected to the gate electrode of the N-channel transistor array, or one of the shared diffusion regions is VS.
The other shared diffusion region supplied with the potential of S is connected to the gate electrode of the P-channel transistor array, or two or more of the bit lines or the first (second) supporting bit lines are connected in parallel. The gate electrode of the P-channel transistor or two or more of the N connected in parallel
It is characterized in that it is electrically connected to the gate electrode of the channel transistor.

[0011]

FIG. 1 shows an example of a circuit diagram of a read-only memory circuit in a master slice type semiconductor integrated circuit device of the present invention. The read-only memory circuit of FIG. 1 has a structure of M words × 4 bits. 1, 101, 102, ... 10 in FIG.
Reference numeral 7 denotes an N-channel transistor and a P-channel transistor which form the basic cell. 108, 109,
Reference numerals 110 and 111 are word lines of the read-only storage circuit device, and reference numerals 112, 113, 114 and 115 are bit lines of the read-only storage circuit device. Also, 122, 123,
Reference numerals 124 and 125 are logic circuits connected to the bit line. In FIG. 1, 116, 117 and 118 are N of the present invention.
The N-channel transistor array 116 is a channel transistor array or a P-channel transistor array, and the N-channel transistor array 116 includes a plurality of N-channel transistors including the N-channel transistor 105 in the basic cell.
The transistor column selection line 11 of the present invention is configured by a channel transistor, and the gate electrode is electrically connected.
Make up 9. Similarly, the P-channel transistor array 11
7 and 118 are P-channel transistors 106 and 10, respectively.
A plurality of P-channel transistors including the gate electrodes are electrically connected to form the transistor column selection lines 120 and 121 of the present invention. In the case of the read-only memory circuit having M words × 4 bits, the data that can be represented by 4 bits is a combination pattern of 4 bits of binary (0, 1) that can be represented by 1 bit. That is, in the case of 4 bits, there are 16 patterns. Therefore, the data is (0, 0, 0, 0) in the case of the read-only memory circuit having a 4-bit structure, regardless of the number of words.
16 of (1, 0, 0, 0), ... (1, 1, 1, 1)
Only patterns. In the present invention, the data represented by the number of bits is formed by the transistor array, that is, 16 patterns in the case of 4 bits. In FIG. 1, the transistor array 116 is (0, 0, 0, 0), the transistor array 117 is (1, 0, 0, 0), and the transistor array 118.
Constitute (1, 1, 1, 1) and each has a dedicated transistor column selection line. The transistor 101 which is selected when the word line 108 is turned on is supplied with the potential of VDD in one diffusion region, and the other diffusion region is (0, 0, 0,
0) Data is connected to the transistor column selection line 119 of the N-channel transistor column. Similarly, in the transistor 102 in which the word line 109 is selected and turned on, the potential of VSS is supplied to one diffusion region, and the other diffusion region is a P-channel transistor array forming data (1, 0, 0, 0). Connected to the transistor column selection line 120. Then, when the word line 108 is selected, the data of (0, 0, 0, 0) is output onto the bit line by the transistor column selection line 119 connected to the transistor 101 connected to the selected word line. To be done. In this case, in the conventional method, the number of transistors in the memory cell region is Mx4, whereas in the structure of the present invention, the number of transistors is M + (16x4). That is, 256
In the case of the word × 4 bit structure, the conventional method requires 1024 transistors, whereas the method of the present invention requires 320 transistors. Therefore, with the structure for selecting the data pattern represented by the number of bits as in this embodiment, it is possible to read out the required data with a smaller number of transistors than in the conventional case.

FIG. 2 shows an example of a circuit diagram in which the number of bits of the read-only memory circuit in the master slice type semiconductor integrated circuit device of the present invention is divided into blocks. The read-only memory circuit has a structure of M words × 4 bits, and 4 bits are 2 bits × 2 blocks. In FIG. 2, 201, 20
2, ... 210 represent N-channel transistors and P-channel transistors which form the basic cell. Two
Reference numerals 11, 212 and 213 are word lines of the read-only memory circuit device, and 214, 215, 216 and 217 are bit lines of the read-only memory circuit device. Also, 218, 21
Reference numerals 9, 220 and 221 denote logic circuits connected to the bit line. 222, 223, 224, and 225 in FIG.
Is an N-channel transistor array or a P-channel transistor array of the present invention.
22 is composed of a plurality of N-channel transistors including the N-channel transistor 207 in the basic cell, and the gate electrodes thereof are electrically connected to each other to form the transistor column selection line 226 of the present invention. Similarly, the transistor array 22
3, 224 and 225 are transistors 208 and 20 respectively.
Composed of a plurality of transistors including 9, 210,
The gate electrodes are electrically connected to form the transistor column selection lines 227, 232, 233 of the present invention. In this embodiment, 4 bits are divided into blocks of 2 bits. The transistor 202 which is turned on when the word line 212 is selected supplies the VSS potential to one diffusion region, and the other diffusion region forms the data of (1, 1) in the transistor channel selection line of the P-channel transistor column 225. Two
The transistor 205 connected to the transistor 33 and turned on at the same time as the transistor 202 supplies the VDD potential to one diffusion region, and the other diffusion region forms the data of (0, 0) in the N-channel transistor array 222. It is connected to the column selection line 226. Therefore, the word line 212
Is selected, the transistor column selection lines 233 and 226 connected to the transistors 202 and 205 connected to the selected word line select (1,
The data 1) and (0, 0) are output to form 4-bit data. In this case, in the conventional method, the number of transistors in the memory cell region is Mx4, whereas in the structure of the present invention, the number of transistors is 2x (M + (4x2)).
It is an individual. That is, in the case of a 256 word × 4 bit structure, the conventional method requires 1024 transistors, whereas the method of the present invention requires 528 transistors.
Individuals are all right. Therefore, even if the number of bits is divided as in the present embodiment, it is possible to read out the necessary data with a smaller number of transistors than the conventional one by providing the selecting transistor in each block. Also, by dividing,
Since the number of patterns of blocks is reduced, efficient placement is possible and the degree of freedom of placement is improved.

FIG. 3 shows a first (second) support bit line and a second (first) bit line for stabilizing the potential of the gate electrode of the logic non-inverting circuit or the logic inverting circuit of the present invention to the potential of VDD or VSS. The structural example of the bit line by a support bit line is shown. Figure 3
, 301, 302, ..., 307 denote N-channel transistors and P-channel transistors which form the basic cell. Reference numerals 308, 309, and 310 are word lines of the read-only memory circuit device, and 311 are bit lines of the read-only memory circuit device. In FIG. 3, reference numeral 312 is the first (second) support bit line of the present invention, and 313 is the second support bit line of the present invention.
This is the (first) support bit line. The first (second) support bit line 312 is electrically connected to the bit line 311 through a logic inversion circuit 314, and the second (first) support bit line 313 is a logic forward circuit 315. Through the bit line 3
11 electrically connected. In addition, one diffusion region of the N-channel transistor used as a memory cell is always V
The potential of SS is supplied, and one diffusion region of the P-channel transistor is always supplied with the potential of VDD. In the N-channel transistor, the other diffusion region is connected to the support bit line connected to the normal logic circuit to output 0 data, and is connected to the support bit line connected to the inversion logic circuit to output 1 data. Output the data. Similarly, in the P-channel transistor, the other diffusion region is connected to the support bit line connected to the normal logic circuit to output one data and connected to the support bit line connected to the inversion logic circuit. To output 0 data. Therefore, regardless of the data to be output, the diffusion region of the N-channel transistor is VS
The potential of S, VD in the diffusion region of the P-channel transistor
Since the potential of D is supplied, the current consumption of the potentials of VSS and VDD flowing to the other diffusion region when the transistor is turned on is suppressed. Further, the structure in which the bit line is composed of the first and second support bit lines is not related to the circuit structure shown in FIGS.

FIG. 4 shows an example of a configuration in which a plurality of transistors according to the present invention reads a set of data from a transistor array.
The plurality of N-channel transistors 404 and 405 are turned on or off by the word line 410, and select / unselect signals are transmitted to the same transistor select line 418. Data read time by determining the number of the transistors according to the charge / discharge time of the potential of the transistor array and the transistor selection line relative to the transistor selection line determined by the relative positional relationship between the transistor array and the transistor array selection transistor Can be changed.

FIG. 5 shows a configuration example of a logic circuit connected to the bit line of the present invention. When an N-channel transistor and a P-channel transistor are connected to the bit line, the input circuit of the logic circuit is composed of two P-channel transistors connected in parallel and one N-channel transistor, and the gain coefficient of the transistor is By decreasing the ratio-gain coefficient of N-channel transistor / gain coefficient of P-channel transistor-to bring the gate threshold value of the logic inversion circuit close to the potential of VDD / 2, it is possible to speed up data reading.

[0016]

As described above, according to the present invention, in the master slice type semiconductor integrated circuit device, the 4-bit data pattern set in which the number of bits of the read-only memory circuit can be configured is selected and read. It is possible to reduce the number of transistors used, and it is possible to configure a large-scale read-only circuit with a small number of transistors.
The chip area can be reduced and the cost can be reduced.

By setting the logic inversion circuit between the support bit lines for reading the data pattern, it is possible to suppress the current consumption.

Then, by increasing the number of transistors selected and operated by the word line and connected to the transistor row selection line in parallel according to the connection point and the wiring length of the transistor row, high speed is achieved. In addition, the data can be read out.

Further, by constructing a logic circuit connected to the bit line by N-channel transistors connected in parallel or P-channel transistors connected in parallel, the gate threshold value can be changed and data can be read at high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a read-only memory circuit M word × 4 bits in a master slice type semiconductor integrated circuit device of the present invention.

FIG. 2 is a read-only memory circuit M word x (2 bits x in the master slice type semiconductor integrated circuit device of the present invention.
It is a circuit diagram of (2 blocks).

FIG. 3 is a configuration of a bit line including a first (second) support bit line and a second (first) support bit line for stabilizing the potential of the gate electrode of the logic non-inverting circuit or the logic inverting circuit of the present invention. It is a figure which shows an example.

FIG. 4 is a diagram showing a configuration example of reading one data from a plurality of transistors of the present invention.

FIG. 5 is a diagram showing a configuration example of a logic circuit connected to a bit line of the present invention.

FIG. 6 is a diagram showing an example of a circuit of a read-only memory circuit in a conventional master slice type semiconductor integrated circuit device.

FIG. 7 is a layout example diagram of a circuit diagram of a read-only memory circuit in a conventional master slice type semiconductor integrated circuit device.

[Explanation of symbols]

101, 102, 103, 104, 105, 201, 2
02, 203, 204, 205, 206, 207, 20
9, 301, 302, 303, 304, 306, 40
1, 402, 403, 404, 405, 406, 40
7, 501, 502, 503, 513, 516, 60
1, 603, 605, 607, 701, 702 ...
N-channel transistors 106, 107, 208, 210, 305, 307, 5
04, 511, 512, 514, 515, 602, 60
4, 606, 608, 703, 704 ... P-channel transistors 108, 109, 110, 111, 211, 212, 2
13, 308, 309, 310, 408, 409, 41
0, 516, 517, 609, 610, 611, 61
2, 705, 706, 707, 708 ... Word lines 112, 113, 114, 115, 214, 215, 2
16, 217, 311, 411, 412, 509, 61
3, 614, 724, 725 ... Bit lines 116, 117, 118, 222, 223, 224, 2
25, 316, 317, 419, 420, 505, 50
6 ... Transistor rows 119, 120, 121, 226, 227, 228, 2
29, 230, 231, 232, 233, 318, 31
9, 320, 321, 415, 415, 417, 41
8, 507, 508 ... Transistor column selection line 312, 313 ... Support bit line 314, 322, 323 ... Logic inversion circuit 122, 123, 124, 125, 218, 219, 2
20, 221, 315, 413, 414, 510 ...
Logic forward circuit 709, 710 ... Power source first metal wiring 711, 712 ... Gate electrode 713, 714, 715, 716, 717 ... First via 718, 719, 720 ... Second Vias 721, 722 ... Logic first metal wiring layer 723 ... Logic second metal wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/10 471 8728-4M 9054-4M H01L 27/08 321 J

Claims (8)

[Claims] 1. A basic cell consisting of one or more N-channel transistors and one or more P-channel transistors forming logic on a semiconductor substrate, and an input / output basic cell forming input / output logic and a package directly electrically. In a master slice type semiconductor integrated circuit device in which input / output terminals to be connected are regularly arranged, a read-only word line is formed on an arbitrary metal wiring layer of a logic circuit metal wiring layer formed by the semiconductor integrated circuit device. A read-only bit line exists in any metal wiring layer of the logic circuit metal wiring layer, and one or more gate electrodes of N-channel transistors forming the basic cell are connected to each other. Or an N-channel transistor array that connects the gate electrodes of the P-channel transistors that form the basic cell. Of the N-channel transistors, one of the diffusion regions of the N-channel transistors in the N-channel transistor column has a second potential or a first potential, and the other diffusion region is electrically connected to the bit line. , One of the diffusion regions of the P-channel transistors in the P-channel transistor array has a second potential or a first potential, and the other diffusion region is electrically connected to the bit line, and the word The gate electrode of the N-channel transistor or the P-channel transistor which constitutes the basic cell is electrically connected to the line, and one diffusion region of the N-channel transistor or the P-channel transistor is supplied with the first potential and the other diffusion A region connected to the gate electrode of the N-channel transistor array, or the N-channel transistor or P-channel transistor Master slice semiconductor integrated circuit device, characterized in that the other diffusion region is supplied is connected to the gate electrode of the P-channel transistor arrays 1-way diffusion region a second potential of. 2. The master slice type semiconductor integrated circuit device according to claim 1, wherein the bit line is composed of a first support bit line and a second support bit line to form the N-channel transistor array. One of the diffusion regions of the N-channel transistor has a second potential, and the other diffusion region of the N-channel transistor is connected to the first or second support bit line, or P constituting the P-channel transistor string. One of the diffusion regions of the channel transistor is the first
And the other diffusion region of the P-channel transistor is connected to the first or second support bit line, and an inversion signal of the first support bit line forming the bit line is applied to the second support bit line. A master slice type semiconductor integrated circuit device, characterized in that an inverted signal of the second auxiliary bit line which is input to the auxiliary bit line and which constitutes the bit line is input to the first auxiliary bit line. 3. The master slice type semiconductor integrated circuit device according to claim 1, wherein two or more N-channel transistors or two or more of the word lines are provided in one or more word lines of the word lines. The gate electrode of the P-channel transistor is electrically connected, and the one or more diffusion regions shared by the two or more N-channel transistors or the two or more P-channel transistors are supplied with the first potential and shared by the other. The diffusion region is electrically connected to the gate electrode of the N-channel transistor array, or the two or more N
A channel transistor or one diffusion region shared by two or more P-channel transistors is supplied with a second potential, and the other diffusion region shared is electrically connected to the gate electrode of the P-channel transistor array. A master slice type semiconductor integrated circuit device characterized. 4. The master slice type semiconductor integrated circuit device according to claim 1, wherein the bit line or the first (second) support bit line is connected in parallel.
A master slice type semiconductor integrated circuit device, wherein the master slice type semiconductor integrated circuit device is electrically connected to the gate electrodes of at least two P-channel transistors or the gate electrodes of at least two N-channel transistors connected in parallel. 5. A basic cell composed of one or more N-channel transistors and one or more P-channel transistors forming a logic on a semiconductor substrate, and an input / output basic cell forming an input / output logic and a package directly electrically. In a master slice type semiconductor integrated circuit device in which input / output terminals to be connected are regularly arranged, a read-only word line is formed on an arbitrary metal wiring layer of a logic circuit metal wiring layer formed by the semiconductor integrated circuit device. A read-only bit line exists in any metal wiring layer of the logic circuit metal wiring layer, and one or more gate electrodes of N-channel transistors forming the basic cell are connected to each other. Or an N-channel transistor array that connects the gate electrodes of the P-channel transistors that form the basic cell. Of the N-channel transistors, one of the diffusion regions of the N-channel transistors in the N-channel transistor column has a second potential or a first potential, and the other diffusion region is electrically connected to the bit line. , One of the diffusion regions of the P-channel transistors in the P-channel transistor array has a second potential or a first potential, and the other diffusion region is electrically connected to the bit line, and the word Two or more independent N-channel transistors or two independent N-channel transistors that form the basic cell on a line-by-line basis.
The gate electrodes of the plurality of P-channel transistors are electrically connected to each other, and the independent two or more N-channel transistors or the independent two or more P-channel transistors are independent of each other in one of the diffusion regions. The other diffusion region, which is supplied with a potential, is connected to the gate electrode of the N-channel transistor array, or the two or more independent N-channel transistors or the two or more independent P-channel transistors are independent of one of the diffusion regions. A master slice type semiconductor integrated circuit device, characterized in that a second potential is supplied to the other and the other diffusion region is connected to the gate electrode of the P-channel transistor array. 6. The master slice type semiconductor integrated circuit device according to claim 5, wherein the bit line is composed of a first support bit line and a second support bit line to form the N-channel transistor array. One of the diffusion regions of the N-channel transistor has a second potential, and the other diffusion region of the N-channel transistor is connected to the first or second support bit line, or P constituting the P-channel transistor string. One of the diffusion regions of the channel transistor is the first
And the other diffusion region of the P-channel transistor is connected to the first or second support bit line, and an inversion signal of the first support bit line forming the bit line is applied to the second support bit line. A master slice type semiconductor integrated circuit device, characterized in that an inverted signal of the second auxiliary bit line which is input to the auxiliary bit line and which constitutes the bit line is input to the first auxiliary bit line. 7. The master slice type semiconductor integrated circuit device according to claim 5, wherein the two or more independent N-channel transistors connected independently in units of the word line. The diffusion region is shared by one unit and one or more N-channel transistors are connected in parallel, or the independent two or more P-channel transistors are independently connected in the word line unit One or more P-channel transistors sharing the diffusion region and connected in parallel, one of the shared diffusion regions is supplied with the first potential, and the other shared diffusion region is connected to the gate electrode of the N-channel transistor array. Alternatively, one of the shared diffusion regions is supplied with the second potential and the other shared diffusion region is connected to the gate electrode of the P-channel transistor array. A master slice type semiconductor integrated circuit device characterized by: 8. The master slice type semiconductor integrated circuit device according to claim 5, wherein said bit line or said first (second) support bit line is connected in parallel.
A master slice type semiconductor integrated circuit device, wherein the master slice type semiconductor integrated circuit device is electrically connected to the gate electrodes of at least two P-channel transistors or the gate electrodes of at least two N-channel transistors connected in parallel.