JPH06132490A - Semiconductor element and fabrication thereof - Google Patents

Abstract

PURPOSE:To reduce the area of an MIM capacitor by forming source-drain-gate electrodes on the main surface of a semi-insulating GaAs substrate at a FET part whereas forming an underlying electrode of AuGe/Ni/Au simultaneously with formation of source-drain electrodes on the main surface of the semi- insulating GaAs substrate at a capacitor part. CONSTITUTION:A FET part 2 is constituted of a source region 4 and a drain region 5, an n-type channel region 6 extending between the pair of regions, a source electrode 10 and a drain electrode 11 provided on the source region 4 and the drain region 5, and a gate electrode 12 provided on the channel region 6. At a capacitor part 3, an underlying electrode 20 is provided on the main surface of a semi-insulating GaAs substrate 1. The underlying electrode 20 is formed of an AuGe/Ni/Au film simultaneously with formation of the source- drain-gate electrodes 10, 11, 12. This structure decreases the area of the capacitor part 3 and presents a high capacity MIM capacitor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, particularly a metal
Insulator-MIM (MIM) three-layer structure
The present invention relates to a semiconductor device having a capacitance and a manufacturing method thereof,
For example, the present invention relates to a technique effectively applied to a GaAs IC having a built-in capacitance.

[0002]

2. Description of the Related Art As a microwave transistor having features such as low noise, high cutoff frequency, and high output, a gallium arsenide field effect transistor (abbreviated as GaAs-FET) formed based on a substrate having a zinc blende type crystal structure. .) Is widely known. A Schottky barrier gate type field effect transistor (also called MESFET) is known as one of the GaAs-FETs. MES
The FET is composed of a source / drain electrode having an ohmic contact structure provided on the main surface of an n-conductive type active region and one or two gate electrodes having a Schottky junction structure provided in the middle thereof, and has a single gate structure. Alternatively, it constitutes a dual gate structure.

These GaAs-MESFETs are incorporated in a broadband low noise GaAs IC for communication. For the broadband low-noise GaAs IC for communication, see, for example, "Technical Report of IEICE Technical Report", 1
Published January 22, 985, SSD84-106, P24
~ P31. In the consumer-use GaAs broadband low-noise amplifier IC described in this document, FE
T has an Al gate planar structure, and a resistor and a Schottky capacitor are incorporated in series between the gate and the drain. The source / drain electrodes are AuGe.
It is described that the interlayer insulating film is formed of a PSG film as well as being formed of a system.

On the other hand, there is a GaAs IC in which a capacitance is formed by an MIM capacitance. For example, "MMIC:
GaAs FETs and HEMTs "Peter
HLadbroke Director, Gabs
Code Ltd, Arttech House, Bos
ton and London 1989, P2
9 to P53 describe passive components in MMIC. Further, in P29 of this document, MESF
The ET, the diode, the resistor, the MIM capacitance and the like are shown, and the explanation of the MIM capacitance is given in P46.

On the other hand, "solid state technology Japan edition", issued by Nippon SST Co., Ltd., January 1989, P21 to P24, MMIC formed using a semi-insulating undoped GaAs substrate has a thickness of 200 nm. An example of using Si ₃ N ₄ as an insulator of MIM capacitor is shown.

[0006]

PROBLEM TO BE SOLVED BY THE INVENTION GaAs with a built-in capacitor
In the IC, the MIM capacitance is adopted as the capacitance. For example, FIG. 9 shows a GaAs IC developed by the present applicant.
FIG. 9 is a view showing the main part of FIG. 1, in which the FET and the MIM capacitor are incorporated in a single semiconductor substrate. That is, this GaA
The sIC is composed of a semi-insulating GaAs substrate 1 with a FET portion 2 on the main surface.
And the capacitance part 3 are adjacent to each other. FET part 2
Is a source region 4 and a drain region 5 made of an n ⁺ type layer, a channel region 6 made of an n type layer extending between the pair of regions, the source region 4 and the drain region 5.
Source electrode 10 and drain electrode 11 provided on top
And the gate electrode 12 provided on the channel region 6.
It consists of The source electrode 10 and the drain electrode 11 are made of a film made of AuGe / Ni / Au and are in ohmic contact with the source region 4 and the drain region 5, respectively. In addition, the gate electrode 12 is
It is composed of an Al film and forms a Schottky barrier junction with the channel region 6. The source electrode 10 and the drain electrode 1 are formed on the main surface of the semi-insulating GaAs substrate 1.
1. An insulating film made of a PSG film 15 that electrically separates the gate electrode 12 is provided. In addition, this PSG film 1
5, source electrode 10, drain electrode 11, gate electrode 1
The PSG film 16 is provided so as to cover 2. A wiring layer 17 made of Al is provided on the PSG film 16. When the wiring layer 17 is formed, the PSG
As a result of filling the contact through holes previously provided in the film 16 with Al, the respective wiring layers 17 are formed.
Is a source electrode 10, a drain electrode 11, a gate electrode 12
Electrical contact. On the other hand, in the capacitance section 3,
A lower layer electrode 20 is provided on the main surface of the semi-insulating GaAs substrate 1, and a capacitive insulating film 2 is formed on the lower layer electrode 20.
1, the upper layer electrode 22 is provided, and the MIM capacitor is formed. The capacitance insulating film 21 is the PSG film 16 formed in the FET part 2, and the upper layer electrode 22 is the FET part 2
It is formed simultaneously with the wiring layer 17 formed in.

In the MIM capacitor having such a structure,
The thickness of the capacitance insulating film 21 is PS in the FET portion 2.
It is determined by the thickness of the G film 16. The thickness of the PSG film 16 is determined from the viewpoint of breakdown resistance and the like.
Å The thickness before and after is adopted. The capacitance increases as the dielectric constant of the capacitance insulating film (dielectric) increases. The capacitance is inversely proportional to the thickness of the capacitive insulating film and proportional to the area. As mentioned above,
In the case of a MIM capacitor having a PSG film with a dielectric constant of 3.9 and a thickness of 7,000 Å, in order to obtain a capacitance of 0.5PF,
The area of the electrodes (upper and lower layer electrodes) is about 10,000 μm ² , and the ratio of the area of the capacitor portion to the area of the semiconductor element becomes large. Therefore, the MIM having such a structure
It is difficult to reduce the size of a semiconductor device incorporating a capacitor.

In order to increase the capacitance, it is desirable to use an insulating film having a high dielectric constant and to make the insulating film thin. Conventionally, as shown in the above document, Si ₃ N ₄ (nitride) having a large permittivity of 7 is used with respect to the permittivity of 3.9 of the PSG film.

Therefore, the inventors of the present invention have also used the Ga
In order to increase the capacity of the AsIC, the capacity insulating film is not shared with the insulating film of the FET section, and the capacity insulating film is a plasma nitride film (PS) having a thickness of about 2000Å.
It was attempted to form with an iN film). FIG. 10 shows the structure. In the case of the GaAs IC, the lower electrode 20 is AuG.
e / Ni / Au, and S directly by plasma
When the iN film is formed, Au reacts with Si, which is not preferable. Therefore, before forming the P-SiN film, a thickness of 1 is formed by a CVD method so that reaction inhibition does not occur.
A reaction blocking film 25 made of a PSG film of about 000Å was formed. In addition, in the capacitance portion 3, the reaction blocking film 25
A high dielectric film 26 made of a plasma nitride film (P-SiN film) having a thickness of about 2000 Å is partially provided on the top. Then, at the same time when the wiring layer 17 is provided in the FET portion 2, a through hole for contact is formed in the PSG film 16 of the capacitance portion in order to provide the upper layer electrode 22 of the MIM capacitance in the capacitance portion 3, and Al is formed in this through hole portion. A method of forming the upper electrode 22 by providing the above has been developed.

However, in this manufacturing method, the sum of the insulating films on the source electrode 10, the drain electrode 11 and the gate electrode 12 in the FET portion 2 is the reaction blocking film 25 and the PSG.
In contrast to the sum of the film 16, the thickness of the insulating film on the high dielectric film 26 of the capacitor section 3 is only the PSG film 16, and if a through hole is formed in the same step, The high dielectric film 26 is etched and the desired capacitance cannot be obtained. Therefore, the through hole forming process in the FET part 2 and the through hole forming process in the capacitor part 3 must be performed separately, and the photolithography process with high production cost will increase.

An object of the present invention is to provide a technique for manufacturing a semiconductor device capable of reducing the area of the MIM capacitor.

Another object of the present invention is to reduce the manufacturing cost of a semiconductor device by reducing the number of steps in forming MESFETs and MIM capacitors. The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0013]

The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the semiconductor device of the present invention is G
The circuit structure has an MIM capacitance in series between the source and drain of the aAs-MESFET, and the FET portion has a source / drain / gate electrode on the main surface of the semi-insulating GaAs substrate and the capacitor portion is semi-insulating. Sex Ga
The structure is such that the lower surface electrode made of AuGe / Ni / Au is formed on the main surface of the As substrate at the same time when the source / drain electrodes are formed. In the FET part, the source / drain / gate electrodes are covered with a reaction blocking film made of a CVDPSG film and a main insulating film made of a CVDPSG film, and a through hole contact part is provided in the main insulating film and the reaction blocking film. The wiring layers are in electrical contact with the source / drain / gate electrodes, respectively. Further, in the capacitance part, a capacitance insulating film and an upper layer electrode provided on the capacitance insulating film are formed on the lower layer electrode. The capacitive insulating film has a lower layer serving as the reaction blocking film and an upper layer serving as a high dielectric film made of a plasma nitride film. The upper layer electrode is formed by providing a through hole in the insulating film on the capacitive insulating film provided on the capacitive insulating film and a wiring layer provided in the through hole portion. The insulating film on the capacitive insulating film is composed of a dummy insulating film provided on the high dielectric film and a main insulating film provided on the dummy insulating film. In addition, the dummy insulating film is made of C having the same thickness as the reaction blocking film.
It is formed of a VDPSG film.

In the manufacture of such a semiconductor device, AuGe is formed on the main surface of the semi-insulating GaAs substrate.
/ Ni / Au is selectively formed to form source / drain electrodes in the FET part and lower layer electrodes in the capacitor part. Then, a gate electrode is formed in the FET section. Next, a reaction blocking film made of a CVDPSG film having a thickness of about 1000Å, a high dielectric film made of a plasma nitride film having a thickness of about 2000Å, and the same thickness as the reaction blocking film are formed on the entire main surface of the semi-insulating GaAs substrate. A dummy insulating film made of the CVDPSG film is formed. Next, the high dielectric film and the dummy insulating film on the lower electrode are formed only on the lower electrode by selective etching. Next, a main insulating film made of a CVDPSG film having a thickness of about 6000 Å is provided on the entire main surface side of the semi-insulating GaAs substrate 1. Next, through holes are provided on the source / drain / gate electrodes of the FET section and on the dummy insulating film of the capacitor section by simultaneous processing. Next, after Al is vapor-deposited on the main insulating film, selective etching is performed to form a wiring layer connected to the source / drain / gate electrodes and an upper layer electrode formed on the high dielectric film. Further, a metal film mainly composed of Al is provided on the main insulating film by sputtering or the like, and this film is selectively etched to be provided on the wiring layer connected to the source / drain / gate electrodes and the high dielectric film. An upper layer electrode is formed.

[0015]

According to the above-mentioned means, in the semiconductor element constituting the GaAsIC having the MIM capacitance of the present invention,
A PSG film as a capacitance insulating film for the MIM capacitor, and this PSG film
A plasma nitride film having a dielectric constant about 1.8 times higher than that of the film is used, and the PSG film is 1000 Å
On the other hand, since the plasma nitride film is as thin as about 2000 Å, the MIM capacitance is as high as about 1.65 PF when the electrode area is about 10000 μm ² . Further, in the semiconductor element of the present invention, since the thickness of the insulating film on the capacitor insulating film and the thickness of the insulating film on the source / drain / gate electrodes are the same,
When forming a through hole in the insulating film on the gate electrode,
Through holes can also be formed in the insulating film on the capacitor insulating film,
Further, since the wiring layer connected to the source / drain / gate electrodes and the upper electrode of the MIM capacitor can be simultaneously formed by the subsequent wiring layer formation, the manufacturing cost of the semiconductor element can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a main part of a semiconductor element that constitutes a GaAs IC with a built-in capacitor of the present invention, FIGS. 2 to 8 are cross-sectional views in each step of manufacturing the semiconductor element, and FIG. 3 is a cross-sectional view of a wafer in which ions are implanted into the substrate, FIG. 3 is a cross-sectional view of a wafer provided with a source electrode, a drain electrode, a gate electrode, and a lower layer electrode, and FIG. FIG. 5 is a sectional view of a wafer in which films are stacked, FIG. 5 is a sectional view of a wafer in which a dummy insulating film and a high dielectric film are selectively etched, and FIG. 6 is a wafer in which a main insulating film is provided on a main surface. FIG. 7 is a sectional view of a wafer in which through holes are formed in the FET section and the capacitor section, and FIG. 8 is a sectional view of a wafer in which a wiring layer and an upper layer electrode are provided.

In this embodiment, a GaAs-MESFET is used.
An example in which the present invention is applied to a GaAs IC with a built-in capacitor in which an MIM capacitor is serially incorporated between the gate and the drain will be described. As shown in FIG. 1, a semiconductor element (hereinafter, also referred to as a chip) that constitutes the GaAs IC is
The FET part 2 and the capacitor part 3 are formed on the main surface of the semi-insulating GaAs substrate 1.
It has a structure that is adjacent to. The FET portion 2 includes a source region 4 and a drain region 5 made of an n ⁺ -type layer, and a channel region 6 made of an n-type layer extending between the pair of regions.
And a source electrode 10 and a drain electrode 11 provided on the source region 4 and the drain region 5, and a gate electrode 12 provided on the channel region 6. The source electrode 10 and the drain electrode 11
Is composed of a film of AuGe / Ni / Au having a thickness of 4500Å, and is in ohmic contact with the source region 4 and the drain region 5, respectively. The gate electrode 12 is made of a metal film mainly containing Al and forms a Schottky barrier junction with the channel region 6.

On the other hand, in the capacitor section 3, a lower layer electrode 20 is provided on the main surface of the semi-insulating GaAs substrate 1. The lower layer electrode 20 is formed at the same time as the source / drain / gate electrodes 10, 11 and 12. Therefore, in this embodiment, the lower electrode 20 is composed of a film of AuGe / Ni / Au having a thickness of 4500Å.

Further, on the main surface of the semi-insulating GaAs substrate 1, CVD for electrically separating the source electrode 10, the drain electrode 11, the gate electrode 12 and the lower layer electrode 20 is performed.
An insulating film made of a PSG film (CVDPSG film) 15 is provided. The PSG film 15 has a thickness of about 4500Å. Further, a C film having a thickness of about 1000Å is formed so as to cover the PSG film 15, the source electrode 10, the drain electrode 11, the gate electrode 12 and the lower layer electrode 20.
A reaction blocking film 25 made of a VDPSG film is provided.

In the capacitance part 3, a thickness of 2000Å is formed on the reaction blocking film 25 in correspondence with the lower layer electrode 20.
Plasma nitride film (P-
A high dielectric film 26 made of a SiN film) is provided.
The upper layer electrode 22 of the MIM capacitor is formed on the high dielectric film 26. The upper layer electrode 22 is a capacitor insulating film 21.
A through hole is formed in the upper insulating film, that is, in the upper insulating film 31 of the capacitor insulating film on the high dielectric film 26.
It is formed by a wiring layer (metal film) formed by sputtering and patterning a metal mainly consisting of l, that is, a through hole contact portion. The insulating film 31 on the capacitive insulating film is formed by CVDPS provided on the high dielectric film 26.
Dummy insulating film 32 made of G film and this dummy insulating film 3
Main insulating film 33 made of CVDPSG film provided on
It consists of

The main insulating film 33 is formed of a CVDPSG film having a thickness of about 6000Å. The main insulating film 33 is also provided on the reaction blocking film 25 covering the source / drain / gate electrodes 10, 11, 12 and the like. In the FET section, a wiring layer 17 made of a metal mainly containing Al is provided on the main insulating film 33. The wiring layer 17 is formed by the main insulating film 33 and the reaction blocking film 25.
Are electrically connected to the source / drain / gate electrodes 10, 11 and 12, respectively, through through-hole contact portions made of a metal mainly containing Al, which are filled in the through-holes. The wiring layer 17 and the upper electrode 22 have a thickness of about 0.5 μm.

In this embodiment, this is one of the features of the present invention.
The through-holes are formed in the capacitor section 3 in the same process, that is, in the same process. Therefore, in this embodiment, the thickness of the insulating film forming the through hole in the FET part 2 and the thickness of the insulating film forming the through hole in the capacitor part 3 (capacitor insulating film upper insulating film 31) are made the same. In addition, all the respective insulating films are CVD
It is formed of a PSG film. The insulating film forming the through holes in the FET part 2 is formed by CVD with a thickness of about 1000Å.
Reaction blocking film 25 made of PSG film and this reaction blocking film 2
5 and a main insulating film 33 made of a CVDPSG film having a thickness of about 6000 Å. Further, the insulating film forming the through hole in the capacitor 3 is formed by CVD.
A dummy insulating film 32 made of a PSG film and a CVDPS having a thickness of about 6000Å provided on the dummy insulating film 32.
And a main insulating film 33 made of a G film. Therefore, the thickness of the dummy insulating film 32 is set to about 1000Å.

The surface of this semiconductor element is covered with a passivation film 35.

Next, a method of manufacturing such a semiconductor device will be described with reference to FIGS. First, as shown in FIG. 2, a compound semiconductor thin plate (wafer) 4
0 is prepared. This wafer 40 comprises a semi-insulating GaAs substrate 1. Further, the wafer 40 is subjected to a selective diffusion process in the FET portion 2 so as to have the n ⁺ type source region 4, the drain region 5 and the n type channel region 6.
Is formed.

Next, as shown in FIG. 3, the source electrode 10 and the drain electrode 11 are formed in the FET part 2 by the lift-off method, and the lower layer electrode 20 of the lower MIM capacitor is formed in the capacitor part 3. To be done. That is, the thickness of the main surface of the semi-insulating GaAs substrate 1 is 450
A CVDPSG film 15 of about 0Å is provided. afterwards,
A photoresist film (not shown) is selectively provided on the PSG film 15, and AuGe, Ni, and Au are sequentially deposited on the photoresist film. This AuGe
The / Ni / Au layer is about 4500Å thick. Then, the source electrode 10, the drain electrode 11, and the lower layer electrode 20 are formed by removing the photoresist film. Then, the photoresist film is removed, and a thickness of 5000 is formed by the same lift-off method.
The gate electrode 12 of about Å is formed. The gate electrode 12 is formed on the channel region 6 and
A Schottky junction is formed with the channel region 6.

Next, as shown in FIG. 4, a PSG having a thickness of about 1000Å is formed on the main surface of the wafer 40 by the CVD method.
A reaction blocking film (CVDPSG film) 25 made of a film is formed. Further, plasma CV is formed on the reaction blocking film 25.
Plasma nitride film (P-SiN film) by D method
High-dielectric film (P-SiN) with a thickness of about 2000Å
A film) 26 is formed. Further, this P-SiN film 26
A dummy insulating film 32 made of a CVDPSG film and having a thickness of about 1000Å is formed thereon. The dummy insulating film 32 is formed to have the same thickness as the reaction blocking film 25.

Next, as shown in FIG. 5, an etching mask (insulating film) not shown is selectively formed on the dummy insulating film 32, and the dummy insulating film exposed by using the etching mask as a mask. 32 and the high dielectric film 26 are etched, and the capacitance insulating film 21 including the reaction blocking film 25 and the high dielectric film 26 is formed on the insulating film lower layer electrode 20.

Next, as shown in FIG. 6, a main insulating film 33 made of a CVDPSG film and having a thickness of about 6000Å is formed on the main surface of the wafer 40. In this state, the FET section 2
Source / drain / gate electrodes 10, 11, 1 in
The thickness of the insulating film on 2 is CVDP with a thickness of about 1000Å
The sum of the thickness of the reaction blocking film 25 made of the SG film and the thickness of the main insulating film 33 made of the CVDPSG film having a thickness of about 6000Å, that is, about 7,000Å. Further, the insulating film on the capacitive insulating film 21 in the capacitive portion 3 (insulating film 31 on the capacitive insulating film)
Is about the sum of the thickness of the dummy insulating film 32 made of a CVDPSG film having a thickness of about 1000 Å and the main insulating film 33 having a thickness of about 6000 Å, that is, about 7,000 Å, and the thickness of the insulating film forming the through hole. Will be set to the same thickness in the FET portion 2 and the capacitance portion 3.

Next, as shown in FIG. 7, through holes 41, 42, 43 are formed in the FET section 2 by the conventional photolithography so as to correspond to the source / drain / gate electrodes 10, 11, 12. At the same time, in the capacitance section 3, a through hole 44 is formed in the capacitance insulating film 21.
Is formed. Through holes can be formed in the FET portion 2 and the capacitor portion 3 in the same process and by the same process because the thickness of the insulating film forming the through hole is the same as described above. As a result, the costly photolithography process can be performed by the FET section 2 and the capacitor section 3.
Since it is not necessary to separate them, it is possible to reduce the manufacturing cost. In the capacitor section 3, it is possible to obtain a predetermined MIM capacity by selecting the size of the through hole 44.

Next, as shown in FIG. 8, a metal having a thickness of about 1.0 μm, which is mainly composed of Al, is formed on the main surface of the wafer 40 by sputtering, and a desired pattern is formed. Gate electrodes 10, 11, 12
An upper electrode 22 is formed on the wiring layer 17 and the capacitive insulating film 21 connected to the. Thereafter, the passivation film 35 is formed on the main surface of the wafer 40, and the wafer 40 is finally divided into vertical and horizontal parts to form a rectangular semiconductor element as shown in FIG.

[0031]

(1) In the semiconductor device of the present invention,
A PSG film as a capacitance insulating film for the MIM capacitor, and this PSG film
A plasma nitride film having a dielectric constant about 1.8 times higher than that of the film is used, and the PSG film is 1000 Å
Since the plasma nitride film is as thin as about 2000Å, when the electrode area is about 10000 μm ² , the MIM capacity is about 1 PF compared to 0.5PF when the CVDPSG film with a capacity of 7,000Å is used as the capacity insulating film. .65
The effect of increasing the PF is obtained. As a result, a semiconductor element having a high MIM capacitance can be provided.

(2) According to the above (1), the semiconductor element of the present invention has an effect that the area of the capacitance portion can be reduced because the MIM capacitance is increased.

(3) According to the above (1), the semiconductor element of the present invention has an effect that the area of the capacitance portion can be reduced due to the increase in the MIM capacitance, and the semiconductor element can be miniaturized.

(4) In the manufacture of the semiconductor device of the present invention, the thickness of the insulating film on the capacitance insulating film is the same as the thickness of the insulating film on the source / drain / gate electrodes due to the use of the dummy insulating film. Therefore, when a through hole is formed in the insulating film on the source / drain / gate electrodes, the through hole can be formed in the insulating film on the capacitance insulating film at the same time, so that the through hole process can be performed only once, and the manufacturing cost can be reduced. It is possible to obtain the effect that the reduction of

(5) In manufacturing the semiconductor device of the present invention, the lower layer electrode of the MIM capacitor is formed at the same time when the source / drain electrodes of the MESFET are formed.
The formation of the upper layer electrode of the MIM capacitor at the same time when the wiring layer connected to the source / drain / gate electrodes of T is formed, and the formation of the through hole in the FET portion and the capacitance portion prior to the formation of the wiring layer and the upper layer electrode is performed once. By performing the process, it is possible to achieve the effect of reducing the manufacturing cost of the semiconductor element having the MIM capacitance and the MESFET.

(6) From the above (1) to (5), according to the present invention, there is a synergistic effect that a GaAs IC having a small capacitance portion area and a high capacitance MIM capacitance can be provided at low cost. To be

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The thickness of each insulating film is not limited to the values in the examples. Also, the material of the insulating film may be another material. further,
The lower electrode of the MIM capacitor is not limited to AuGe / Ni / Au.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of the capacity built-in type GaAs IC which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. INDUSTRIAL APPLICABILITY The present invention can be applied to manufacture of a semiconductor device having a structure in which at least MIM capacitors are provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a semiconductor element which constitutes a GaAs IC with a built-in capacitor according to the present invention.

FIG. 2 is a cross-sectional view showing a wafer into which impurities are selectively ion-implanted in the production of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing a wafer provided with a source electrode, a drain electrode, a gate electrode and a lower layer electrode in the manufacture of the semiconductor device of the present invention.

FIG. 4 is a cross-sectional view showing a wafer in which a reaction blocking film, a high dielectric film and a dummy PSG film are stacked on the main surface in the production of the semiconductor device of the present invention.

FIG. 5 is a view showing a dummy P in the manufacture of the semiconductor device of the present invention.
FIG. 6 is a cross-sectional view showing a wafer in which an SG film and a high dielectric film are selectively etched.

FIG. 6 is a cross-sectional view showing a wafer provided with a main insulating film on its main surface in the production of the semiconductor device of the present invention.

FIG. 7 is a cross-sectional view showing a wafer in which through holes are formed in the FET part and the capacitor part in the manufacture of the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view showing a wafer provided with a wiring layer and an upper layer electrode in the production of the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing a main part of a semiconductor element that constitutes a conventional GaAs IC with a built-in capacitor.

FIG. 10: GaAs with a built-in capacitor developed by the present inventors
It is sectional drawing which shows the principal part of the semiconductor element which comprises IC.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... FET part, 3 ... Capacitance part, 4 ... Source region, 5 ... Drain region, 6 ... Channel region, 10 ... Source electrode, 11 ... Drain electrode, 12 ...
Gate electrode, 15 ... PSG film, 16 ... PSG film, 17 ...
Wiring layer, 20 ... Lower layer electrode, 21 ... Capacitance insulating film, 22 ... Upper layer electrode, 25 ... Reaction blocking film (CVDPSG film), 26 ...
High dielectric film (P-SiN film), 31 ... Capacitor insulating film upper insulating film, 32 ... Dummy insulating film, 33 ... Main insulating film, 35 ... Passivation film, 40 ... Wafer, 41, 42, 43, 4
4 ... Through hole.

Claims (4)

[Claims] 1. A GaAs-MESFET and a MIM capacitor, wherein the source / drain electrode of the MESFET and the lower electrode of the MIM capacitor have the same composition by simultaneous formation, and the source / drain / gate electrode of the MESFET is formed. A wiring layer connected through a through-hole contact portion and an upper electrode of the MIM capacitor have the same composition by simultaneous formation, and the MIM capacitor is provided on the capacitor insulating film. A through hole is provided in the insulating film on the capacitor insulating film, and an upper layer electrode is formed by the wiring layer embedded in the through hole, and the thickness of the insulating film on the capacitor insulating film and the source / drain / gate electrode The semiconductor element is characterized in that the insulating films have the same thickness. 2. The capacitance insulating film is composed of a reaction blocking film and a high dielectric film having a high dielectric constant provided on the reaction blocking film, and the insulating film on the source / drain / gate electrodes is formed of the reaction blocking film. A dummy insulating film having a reaction blocking film and a main insulating film provided on the reaction blocking film, wherein the insulating film on the capacitive insulating film is provided on the capacitive insulating film and has the same thickness as the reaction blocking film. The semiconductor element according to claim 1, comprising a film and a main insulating film provided on the dummy insulating film. 3. The lower electrode of the MIM capacitor is AuGe /
Ni / Au, the upper electrode is made of Al, the reaction blocking film PSG film, the high dielectric film becomes a plasma nitride film, the dummy insulating film becomes a PSG film, and the main insulating film becomes PSG. The semiconductor element according to claim 2, wherein the semiconductor element is a film. 4. A source / drain electrode of the MESFET and a lower layer electrode of the MIMFET having a GaAs-MESFET and a MIM capacitance are formed at the same time, and a through-hole contact portion is formed in the source / drain / gate electrode of the MESFET. A method of manufacturing a semiconductor device, characterized in that a wiring layer connected via a metal layer and an upper electrode of the MIM capacitor are formed at the same time, and a lower reaction blocking film on the lower electrode and the source / drain / gate electrodes. And a step of providing a capacitive insulating film made of a high dielectric film as an upper layer and providing a dummy insulating film having the same thickness as the reaction blocking film on the capacitive insulating film, and selecting the high dielectric film and the dummy insulating film. Etching, a step of forming a main insulating film on the exposed reaction blocking film and the dummy insulating film, and Forming a through hole in the source / drain / gate electrode and the capacitance insulating film.