JPH06132276A - Method for forming semiconductor film - Google Patents
Method for forming semiconductor filmInfo
- Publication number
- JPH06132276A JPH06132276A JP4284350A JP28435092A JPH06132276A JP H06132276 A JPH06132276 A JP H06132276A JP 4284350 A JP4284350 A JP 4284350A JP 28435092 A JP28435092 A JP 28435092A JP H06132276 A JPH06132276 A JP H06132276A
- Authority
- JP
- Japan
- Prior art keywords
- sih
- film
- semiconductor film
- forming
- good
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
- H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の薄膜形成方
法に関するものであり、特に高アスペクト比の段差への
埋め込みと平坦化が可能な層間絶縁膜の製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a thin film of a semiconductor device, and more particularly to a method of manufacturing an interlayer insulating film which can be embedded in a step having a high aspect ratio and flattened.
【０００２】[0002]
【従来の技術】近年、デバイスの高集積化、微細化の進
展に伴い、配線の多層化が進んでいる。このような多層
配線構造においては、デバイス表面の高アスペクト比化
が進むため、層間絶縁膜の平坦性が悪化する。しかし、
デバイス作成の観点においてはより高い平坦度が要求さ
れている。2. Description of the Related Art In recent years, with the progress of high integration and miniaturization of devices, multi-layer wiring has been advanced. In such a multilayer wiring structure, since the aspect ratio of the device surface is increased, the flatness of the interlayer insulating film is deteriorated. But,
From the viewpoint of device fabrication, higher flatness is required.
【０００３】従来、絶縁膜形成技術として、シラン−酸
素系常圧ＣＶＤ法が用いられるが、この方法では、オー
バハングのできやすいノンコンフォーマルなステップカ
バレッジを示すため、高アスペクト比の形状には使用で
きず、平坦度も良好とは言えない。Conventionally, a silane-oxygen-based atmospheric pressure CVD method has been used as a technique for forming an insulating film. However, since this method shows non-conformal step coverage that easily causes overhang, it is used for a shape having a high aspect ratio. It cannot be done, and the flatness is not good.
【０００４】これを解決する方法として、無機もしくは
有機ＳＯＧによる塗布法、スパッタエッチ時のファセッ
ティング効果を利用したバイアスＥＣＲ法、犠牲膜を前
面プラズマエッチするエッチバック法等考えられている
が、絶縁膜の膜質、パターン依存性、工程の複雑さ、プ
ラズマによるダメージなどの問題がある。As a method for solving this, a coating method using an inorganic or organic SOG, a bias ECR method utilizing the faceting effect at the time of sputter etching, an etch-back method of etching the sacrificial film by front surface plasma are considered. There are problems such as film quality, pattern dependence, process complexity, and plasma damage.
【０００５】この平坦性の問題を解決するための手段と
して、特開昭６１−７７６９５号に示されているごとく
有機シラン（ＴＥＯＳ，テトラエトキシシラン）とオゾ
ンを反応させる方法が開発されてきた。この方法によれ
ば、表面反応主体のプロセスであるため反応種が基体表
面を十分マイグレーションし、結果として良好なステッ
プカバレッジを示す。As a means for solving this problem of flatness, a method of reacting an organic silane (TEOS, tetraethoxysilane) with ozone has been developed as shown in JP-A-61-77695. According to this method, since the process is mainly a surface reaction, the reactive species sufficiently migrate on the surface of the substrate, resulting in good step coverage.
【０００６】オゾンとＴＥＯＳを用いる反応はステップ
カバレッジは良いものの、成膜温度が４００℃程度の低
温反応のため膜がポーラスである、また、膜中にＳｉ−
ＯＨ結合が存在する等の欠点がある。これらが水分の吸
収や、ガスの発生による断線不良を引き起こす原因とな
る。また、この反応で形成する酸化膜の膜質はオゾン濃
度に影響を受けるが、肝心なオゾン濃度のコントロール
が困難なため、良好な膜質が得られないという問題もあ
る。Although the reaction using ozone and TEOS has good step coverage, the film is porous due to the low temperature reaction at a film forming temperature of about 400.degree.
There are drawbacks such as the presence of OH bonds. These may cause water absorption and defective disconnection due to gas generation. Further, although the film quality of the oxide film formed by this reaction is affected by the ozone concentration, there is also a problem that good film quality cannot be obtained because it is difficult to control the ozone concentration, which is essential.
【０００７】[0007]
【発明が解決しようとする課題】上述したごとく、多層
配線形成プロセスにおける絶縁膜の平坦化には多くの障
害が存在し、将来有望であると思われるオゾン−ＴＥＯ
ＳＣＶＤ法においても、膜質が良好でなく、オゾンの取
扱が困難である等の問題点が指摘されている。As described above, there are many obstacles to the flattening of the insulating film in the multi-layer wiring formation process, and ozone-TEO, which is considered to be promising in the future.
Also in the SCVD method, problems such as poor film quality and difficulty in handling ozone have been pointed out.
【０００８】本発明の目的は上記問題点を解決して、ア
スペクト比の高い表面にも、良好な平坦性を持ちかつ、
膜質が良い酸化膜を形成することが可能な半導体膜形成
方法を提供することにある。The object of the present invention is to solve the above-mentioned problems and to have good flatness even on a surface having a high aspect ratio, and
It is an object of the present invention to provide a semiconductor film forming method capable of forming an oxide film having good film quality.
【０００９】[0009]
【課題を解決するための手段】上記オゾン−ＴＥＯＳＣ
ＶＤ法の問題点は成膜温度が低い点とオゾン濃度のコン
トロールが難しい点である。これは原料にＴＥＯＳを使
用する以上回避不可能の問題と考えられる。なぜなら、
ＴＥＯＳ自体の分解温度が約７００℃と高く、オゾンの
ように反応性の高い化学種でないと低温で反応しないた
めである。低温化のためにプラズマを使用する方法も考
えられているが、プラズマダメージ、ステップカバレッ
ジが悪化する等の問題が発生する。Means for Solving the Problems Ozone-TEOSC
The problems of the VD method are that the film forming temperature is low and that the ozone concentration is difficult to control. This is considered to be an unavoidable problem when TEOS is used as the raw material. Because
This is because the decomposition temperature of TEOS itself is as high as about 700 ° C., and unless it is a highly reactive chemical species such as ozone, it will not react at a low temperature. Although a method of using plasma for lowering the temperature has been considered, problems such as plasma damage and deterioration of step coverage occur.
【００１０】このような問題を解決するために、本発明
者らが鋭意努力の結果、オゾンのような取扱の難しい化
学種を用いずに、酸素を使用し、やはり低温で酸化膜を
合成することのできる原料ガスを発見した。このガスを
ＴＥＯＳの代わりに用いることにより、アスペクト比の
高い表面にも、良好な平坦性を持ちかつ、膜質が良い酸
化膜を形成することが可能になった。As a result of diligent efforts by the present inventors to solve such a problem, oxygen is used without using a difficult-to-handle chemical species such as ozone, and an oxide film is also synthesized at a low temperature. We have discovered a raw material gas that can be used. By using this gas instead of TEOS, it becomes possible to form an oxide film having good flatness and good film quality even on a surface having a high aspect ratio.
【００１１】即ち、本発明は、 一般式 （Ｒ1 Ｒ2 Ｎ）n ＳｉＨ4-n （但し、上式において、Ｒ1 、Ｒ2 がＨ−，ＣＨ3 −，
Ｃ2 Ｈ5 −，Ｃ3 Ｈ7 −，Ｃ4 Ｈ9 −のいずれかであ
り、そのうち少なくとも一つがＨ−でない。ｎは１〜４
の整数である）で表わされる有機シラン化合物と酸素を
含んだ化合物を加えて原料ガスとして化学気相成長法に
より酸化珪素膜を形成することを特徴とする半導体膜形
成方法を提供するものである。That is, according to the present invention, the general formula (R 1 R 2 N) n SiH 4-n (where R 1 and R 2 are H-, CH 3- ,
C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. n is 1 to 4
The present invention provides a method for forming a semiconductor film, characterized in that a silicon oxide film is formed by a chemical vapor deposition method as a raw material gas by adding an organic silane compound represented by .
【００１２】ここで、有機シラン化合物を２種類以上組
み合わせて用いるのが好ましい。Here, it is preferable to use two or more kinds of organic silane compounds in combination.
【００１３】また、有機シラン化合物としては、トリス
ジメチルアミノシラン（（ＣＨ3 ） 2 Ｎ）3 ＳｉＨ、ビ
スジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）2 Ｓｉ
Ｈ2 、ジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）ＳｉＨ
3 、トリスジエチルアミノシラン（（Ｃ2 Ｈ5 ）2 Ｎ）
3 ＳｉＨ、ビスジエチルアミノシラン（（Ｃ2 Ｈ5 ）2
Ｎ）2 ＳｉＨ2 、ジエチルアミノシラン（（Ｃ2 Ｈ5 ）
2 Ｎ）ＳｉＨ3 、トリスジプロピルアミノシラン（（Ｃ
3 Ｈ7 ）2 Ｎ）3 ＳｉＨ、ビスジプロピルアミノシラン
（（Ｃ3 Ｈ7 ）2 Ｎ）2 ＳｉＨ2 、ジプロピルアミノシ
ラン（（Ｃ3 Ｈ7 ） 2 Ｎ）ＳｉＨ3 、トリスジイソブチ
ルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）3 ＳｉＨ、ビスジ
イソブチルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）2 ＳｉＨ
2 、ジイソブチルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）Ｓ
ｉＨ3 を用いるのが好適である。The organosilane compound is tris.
Dimethylaminosilane ((CH3) 2N)3SiH, Bi
Sdimethylaminosilane ((CH3)2N)2Si
H2, Dimethylaminosilane ((CH3)2N) SiH
3, Trisdiethylaminosilane ((C2HFive)2N)
3SiH, bisdiethylaminosilane ((C2HFive)2
N)2SiH2, Diethylaminosilane ((C2HFive)
2N) SiH3, Trisdipropylaminosilane ((C
3H7)2N)3SiH, bisdipropylaminosilane
((C3H7)2N)2SiH2, Dipropylaminosi
Run ((C3H7) 2N) SiH3, Tris diisobuty
Luminosilane ((CFourH9)2N)3SiH, bisuji
Isobutylaminosilane ((CFourH9)2N)2SiH
2, Diisobutylaminosilane ((CFourH9)2N) S
iH3Is preferably used.
【００１４】[0014]
【発明の作用】以下に本発明をさらに詳細に説明する。
本発明の半導体膜形成法によれば、本原料ガスと酸素を
含む分子を用いることにより、低温合成が可能で、しか
も、オゾンの場合と異なり反応が容易に制御できるた
め、良好な膜質を持つ酸化膜が形成できる。さらに、有
機材料の流動性からステップカバレッジも良好なものが
得られる。The present invention will be described in more detail below.
According to the method for forming a semiconductor film of the present invention, low temperature synthesis is possible by using the raw material gas and a molecule containing oxygen, and moreover, unlike the case of ozone, the reaction can be easily controlled, resulting in a good film quality. An oxide film can be formed. Further, due to the fluidity of the organic material, good step coverage can be obtained.
【００１５】本発明の半導体膜形成方法においては、原
料として有機シラン化合物と含酸素化合物を用い、これ
らを原料ガスとして化学気相成長法により酸化珪素膜を
形成する。In the semiconductor film forming method of the present invention, an organic silane compound and an oxygen-containing compound are used as raw materials, and a silicon oxide film is formed by a chemical vapor deposition method using these as raw material gases.
【００１６】本発明においては、有機シラン化合物とし
ては、一般式 （Ｒ1 Ｒ2 Ｎ）n ＳｉＨ4-n （但し、上式において、Ｒ1 、Ｒ2 がＨ−，ＣＨ3 −，
Ｃ2 Ｈ5 −，Ｃ3 Ｈ7 −，Ｃ4 Ｈ9 −のいずれかであ
り、そのうち少なくとも一つがＨ−でない。ｎは１〜４
の整数である）で表される有機化合物を少なくとも１種
用いる。In the present invention, the organic silane compound is represented by the general formula (R 1 R 2 N) n SiH 4-n (provided that in the above formula, R 1 and R 2 are H-, CH 3- ,
C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. n is 1 to 4
Is an integer) is used at least one kind.
【００１７】また、酸素含有化合物としては、酸素のほ
か、Ｎ2 Ｏなどの系に悪影響を与えない酸素含有化合物
であれば、何を用いてもよい。As the oxygen-containing compound, in addition to oxygen, any oxygen-containing compound which does not adversely affect the system such as N 2 O may be used.
【００１８】上記有機シラン化合物としては、有機シラ
ン化合物が、トリスジメチルアミノシラン（（ＣＨ3 ）
2 Ｎ）3 ＳｉＨ，ビスジメチルアミノシラン（（Ｃ
Ｈ3 ）2Ｎ）2 ＳｉＨ2 ，ジメチルアミノシラン（（Ｃ
Ｈ3 ）2 Ｎ）ＳｉＨ3 ，トリスジエチルアミノシラン
（（Ｃ2 Ｈ5 ）2 Ｎ）3 ＳｉＨ，ビスジエチルアミノシ
ラン（Ｃ2 Ｈ5 ）2 Ｎ）2 ＳｉＨ2 ，ジエチルアミノシ
ラン（（Ｃ2 Ｈ5 ）2 Ｎ）ＳｉＨ3 ，トリスジプロピル
アミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）3 ＳｉＨ，ビスジプ
ロピルアミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）2 ＳｉＨ2 ，
ジプロピルアミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）Ｓｉ
Ｈ3 ，トリスジイソブチルアミノシラン（（Ｃ4 Ｈ 9 ）
2 Ｎ）3 ＳｉＨ，ビスジイソブチルアミノシラン（（Ｃ
4 Ｈ9 ）2 Ｎ）2 ＳｉＨ2 ，ジイソブチルアミノシラン
（（Ｃ4 Ｈ9 ）2 Ｎ）ＳｉＨ3 を用いるのが好ましい。Examples of the above-mentioned organic silane compound include organic sila.
Compound is trisdimethylaminosilane ((CH3)
2N)3SiH, bisdimethylaminosilane ((C
H3)2N)2SiH2, Dimethylaminosilane ((C
H3)2N) SiH3, Trisdiethylaminosilane
((C2HFive)2N)3SiH, bisdiethylamino
Run (C2HFive)2N)2SiH2, Diethylamino
Run ((C2HFive)2N) SiH3, Trisdipropyl
Aminosilane ((C3H7)2N)3SiH, biszip
Ropylaminosilane ((C3H7)2N)2SiH2，
Dipropylaminosilane ((C3H7)2N) Si
H3, Trisdiisobutylaminosilane ((CFourH 9)
2N)3SiH, bisdiisobutylaminosilane ((C
FourH9)2N)2SiH2, Diisobutylaminosilane
((CFourH9)2N) SiH3Is preferably used.
【００１９】本発明の方法を実施する際にしては、図１
に模式的に示す装置を用いるのが好適である。同図にお
いて、１は原料ガス、２は基板、３はヒータ、４はオイ
ルバス、５は成膜室、６はノズル、７は排気ポンプ、８
はストップバルブ、９はガスラインである。In carrying out the method of the present invention, FIG.
It is suitable to use the apparatus schematically shown in FIG. In the figure, 1 is a source gas, 2 is a substrate, 3 is a heater, 4 is an oil bath, 5 is a film forming chamber, 6 is a nozzle, 7 is an exhaust pump, and 8 is.
Is a stop valve, and 9 is a gas line.
【００２０】[0020]
【実施例】以下、本発明を実施例に基づいて具体的に説
明する。EXAMPLES The present invention will be specifically described below based on examples.
【００２１】（実施例１）本実施例においては、図１に
示す装置を用いて成膜を行った。原料ガスとしてはトリ
スジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）3 ＳｉＨと
酸素を用いた。実験条件は基板としてステップカバレッ
ジ測定用のＡｌの配線パターン付のＳｉウエハと赤外吸
収スペクトルを測定するためのペアＳｉウエハを用い、
基板温度４００℃、動作圧力１００ｔｏｒｒ、原料ガス
はオイルバスにて７０℃に加熱され、窒素ガス１０ｓｃ
ｃｍによりバブリングされ成膜室に導入した。また、酸
素は５ｓｃｃｍ、バッファガスとして窒素を１００ｓｃ
ｃｍ流した。この条件で成膜した膜の赤外吸収スペクト
ルを図２に示す。この図より、この膜が良質なＳｉＯ 2
膜であることが判る。また、ステップカバレッジも良好
であった。なお、ここでは酸素を含む化合物として酸素
分子を用いたが、もちろん、酸素を含む化合物（例えば
Ｎ2 Ｏなど）であれば使用できる。(Embodiment 1) In this embodiment, FIG.
Film formation was performed using the apparatus shown. The source gas is tri
Sdimethylaminosilane ((CH3)2N)3With SiH
Oxygen was used. The experimental conditions are step coverage as a substrate.
Si wafer with Al wiring pattern for infrared measurement and infrared absorption
Using a pair of Si wafers for measuring the absorption spectrum,
Substrate temperature 400 ° C, operating pressure 100 torr, source gas
Is heated to 70 ° C in an oil bath, nitrogen gas 10sc
It was bubbled by cm and introduced into the film forming chamber. Also acid
Element is 5 sccm, nitrogen as buffer gas is 100 sc
cm flowed. Infrared absorption spectrum of film formed under these conditions
Is shown in FIG. This figure shows that this film is of good quality 2
It turns out to be a film. Also, good step coverage
Met. Note that here, oxygen is used as a compound containing oxygen.
Although a molecule was used, of course, a compound containing oxygen (for example,
N2O, etc.) can be used.
【００２２】（実施例２）本実施例においても、図１に
示す装置を用いて成膜を行った。原料ガスとしてはトリ
スジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）3 ＳｉＨと
ビスジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）2 ＳｉＨ
2 を１：１で混合したものと酸素を用いた。実験条件は
基板としてステップカバレッジ測定用のＡｌの配線パタ
ーン付きのＳｉウエハと赤外吸収スペクトルを測定する
ためのベアＳｉウエハを用い、動作圧力１００ｔｏｒ
ｒ、原料ガスはオイルバスにて７０℃に加熱され、窒素
ガス１０ｓｃｃｍによりバブリングされ成膜室に導入し
た。また、酸素は５ｓｃｃｍ、バッファガスとして窒素
を１００ｓｃｃｍ流した。この条件で成膜した膜の場
合、実施例１と同等の膜質を得るための基板温度は３５
０℃で良いことが判った。より一層の低温化が可能にな
ったといえる。(Embodiment 2) In this embodiment as well, film formation was performed using the apparatus shown in FIG. Raw material gases include trisdimethylaminosilane ((CH 3 ) 2 N) 3 SiH and bisdimethylaminosilane ((CH 3 ) 2 N) 2 SiH
A mixture of 2 in 1: 1 and oxygen was used. The experimental conditions were as follows: an Si wafer with Al wiring pattern for step coverage measurement and a bare Si wafer for measuring infrared absorption spectrum were used as substrates, and operating pressure was 100 torr.
r, the raw material gas was heated to 70 ° C. in an oil bath, bubbled with 10 sccm of nitrogen gas, and introduced into the film forming chamber. Further, oxygen was flowed at 5 sccm, and nitrogen was flowed at 100 sccm as a buffer gas. In the case of a film formed under these conditions, the substrate temperature for obtaining a film quality equivalent to that in Example 1 is 35.
It turns out that 0 ° C is good. It can be said that even lower temperatures have become possible.
【００２３】（比較例）本発明の効果を明確にするた
め、比較例として従来からステップカバレッジが良いと
されているオゾン−ＴＥＯＳによる酸化膜の合成を行っ
た。原料ガスとしてはテトラエトキシシラン（ＴＥＯ
Ｓ）とオゾン（Ｏ3 ）を用いた。実験条件は基板として
Ａｌの配線パターン付のＳｉと赤外吸収スペクトルを測
定するためのベアＳｉウエハを用い、基板温度４００
℃、動作圧力は１気圧、ＴＥＯＳはオイルバスにて６５
℃に加熱され、窒素ガス１００ｓｃｃｍによりバブリン
グされ成膜室に導入した。また、オゾンはオゾナイザー
（約４％がオゾンになる）により供給され、その時の酸
素の流量は７．５ＳＬＭとした。またバッファガスとし
て窒素を３５ＳＬＭ流した。この条件で成膜した膜の赤
外吸収スペクトルを図３に示す。この図より、この膜が
ＯＨ基を多量に含むＳｉＯ2 膜であり、膜として問題が
あることが判る。(Comparative Example) In order to clarify the effect of the present invention, an oxide film was synthesized by ozone-TEOS, which has been conventionally considered to have good step coverage, as a comparative example. As a raw material gas, tetraethoxysilane (TEO
S) and ozone (O 3 ) were used. The experimental conditions were as follows: Si with an Al wiring pattern was used as a substrate, and a bare Si wafer for measuring an infrared absorption spectrum was used.
℃, operating pressure 1 atm, TEOS 65 in the oil bath
It was heated to 0 ° C., bubbled with 100 sccm of nitrogen gas, and introduced into the film forming chamber. Further, ozone was supplied by an ozonizer (about 4% becomes ozone), and the flow rate of oxygen at that time was 7.5 SLM. Further, 35 SLM of nitrogen was used as a buffer gas. The infrared absorption spectrum of the film formed under these conditions is shown in FIG. From this figure, it can be seen that this film is a SiO 2 film containing a large amount of OH groups and has a problem as a film.
【００２４】[0024]
【発明の効果】本発明によれば、成膜温度は低温（４０
０℃以下）のままで、ステップカバレッジが良好で、平
坦性も高く、しかも膜質の良い酸化膜が形成できる。According to the present invention, the film forming temperature is low (40
(0 ° C. or less), an oxide film having good step coverage, high flatness, and good film quality can be formed.
【図１】 本発明の実施例で用いた成膜装置の概略図で
ある。FIG. 1 is a schematic view of a film forming apparatus used in an example of the present invention.
【図２】 本発明により形成した実施例１での膜の赤外
吸収スペクトル図である。FIG. 2 is an infrared absorption spectrum diagram of the film of Example 1 formed according to the present invention.
【図３】 従来の方法より形成した比較例での膜の赤外
吸収スペクトル図である。FIG. 3 is an infrared absorption spectrum diagram of a film of a comparative example formed by a conventional method.
１ 原料ガス ２ 基板 ３ ヒータ ４ オイルバス ５ 成膜室 ６ ノズル ７ 排気ポンプ ８ ストップバルブ ９ ガスライン 1 Raw Material Gas 2 Substrate 3 Heater 4 Oil Bath 5 Film Forming Chamber 6 Nozzle 7 Exhaust Pump 8 Stop Valve 9 Gas Line
Claims (3)
Ｃ2 Ｈ5 −，Ｃ3 Ｈ7 −，Ｃ4 Ｈ9 −のいずれかであ
り、そのうち少なくとも一つがＨ−でない。ｎは１〜４
の整数である）で表わされる有機シラン化合物と酸素を
含んだ化合物を加えて原料ガスとして化学気相成長法に
より酸化珪素膜を形成することを特徴とする半導体膜形
成方法。1. A compound represented by the general formula (R 1 R 2 N) n SiH 4-n (wherein R 1 and R 2 are H-, CH 3- ,
C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. n is 1 to 4
A compound containing oxygen and a compound containing oxygen is added to form a silicon oxide film by a chemical vapor deposition method as a raw material gas.
て用いる請求項１に記載の半導体膜形成方法。2. The method for forming a semiconductor film according to claim 1, wherein two or more kinds of organic silane compounds are used in combination.
Ｈ、 ビスジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）2 ＳｉＨ
2 、 ジメチルアミノシラン（（ＣＨ3 ）2 Ｎ）ＳｉＨ3 、 トリスジエチルアミノシラン（（Ｃ2 Ｈ5 ）2 Ｎ）3 Ｓ
ｉＨ、 ビスジエチルアミノシラン（（Ｃ2 Ｈ5 ）2 Ｎ）2 Ｓｉ
Ｈ2 、 ジエチルアミノシラン（（Ｃ2 Ｈ5 ）2 Ｎ）ＳｉＨ3 、 トリスジプロピルアミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）3
ＳｉＨ、 ビスジプロピルアミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）2 Ｓ
ｉＨ2 、 ジプロピルアミノシラン（（Ｃ3 Ｈ7 ）2 Ｎ）Ｓｉ
Ｈ3 、 トリスジイソブチルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）
3 ＳｉＨ、 ビスジイソブチルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）2
ＳｉＨ2 、 ジイソブチルアミノシラン（（Ｃ4 Ｈ9 ）2 Ｎ）ＳｉＨ
3である請求項１または２に記載の半導体膜形成方法。3. The organosilane compound is trisdimethylaminosilane ((CH 3 ) 2 N) 3 Si.
H, bisdimethylaminosilane ((CH 3 ) 2 N) 2 SiH
2 , dimethylaminosilane ((CH 3 ) 2 N) SiH 3 , trisdiethylaminosilane ((C 2 H 5 ) 2 N) 3 S
iH, bisdiethylaminosilane ((C 2 H 5 ) 2 N) 2 Si
H 2, diethylaminosilane ((C 2 H 5) 2 N) SiH 3, tris dipropylamino silane ((C 3 H 7) 2 N) 3
SiH, bis dipropylamino silane ((C 3 H 7) 2 N) 2 S
iH 2 , dipropylaminosilane ((C 3 H 7 ) 2 N) Si
H 3, tris diisobutyl aminosilane ((C 4 H 9) 2 N)
3 SiH, bisdiisobutylaminosilane ((C 4 H 9 ) 2 N) 2
SiH 2, diisobutyl aminosilane ((C 4 H 9) 2 N) SiH
The method for forming a semiconductor film according to claim 1, wherein the method is 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4284350A JPH06132276A (en) | 1992-10-22 | 1992-10-22 | Method for forming semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4284350A JPH06132276A (en) | 1992-10-22 | 1992-10-22 | Method for forming semiconductor film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06132276A true JPH06132276A (en) | 1994-05-13 |
Family
ID=17677450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4284350A Withdrawn JPH06132276A (en) | 1992-10-22 | 1992-10-22 | Method for forming semiconductor film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06132276A (en) |
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