JPH06132276A - Method for forming semiconductor film - Google Patents

Method for forming semiconductor film

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JPH06132276A
JPH06132276A JP28435092A JP28435092A JPH06132276A JP H06132276 A JPH06132276 A JP H06132276A JP 28435092 A JP28435092 A JP 28435092A JP 28435092 A JP28435092 A JP 28435092A JP H06132276 A JPH06132276 A JP H06132276A
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method
film
semiconductor film
good
silane
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JP28435092A
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Japanese (ja)
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Toru Mitomo
友 亨 三
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Kawasaki Steel Corp
川崎製鉄株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02219Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H01L21/02222Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

PURPOSE: To provide a method for forming a semiconductor film, wherein an oxide film having a good flatness and a good film quality can be formed even on a surface of a high aspect ratio.
CONSTITUTION: A method for forming a semiconductor film, wherein a silicon oxide film is formed by a chemical vapor growth method through using as its raw material gas the gas obtained by adding a compound containing oxygen to the organic silane compound specified by a general chemical formula (R1 R2N)nSiH4-no (in the formula, each of R1, R2 is one of H-, CH3-, C2H5-, C3H7-, C4H9-, and at least one of R1, R2 is not H-, and n is one of integers 1-4.).
COPYRIGHT: (C)1994,JPO&Japio

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置の薄膜形成方法に関するものであり、特に高アスペクト比の段差への埋め込みと平坦化が可能な層間絶縁膜の製造方法に関するものである。 The present invention relates is related to a thin film formation method of a semiconductor device, and in particular to a manufacturing method of embedding and flattening capable interlayer insulating film to the step of high aspect ratio.

【0002】 [0002]

【従来の技術】近年、デバイスの高集積化、微細化の進展に伴い、配線の多層化が進んでいる。 In recent years, high integration of devices, with the progress of miniaturization, multi-layered wiring is progressing. このような多層配線構造においては、デバイス表面の高アスペクト比化が進むため、層間絶縁膜の平坦性が悪化する。 In such a multilayer interconnection structure, the high aspect ratio of the device surface progresses, the flatness of the interlayer insulating film is deteriorated. しかし、 But,
デバイス作成の観点においてはより高い平坦度が要求されている。 Higher flatness is required in terms of device fabrication.

【0003】従来、絶縁膜形成技術として、シラン−酸素系常圧CVD法が用いられるが、この方法では、オーバハングのできやすいノンコンフォーマルなステップカバレッジを示すため、高アスペクト比の形状には使用できず、平坦度も良好とは言えない。 Conventionally, as the insulating film formation technique, silane - the oxygen-based atmospheric pressure CVD method is used, in this method, to indicate the possible easy non-conformal step coverage of the overhang, using the shape of the high aspect ratio can not be, it can not be said also flatness good.

【0004】これを解決する方法として、無機もしくは有機SOGによる塗布法、スパッタエッチ時のファセッティング効果を利用したバイアスECR法、犠牲膜を前面プラズマエッチするエッチバック法等考えられているが、絶縁膜の膜質、パターン依存性、工程の複雑さ、プラズマによるダメージなどの問題がある。 As a method to solve this problem, a coating method with an inorganic or organic SOG, a bias ECR method using faceting effect during sputter etching, but the sacrificial film is believed etch-back method or the like to the front plasma etch, insulating quality of the film, the pattern dependence, the complexity of the process, there are problems such as damage due to plasma.

【0005】この平坦性の問題を解決するための手段として、特開昭61−77695号に示されているごとく有機シラン(TEOS,テトラエトキシシラン)とオゾンを反応させる方法が開発されてきた。 [0005] As means for solving this flatness problem, the organic silane (TEOS, tetraethoxysilane) as shown in JP-A-61-77695 a method of reacting with ozone have been developed. この方法によれば、表面反応主体のプロセスであるため反応種が基体表面を十分マイグレーションし、結果として良好なステップカバレッジを示す。 According to this method, the reactive species for a process of surface reactions mainly take the substrate surface sufficiently migrate exhibits good step coverage as a result.

【0006】オゾンとTEOSを用いる反応はステップカバレッジは良いものの、成膜温度が400℃程度の低温反応のため膜がポーラスである、また、膜中にSi− [0006] The reaction using ozone and TEOS Although step coverage good film forming temperature is a membrane is porous for low temperature reactions of about 400 ° C., also in the film Si-
OH結合が存在する等の欠点がある。 There is a drawback such as the OH bond is present. これらが水分の吸収や、ガスの発生による断線不良を引き起こす原因となる。 Absorption and of moisture, becomes a cause of disconnection failure due to the generation of gas. また、この反応で形成する酸化膜の膜質はオゾン濃度に影響を受けるが、肝心なオゾン濃度のコントロールが困難なため、良好な膜質が得られないという問題もある。 Although the quality of the oxide film formed in this reaction is affected by ozone concentration is due to the difficulty is essential ozone concentration control, a problem that good film quality can not be obtained.

【0007】 [0007]

【発明が解決しようとする課題】上述したごとく、多層配線形成プロセスにおける絶縁膜の平坦化には多くの障害が存在し、将来有望であると思われるオゾン−TEO [SUMMARY OF THE INVENTION] As described above, there are many obstacles to the planarization of the insulating film in the multilayer wiring forming process, ozone -TEO that appear to be promising
SCVD法においても、膜質が良好でなく、オゾンの取扱が困難である等の問題点が指摘されている。 In the SCVD method, the film quality is not good, the problem of the like have been pointed out handling of ozone is difficult.

【0008】本発明の目的は上記問題点を解決して、アスペクト比の高い表面にも、良好な平坦性を持ちかつ、 An object of the present invention is to solve the above problems, in a high surface aspect ratio, it has good flatness and,
膜質が良い酸化膜を形成することが可能な半導体膜形成方法を提供することにある。 To provide a semiconductor film forming method capable of forming a film quality good oxide film.

【0009】 [0009]

【課題を解決するための手段】上記オゾン−TEOSC In order to achieve the above ozone -TEOSC
VD法の問題点は成膜温度が低い点とオゾン濃度のコントロールが難しい点である。 Problems of VD method is the point it is difficult to point the film forming temperature is low and the ozone concentration control of. これは原料にTEOSを使用する以上回避不可能の問題と考えられる。 This is believed to avoid possible problems or the use of TEOS as a raw material. なぜなら、 This is because,
TEOS自体の分解温度が約700℃と高く、オゾンのように反応性の高い化学種でないと低温で反応しないためである。 Decomposition temperature of the TEOS itself is as high as about 700 ° C., in order to not react at low temperatures unless a highly reactive species like ozone. 低温化のためにプラズマを使用する方法も考えられているが、プラズマダメージ、ステップカバレッジが悪化する等の問題が発生する。 Although has been considered a method of using plasma for low temperature, plasma damage, problems such as step coverage is deteriorated occurs.

【0010】このような問題を解決するために、本発明者らが鋭意努力の結果、オゾンのような取扱の難しい化学種を用いずに、酸素を使用し、やはり低温で酸化膜を合成することのできる原料ガスを発見した。 [0010] To solve such problems, the results of the present inventors have made extensive efforts, without using the difficult species handling, such as ozone, to use oxygen, also synthesize oxide film at a low temperature I found a raw material gas that can be. このガスをTEOSの代わりに用いることにより、アスペクト比の高い表面にも、良好な平坦性を持ちかつ、膜質が良い酸化膜を形成することが可能になった。 By using this gas instead of TEOS, also high surface aspect ratio, and has good flatness, it has become possible to form the film quality good oxide film.

【0011】即ち、本発明は、 一般式 (R 12 N) n SiH 4-n (但し、上式において、R 1 、R 2がH−,CH 3 −, [0011] Namely, the present invention has the general formula (R 1 R 2 N) n SiH 4-n ( where, in the above formula, R 1, R 2 is H-, CH 3 -,
25 −,C 37 −,C 49 −のいずれかであり、そのうち少なくとも一つがH−でない。 C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. nは1〜4 n is 1 to 4
の整数である)で表わされる有機シラン化合物と酸素を含んだ化合物を加えて原料ガスとして化学気相成長法により酸化珪素膜を形成することを特徴とする半導体膜形成方法を提供するものである。 There is provided a semiconductor film forming method, which comprises forming a integer which is) a silicon oxide film by a chemical vapor deposition method as a raw material gas by adding an organic silane compound and oxygen laden compound represented by .

【0012】ここで、有機シラン化合物を2種類以上組み合わせて用いるのが好ましい。 [0012] Here, it is preferable to use a combination of organic silane compound of two or more.

【0013】また、有機シラン化合物としては、トリスジメチルアミノシラン((CH 3 [0013] As the organic silane compound, tris (dimethylamino) silane ((CH 3) 2 N) 3 SiH、ビスジメチルアミノシラン((CH 32 N) 2 Si 2 N) 3 SiH, bis (dimethylamino) silane ((CH 3) 2 N) 2 Si
2 、ジメチルアミノシラン((CH 32 N)SiH H 2, dimethylamino silane ((CH 3) 2 N) SiH
3 、トリスジエチルアミノシラン((C 252 N) 3, tris diethylamino silane ((C 2 H 5) 2 N)
3 SiH、ビスジエチルアミノシラン((C 252 3 SiH, bis diethylamino silane ((C 2 H 5) 2
N) 2 SiH 2 、ジエチルアミノシラン((C 25 N) 2 SiH 2, diethylaminosilane ((C 2 H 5)
2 N)SiH 3 、トリスジプロピルアミノシラン((C 2 N) SiH 3, tris dipropylamino silane ((C
372 N) 3 SiH、ビスジプロピルアミノシラン((C 372 N) 2 SiH 2 、ジプロピルアミノシラン((C 37 3 H 7) 2 N) 3 SiH, bis dipropylamino silane ((C 3 H 7) 2 N) 2 SiH 2, dipropylamino silane ((C 3 H 7) 2 N)SiH 3 、トリスジイソブチルアミノシラン((C 492 N) 3 SiH、ビスジイソブチルアミノシラン((C 492 N) 2 SiH 2 N) SiH 3, tris diisobutyl aminosilane ((C 4 H 9) 2 N) 3 SiH, bis diisobutyl aminosilane ((C 4 H 9) 2 N) 2 SiH
2 、ジイソブチルアミノシラン((C 492 N)S 2, diisobutyl amino silane ((C 4 H 9) 2 N) S
iH 3を用いるのが好適である。 it is preferable to use iH 3.

【0014】 [0014]

【発明の作用】以下に本発明をさらに詳細に説明する。 Further illustrate the present invention in the following DETAILED DESCRIPTION OF THE INVENTION.
本発明の半導体膜形成法によれば、本原料ガスと酸素を含む分子を用いることにより、低温合成が可能で、しかも、オゾンの場合と異なり反応が容易に制御できるため、良好な膜質を持つ酸化膜が形成できる。 According to the semiconductor film forming method of the present invention, by using a molecule containing the raw material gas and oxygen, at a low temperature synthesis, moreover, since unlike the case of the ozone reaction can be easily controlled, with good quality oxide film can be formed. さらに、有機材料の流動性からステップカバレッジも良好なものが得られる。 Furthermore, those step coverage even better from flowable organic material is obtained.

【0015】本発明の半導体膜形成方法においては、原料として有機シラン化合物と含酸素化合物を用い、これらを原料ガスとして化学気相成長法により酸化珪素膜を形成する。 [0015] In the semiconductor film forming method of the present invention, the organic silane compound and oxygen-containing compound used as the raw material, it forms a silicon oxide film by chemical vapor deposition as a source gas.

【0016】本発明においては、有機シラン化合物としては、一般式 (R 12 N) n SiH 4-n (但し、上式において、R 1 、R 2がH−,CH 3 −, In the present invention, as the organic silane compound represented by the general formula (R 1 R 2 N) n SiH 4-n ( where, in the above formula, R 1, R 2 is H-, CH 3 -,
25 −,C 37 −,C 49 −のいずれかであり、そのうち少なくとも一つがH−でない。 C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. nは1〜4 n is 1 to 4
の整数である)で表される有機化合物を少なくとも1種用いる。 Used at least one kind of organic compound represented by the integer which is).

【0017】また、酸素含有化合物としては、酸素のほか、N 2 Oなどの系に悪影響を与えない酸素含有化合物であれば、何を用いてもよい。 [0017] The oxygen-containing compounds, addition of oxygen, if the system oxygen-containing compounds that do not adversely affect the like N 2 O, what may be used.

【0018】上記有機シラン化合物としては、有機シラン化合物が、トリスジメチルアミノシラン((CH 3 [0018] As the organic silane compound, an organic silane compound, trisdimethylaminosilane ((CH 3)
2 N) 3 SiH,ビスジメチルアミノシラン((C 2 N) 3 SiH, bis (dimethylamino) silane ((C
32 N) 2 SiH 2 ,ジメチルアミノシラン((C H 3) 2 N) 2 SiH 2, dimethylamino silane ((C
32 N)SiH 3 ,トリスジエチルアミノシラン((C 252 N) 3 SiH,ビスジエチルアミノシラン(C 252 N) 2 SiH 2 ,ジエチルアミノシラン((C 252 N)SiH 3 ,トリスジプロピルアミノシラン((C 372 N) 3 SiH,ビスジプロピルアミノシラン((C 372 N) 2 SiH 2 H 3) 2 N) SiH 3 , tris diethylamino silane ((C 2 H 5) 2 N) 3 SiH, bis diethylamino silane (C 2 H 5) 2 N ) 2 SiH 2, diethylaminosilane ((C 2 H 5) 2 N) SiH 3, tris dipropylamino silane ((C 3 H 7) 2 N) 3 SiH, bis dipropylamino silane ((C 3 H 7) 2 N) 2 SiH 2,
ジプロピルアミノシラン((C 372 N)Si Dipropylamino silane ((C 3 H 7) 2 N) Si
3 ,トリスジイソブチルアミノシラン((C 4 H 3, tris diisobutyl aminosilane ((C 4 H 9 9)
2 N) 3 SiH,ビスジイソブチルアミノシラン((C 2 N) 3 SiH, bis diisobutyl aminosilane ((C
492 N) 2 SiH 2 ,ジイソブチルアミノシラン((C 492 N)SiH 3を用いるのが好ましい。 4 H 9) 2 N) 2 SiH 2, diisobutyl aminosilane ((C 4 H 9) 2 N) preferably used SiH 3.

【0019】本発明の方法を実施する際にしては、図1 [0019] In the carrying out the process of the present invention, FIG. 1
に模式的に示す装置を用いるのが好適である。 It is preferable to use the apparatus shown schematically in. 同図において、1は原料ガス、2は基板、3はヒータ、4はオイルバス、5は成膜室、6はノズル、7は排気ポンプ、8 In the figure, 1 is the raw material gas, 2 substrate, 3 is a heater, the oil bath 4, 5 film forming chamber, the nozzle 6, 7 an exhaust pump, 8
はストップバルブ、9はガスラインである。 Stop valve 9 is a gas line.

【0020】 [0020]

【実施例】以下、本発明を実施例に基づいて具体的に説明する。 EXAMPLES The following specifically described the present invention based on examples.

【0021】(実施例1)本実施例においては、図1に示す装置を用いて成膜を行った。 [0021] Example 1 In this example, a film was formed using the apparatus shown in FIG. 原料ガスとしてはトリスジメチルアミノシラン((CH 32 N) 3 SiHと酸素を用いた。 As the raw material gas trisdimethylaminosilane with ((CH 3) 2 N) 3 SiH and oxygen. 実験条件は基板としてステップカバレッジ測定用のAlの配線パターン付のSiウエハと赤外吸収スペクトルを測定するためのペアSiウエハを用い、 The experimental conditions used pair Si wafer for measuring the Si wafer and the infrared absorption spectrum dated wiring pattern Al for step coverage measurement as the substrate,
基板温度400℃、動作圧力100torr、原料ガスはオイルバスにて70℃に加熱され、窒素ガス10sc A substrate temperature of 400 ° C., the operating pressure 100 torr, the raw material gas is heated to 70 ° C. in an oil bath, a nitrogen gas 10sc
cmによりバブリングされ成膜室に導入した。 It was introduced into the film forming is bubbling chamber by a cm. また、酸素は5sccm、バッファガスとして窒素を100sc The oxygen is 5 sccm, the nitrogen as a buffer gas 100sc
cm流した。 Shed cm. この条件で成膜した膜の赤外吸収スペクトルを図2に示す。 An infrared absorption spectrum of the film formed in this condition in Figure 2. この図より、この膜が良質なSiO From this figure, this film is good-quality SiO 2 2
膜であることが判る。 It can be seen that a membrane. また、ステップカバレッジも良好であった。 Also, step coverage was good. なお、ここでは酸素を含む化合物として酸素分子を用いたが、もちろん、酸素を含む化合物(例えばN 2 Oなど)であれば使用できる。 Note that, although using molecular oxygen as a compound containing oxygen, of course, be used as long as it is a compound containing oxygen (for example, N 2 O, etc.).

【0022】(実施例2)本実施例においても、図1に示す装置を用いて成膜を行った。 [0022] Also in Example 2 In this example, a film was formed using the apparatus shown in FIG. 原料ガスとしてはトリスジメチルアミノシラン((CH 32 N) 3 SiHとビスジメチルアミノシラン((CH 32 N) 2 SiH As the raw material gas trisdimethylaminosilane ((CH 3) 2 N) 3 SiH and bis (dimethylamino) silane ((CH 3) 2 N) 2 SiH
2を1:1で混合したものと酸素を用いた。 2 1: the oxygen was used as a mixture with 1. 実験条件は基板としてステップカバレッジ測定用のAlの配線パターン付きのSiウエハと赤外吸収スペクトルを測定するためのベアSiウエハを用い、動作圧力100tor The experimental conditions used bare Si wafer for measuring the Si wafer and an infrared absorption spectrum with a wiring pattern of Al for step coverage measurement as the substrate, the operating pressure 100tor
r、原料ガスはオイルバスにて70℃に加熱され、窒素ガス10sccmによりバブリングされ成膜室に導入した。 r, the raw material gas is heated to 70 ° C. in an oil bath, was introduced into the film forming chamber is bubbled with nitrogen gas 10 sccm. また、酸素は5sccm、バッファガスとして窒素を100sccm流した。 Further, oxygen was flushed 100sccm nitrogen 5 sccm, as a buffer gas. この条件で成膜した膜の場合、実施例1と同等の膜質を得るための基板温度は35 For the film formed in this condition, the substrate temperature to obtain the same quality as in Example 1 35
0℃で良いことが判った。 It may be the 0 ℃ was found. より一層の低温化が可能になったといえる。 It can be said that more has become possible to further lower temperature.

【0023】(比較例)本発明の効果を明確にするため、比較例として従来からステップカバレッジが良いとされているオゾン−TEOSによる酸化膜の合成を行った。 [0023] In order to clarify the effects of (Comparative Example) The present invention, was synthesized oxide film by ozone -TEOS that conventionally step coverage is good as a comparative example. 原料ガスとしてはテトラエトキシシラン(TEO As the raw material gas of tetraethoxysilane (TEO
S)とオゾン(O 3 )を用いた。 S) and using ozone (O 3). 実験条件は基板としてAlの配線パターン付のSiと赤外吸収スペクトルを測定するためのベアSiウエハを用い、基板温度400 The experimental conditions used bare Si wafer for measuring the Si and infrared absorption spectrum dated wiring pattern Al as a substrate, a substrate temperature of 400
℃、動作圧力は1気圧、TEOSはオイルバスにて65 ° C., the operating pressure is 1 atm, TEOS is in an oil bath 65
℃に加熱され、窒素ガス100sccmによりバブリングされ成膜室に導入した。 ℃ heated to, and introduced into the film forming chamber is bubbled by nitrogen gas 100 sccm. また、オゾンはオゾナイザー(約4%がオゾンになる)により供給され、その時の酸素の流量は7.5SLMとした。 Also, ozone is supplied by the ozonizer (about 4% is ozone), oxygen flow rate at that time was 7.5 slm. またバッファガスとして窒素を35SLM流した。 The nitrogen flushed 35SLM as a buffer gas. この条件で成膜した膜の赤外吸収スペクトルを図3に示す。 An infrared absorption spectrum of the film formed in this condition in Fig. この図より、この膜がOH基を多量に含むSiO 2膜であり、膜として問題があることが判る。 From this figure, this film is a SiO 2 film containing a large amount of OH group, it can be seen that there is a problem as a membrane.

【0024】 [0024]

【発明の効果】本発明によれば、成膜温度は低温(40 According to the present invention, the deposition temperature is low (40
0℃以下)のままで、ステップカバレッジが良好で、平坦性も高く、しかも膜質の良い酸化膜が形成できる。 It remains 0 ℃ below), has good step coverage, higher flatness, yet good oxide film quality can be formed.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の実施例で用いた成膜装置の概略図である。 1 is a schematic diagram of a film forming apparatus used in Examples of the present invention.

【図2】 本発明により形成した実施例1での膜の赤外吸収スペクトル図である。 Figure 2 is an infrared absorption spectrum view of the membrane of Example 1 formed by the present invention.

【図3】 従来の方法より形成した比較例での膜の赤外吸収スペクトル図である。 3 is an infrared absorption spectrum of the film in the comparative example of forming the conventional manner.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 原料ガス 2 基板 3 ヒータ 4 オイルバス 5 成膜室 6 ノズル 7 排気ポンプ 8 ストップバルブ 9 ガスライン 1 raw gas 2 substrate 3 heater 4 oil bath 5 deposition chamber 6 nozzle 7 exhaust pump 8 stop valve 9 the gas line

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】一般式 (R 12 N) n SiH 4-n (但し、上式において、R 1 、R 2がH−,CH 3 −, 1. A general formula (R 1 R 2 N) n SiH 4-n ( where, in the above formula, R 1, R 2 is H-, CH 3 -,
    25 −,C 37 −,C 49 −のいずれかであり、そのうち少なくとも一つがH−でない。 C 2 H 5 -, C 3 H 7 -, C 4 H 9 - are either, at least one of them is not H-. nは1〜4 n is 1 to 4
    の整数である)で表わされる有機シラン化合物と酸素を含んだ化合物を加えて原料ガスとして化学気相成長法により酸化珪素膜を形成することを特徴とする半導体膜形成方法。 The semiconductor film forming method characterized in that a silicon oxide film is formed by the integer which is) chemical vapor deposition as a raw material gas by adding an organic silane compound and oxygen laden compound represented by.
  2. 【請求項2】有機シラン化合物を2種類以上組み合わせて用いる請求項1に記載の半導体膜形成方法。 2. A semiconductor film forming method according to claim 1 for use in combination an organic silane compound of two or more.
  3. 【請求項3】有機シラン化合物が、 トリスジメチルアミノシラン((CH 32 N) 3 Si Wherein the organic silane compound is tris (dimethylamino) silane ((CH 3) 2 N) 3 Si
    H、 ビスジメチルアミノシラン((CH 32 N) 2 SiH H, bis (dimethylamino) silane ((CH 3) 2 N) 2 SiH
    2 、 ジメチルアミノシラン((CH 32 N)SiH 3 、 トリスジエチルアミノシラン((C 252 N) 3 2, dimethylamino silane ((CH 3) 2 N) SiH 3, tris diethylamino silane ((C 2 H 5) 2 N) 3 S
    iH、 ビスジエチルアミノシラン((C 252 N) 2 Si iH, bis diethylamino silane ((C 2 H 5) 2 N) 2 Si
    2 、 ジエチルアミノシラン((C 252 N)SiH 3 、 トリスジプロピルアミノシラン((C 372 N) 3 H 2, diethylaminosilane ((C 2 H 5) 2 N) SiH 3, tris dipropylamino silane ((C 3 H 7) 2 N) 3
    SiH、 ビスジプロピルアミノシラン((C 372 N) 2 SiH, bis dipropylamino silane ((C 3 H 7) 2 N) 2 S
    iH 2 、 ジプロピルアミノシラン((C 372 N)Si iH 2, dipropylamino silane ((C 3 H 7) 2 N) Si
    3 、 トリスジイソブチルアミノシラン((C 492 N) H 3, tris diisobutyl aminosilane ((C 4 H 9) 2 N)
    3 SiH、 ビスジイソブチルアミノシラン((C 492 N) 2 3 SiH, bis diisobutyl aminosilane ((C 4 H 9) 2 N) 2
    SiH 2 、 ジイソブチルアミノシラン((C 492 N)SiH SiH 2, diisobutyl aminosilane ((C 4 H 9) 2 N) SiH
    3である請求項1または2に記載の半導体膜形成方法。 3 a semiconductor film forming method according to claim 1 or 2.
JP28435092A 1992-10-22 1992-10-22 Method for forming semiconductor film Withdrawn JPH06132276A (en)

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