JPH06131313A - System for dividing/allocating data - Google Patents

Abstract

PURPOSE:To provide the system for dividing/allocating instructions and data which can easily describe a program for parallel execution, can reduce data transfer time at the time of referring to data and can shorten execution time in parallel execution. CONSTITUTION:In the case of parallelly executing one source program 1 while plural processors 2a, 2b and 2c take partial charge of it, one piece of arrangement data in the program 1 are divided and allocated to the memories of the plural processors 2a, 2b and 2c. Thus, since the arrangement data are allocated, the program for parallel execution can be easily described, and the data transfer time in the case of referring to data can be reduced. Further, since the division of the instruction part into the respective processors 2a, 2b and 2c is made coincident with the division of the arrangement data, the respective processors can perform parallel execution without any problem even when the number of times of repetition is made different for the arrangement data and the instructions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data division / allocation system for parallel execution of a program by a plurality of processors in a computer system composed of a plurality of processors. The present invention relates to a data division / allocation method suitable for application to a distributed memory type multi-processor computer system having the above memory.

[0002]

2. Description of the Related Art As a computer system including a plurality of processors, the systems shown in FIGS. 6 (a) and 6 (b) have been conventionally known. 11A and 11B in FIG.
a, 11b ... Are processors, 12, 12a, 12b ... Are memories, and 13 is a network. FIG. 1A shows a shared memory multiprocessor system,
The processors 11a and 11b share the memory 12, and the memory 12 can be directly accessed from the instructions of the processors 11a and 11b.

FIG. 1B shows a distributed memory type multi-processor system.
b have their own memories 12a, 12b, ..., and communication between the processors is performed via the network 13. By the way, in the above-described multi-processor system, when a program is executed in parallel by a plurality of processors, the following two methods have been conventionally used. A method of converting one source program instructed to the parallel-executable part and executing the source program in parallel.

FIG. 7A shows the source program P1 shown in FIG. 7C as the processors 11a and 11b and the memory 12.
Memory sharing multi-processor
It is the figure which showed the case where it performs in a system. The source program P1 in the figure shows an example in which the data is read from the file to the array A and the DO loop is executed in parallel by the two processors, and the data is read from the file to the array A by "READ A". "PARALLEL
DO I = 1,1000 ... ”and“ = A (I) ”execute parallel execution.

The source program P1 is executed in a shared memory multiprocessor system as shown in FIG. After the array area is secured in the memory 12 by the processor 11a, "READ
"A" is executed to read the data from the file into the area secured in the memory 12. Then, the processor 11a,
Parallel execution is started by 11b. That is, the DO loop of 1 to 1000 is divided into two, the processor 11a executes the DO loop of 1 to 500, and the processor 11b executes the DO loop of 501 to 1000 in parallel. Processor 11
It is read from the memory 12 by a and 11b.

FIG. 2B shows the above source program P1.
To the processor 11a having the memory 12a and the memory 12
FIG. 10 is a diagram showing a case of execution by a distributed memory multi-processor system including a processor 11b having b. In FIG. 2B, the processor 11
After securing the array area in the memory 12a by a,
"READ A" is executed to read the data from the file into the area secured in the memory 12a.

Then, the DO loop of 1 to 1000 is divided into two, and the DO of 1 to 500 is divided by the processor 11a and the processor 11b as shown in FIG.
The loop, DO loops of 501 to 1000 are executed in parallel. Further, in this case, since the array data is stored in the memory 12a, the data is stored in the processors 11a, 1 each time the processor 11b executes the instruction of the DO loop.
It is transferred between 1b. This causes transfer overhead and increases execution time. A method of writing a source program for each processor, converting each to an executable program, and executing them in parallel.

FIG. 8A is a diagram for each processor described by a distributed memory multiprocessor system including a processor 11a having a memory 12a and a processor 11b having a memory 12b.
It is a figure which shows the case where the source program P2a and the source program P2b shown in (b) are executed. Source·
The programs P2a and p2b read the data into the arrays A and B, respectively, from the file, and the source program P
As in the case of No. 1, an example in which a DO loop is executed in parallel by two processors is shown.

The source program P2a is the processor 1
The source program P2b is a program written for 1a, and the source program P2b is a program written for the processor 11b. The source programs P2a and P2b are executed in a distributed memory multiprocessor system as shown in FIG.

After the array areas are secured in the memories 12a and 12b by the processors 11a and 11b, the processor 11a executes "READ A" to read the array data for 500 elements and store the array data in the array A. Then, the event of "first half completed" is notified. The processor 11b continues to wait for the occurrence of the "first half completed" event, and after satisfying it, "READ
"B" is executed to read the array data for 500 elements and store it in array B.

As described above, 1 to 5 are stored in the memory 12a.
The DO loop is executed in parallel by the processor 11a when the data up to 00 is stored, and by the processor 11b when the data of 501 to 1000 is stored in the memory 12b.
It is read from the memories 12a and 12b by a and 11b.

[0012]

By the way, the above method is based on a uniform shared memory system (shared memory system in which access speeds to the memories from the processors are not so different from each other as shown in FIG. 6A). 6) is suitable for application to the multiprocessor system of FIG.
In the distributed memory shown in (b), data transfer with another processor occurs at the time of referring to data, so that there is a drawback that the execution time increases.

Further, in the above method, since the source program must be written for each processor, for example, because of a portion such as a READ statement that cannot be executed in parallel, synchronous control by a POST or WAIT statement, etc. There is a drawback in that it is difficult to describe the program because it is necessary to consider in the program for the parts that cannot be executed in parallel, such as considering in the program.

The present invention has been made in view of the above-mentioned drawbacks of the prior art. In a distributed multi-processor system including a plurality of processors, instruction division for using a plurality of processors and data are used. Data can be shared by a single partitioning instruction for allocating data to the unique memory of each processor, thereby making it possible to easily write a parallel execution program, and at the time of data reference and storage. An object of the present invention is to provide a data division / allocation method that can reduce the data transfer time and the execution time in parallel execution.

[0015]

FIG. 1 shows the principle of the present invention. In order to solve the above problems, the invention of claim 1 of the present invention is, as shown in FIG.
In a shared memory multi-processor computer system in which the access speed from the processor to the memory differs depending on the distance between the processor and the memory, a plurality of processors 2a, 2 of the multi-processor computer system 2
When one source program 1 is shared by b and 2c and executed in parallel, one source program 1 divides one array data in the source program 1 into a plurality of arrays, and a plurality of processors 2a, It is arranged to be allocated to the memories 2b and 2c.

According to a second aspect of the present invention, in a multi-processor computer system of a distributed memory system or a shared memory system in which the access speed from the processor to the memory differs depending on the distance between the processors, When a plurality of processors 2a, 2b, 2c of the processor computer system 2 share one source program 1 for parallel execution, the instruction part in the source program 1 is divided into the processors 2a, 2b, 2c. The arrangement of the array data into the memories of the processors 2a, 2b, 2c is made to coincide with each other.

[0017]

According to the first aspect of the present invention, the multi
A plurality of processors 2a of the processor computer system 2,
When one source program 1 is shared by 2b and 2c and executed in parallel, from one source program 1,
Since one array data in the source program 1 is divided into a plurality of arrays and allocated to the memories of the plurality of processors 2a, 2b, 2c, the parallel execution program can be easily described. It is possible to reduce the data transfer time at the time of referring to the data and the execution time in parallel execution.

According to a second aspect of the present invention, a plurality of processors 2 of the multi-processor computer system 2 are provided.
When one source program 1 is shared by a, 2b, and 2c and executed in parallel, the instruction part in the program 1 is divided into the processors 2a, 2b, and 2c, and the processor 2a, 2b, and 2c of the array data is divided. Since the division into memory is made to match, even if the number of array data and the number of repetitions of instructions are different, parallel execution can be performed without problems in each processor, and the same as in the invention of claim 1. The parallel execution program can be easily written, the data transfer time at the time of data reference can be reduced, and the execution time in parallel execution can be shortened.

[0019]

FIG. 2 is a diagram showing an example of a source program according to the present invention and an operation when the program is executed by the distributed memory multiprocessor system shown in FIG. 6B. In the figure, 11a, 1
1b is a processor, and 12a and 12b are memories unique to the processors 11a and 11b, respectively. Also, P3
Is an example of a source program executed by the system shown in the figure, and an example in which data is read from the file into the array A and the DO loop is executed in parallel by the two processors is shown as in the case of the source program P1. It is a thing. The source program P3 is converted into an executable program which is compiled by a compiler described later and executed by the processors 11a and 11b.

The execution of the program converted into the execution format in the processors 11a and 11b is the same as in the case of FIG.
"AD A" reads the data from the file into array A,
Data is transferred to the processor 11b to execute parallel execution. In the source program P3, "PARTITION P =
(2,1: 1000, BAND) "is division information for dividing the instruction part and the data part and assigning them to multiple processors. In the above description," 2 "in parentheses indicates how many instructions or data Number of processors that indicates whether to allocate to the processor, "1:
“1000” indicates an index section which is a reference for dividing an instruction or data, and “BAND” indicates an index dividing method.

Also, "PARALLEL DO ..." describes the start of parallel execution, as in the case of the source program P1 in FIG. Here, the index section,
A method of dividing the index will be described. Index section The index section serves as a reference for dividing instructions or data as described above. In the source program P3 shown in FIG. 2, the array declaration is "REAL A (1000)" and the repetition in the DO loop is also performed. The number of times is “I = 1,1000”, and these coincide with the index section “1: 1000”. Therefore, the upper and lower limits of the array declaration, or DO
There is no problem even if the instruction and data are divided according to the number of repetitions in the loop.

However, when the number of repetitions in the array declaration or the DO loop does not match, if the instruction or data is divided by either the upper or lower limit value of the array declaration or the number of repetitions in the DO loop, it matches the division value by the other. The problem of not doing occurs. For example, in the following example, REAL A (400) ... DO I = 3,398 ... = A (I) END DO is A (400) in the array declaration, but the number of iterations in the DO loop is I = 3,398. And both ends of the array declaration are excluded from the calculation by "2". In the above example, when the array A is divided into four, the array A becomes A (1:
100) A (101: 200) A (201: 30)
0) It is divided into A (301: 400). Also, DO
When the number of iterations is divided into four by I = 3,398 of the loop, I = 3,101 I = 102,200 I = 2
01,299 I = 300,398 divided into 101
At 300, the two do not match.

On the other hand, when the division is performed using the index section of the division information as a reference, the number of repetitions in the DO loop is I = 3,100 I = 101,200 I = 20
1,300 I = 301,398, which corresponds to the division of data. As described above, the instruction or array is divided based on the index section of the division information, not the opening and closing values of the repetitions or the upper and lower limit values of the subscripts of the array declaration. Even when the value is out of the calculation target, the instruction and array division can be matched even in the reduced section. Index Dividing Method FIG. 3 is a diagram showing an index dividing method. In the figure, the vertical axis represents the processor number and the horizontal axis represents the index value. As shown in the figure, the index can be divided by various methods such as "equal division", "circular division", and "triangular division".

In the above division method, for example, the triangular division is adopted when the processing amount becomes larger toward the rear, such as when the DO loop is a double loop as described below, so that the processing amount becomes uniform. Can be converted. DO I = 1,1000 DO J = 1, I ... FIG. 4 is a diagram showing an example of the configuration of a compiler for compiling a source program for parallel execution, in which 21 is a parallel Source program to be executed, 22 is a compiler for compiling the source program, 23 is a source program analysis unit for analyzing the source program, and 24 is an optimum for automatically finding a parallelizable part from the source program. A code generation unit for generating an executable parallel object program from the analyzed source program, a syntax 26 for performing syntax analysis in the source program analysis unit, and a created parallel object program 27. It is a program.

The optimizing unit 24 in FIG. 4 is provided as needed. As shown in the example of FIG. 2, when the parallelizing part is described in the source program, unnecessary. In the figure, when the source program 21 is given to the compiler 22, the source program 21 is first analyzed by the source program analysis unit 23.

When the source program analysis unit 23 performs syntax analysis, in addition to the grammar of the syntax 26 used when analyzing a normal source program, a parallel program for interpreting a parallel execution source program is used. Syntax 26
Parsing is performed with reference to the grammar of a. Figure 5 is Fo
It is a figure which shows an example of the syntax which employ | adopted the division description for parallel execution to the source program of rtran. The syntax shown in the figure is the same as the source program P3 of FIG.
An example described by Ckus-Naur Form is shown (for BNF, for example, AV Jose 2
Please refer to the compiler-related literature such as the famous book "Compiler I-Principles, Techniques, Tools" Science Co., Ltd. 1990/10/10 first edition).

The output of the source program analysis section 23 is
It is given to the optimization unit 24 as needed. The optimizing unit 24 is not necessary when the parallelized portion is described in the source program, as described above. The optimizing unit 24 selects a parallelizable part in a given source program. As a part that can be parallelized in the source program, a part such as a DO loop in which repeated operations are performed is selected. In selecting the part, for example, in the case of a multiple DO loop, the DO loops are exchanged. Consider the execution performance by dividing the outer loop as much as possible to reduce the number of parallel processing controls and reduce the overhead.

As described above, the program analyzed by the source program analysis unit, or
The program for which the parallelization target loop is selected by the optimization unit 24 is given to the code generation unit 25. In the code generator 25, a final object program is generated from the above program.

In the code generator 25, the object
When generating a program, for the instruction, the start value and end value of the repeated operation are compared with the index value of the division information to determine the processor to execute,
For data, the lower and upper bounds of the subscripts in the array declaration are compared with the index value of the partition information to determine the processor to which the data is assigned.

In the case of the example shown in FIG. 5, "locate-sta
For “tement”, the upper and lower limit values in the declaration of “array-name” are divided into a plurality of arrays by comparing with the index range of the division information, and embedded in the execution format program for each processor. In addition, "parallel-do-stat
For "ement", "start-value" and "end-va"
"lue" against the index range of the partition information, and a new "start-value" for each processor
, "End-value" repetition is incorporated into the executable program.

With the above processing, the compiler 22
Generates and outputs a parallel object program 27 for parallel execution, and the parallel object programs 27a to 27c are loaded into each processor and executed. Actually, the parallel object programs 27a to 27c for each processor are output as a series of programs and loaded into each processor, and when each processor executes, each processor selects and executes the program part corresponding to its own processor. .

In the above embodiments, an example in which the present invention is applied to a multi-processor system having a distributed memory system has been shown, but the present invention is not limited to the above-mentioned embodiments. Even in a multi-processor system with a shared memory system, there is a difference in the access speed to the memory due to the distance between the memory and each processor, and the data for obtaining the data referenced by the instruction execution unit of each processor By applying to a system in which the transfer time is longer than the calculation time and the reduction of the data transfer time contributes to the improvement of the execution speed of the entire program, it is possible to obtain the same effect as in the case of the distributed memory method.

Further, in the above embodiment, an example in which the source program is compiled and executed by the compiler has been shown, but the present invention is not limited to the above embodiment. For example, the source program can be executed on a computer. The present invention can be applied to an interpreter system that executes the program as it is or a preprocessor system that generates a plurality of new source programs from one source program.

[0034]

As is clear from the above description,
In the present invention, one array data in the source program is divided into a plurality of arrays and allocated to the memories of a plurality of processors so that the instruction part in the program and the allocation / division of the array data are matched. It is possible to easily write a parallel execution program, reduce the data transfer time at the time of data reference, and reduce the execution time in parallel execution.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram showing parallel execution processing in the embodiment of the present invention.

FIG. 3 is a diagram showing a method of dividing an index.

FIG. 4 is a diagram showing a configuration of a compiler according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a syntax in the embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a computer system including a plurality of processors.

FIG. 7 is a diagram showing a conventional example (No. 1).

FIG. 8 is a diagram showing a conventional example (No. 2).

[Explanation of symbols]

 1, 21 Source program 2 Multi-processor system 22 Compiler 27 Object program 11a, 11b Processor 12a, 12b Memory 23 Source program analysis unit 24 Optimization unit 25 Code generation unit

Claims (2)

[Claims] 1. A multi-processor computer system of a distributed memory system or a shared memory system in which the access speed from the processor to the memory differs depending on the distance between the processors, and a plurality of multi-processor computer systems (2) are provided. When one source program (1) is shared and executed in parallel by the processors (2a, 2b, 2c) of the above, one array data in the source program (1) is read from one source program (1). Split into multiple arrays,
A data division / allocation system characterized by allocating to the memory of multiple processors (2a, 2b, 2c). 2. A multi-processor computer system of a distributed memory system or a shared memory system in which the access speed from the processor to the memory differs depending on the distance between the processors, and a plurality of multi-processor computer systems (2) are provided. When one source program (1) is shared by the two processors (2a, 2b, 2c) and executed in parallel, each processor (2) of the instruction part in the source program (1)
a, 2b, 2c) and array data processor (2a, 2c
A method of dividing and allocating data, characterized in that the division into memory (b, 2c) is matched.