JPH06131255A - Storage device - Google Patents

Abstract

PURPOSE:To effectively utilize an unused address area as a common memory by coupling the unused address area of an attribute memory with the final address area of a common memory through software. CONSTITUTION:This storage device is equipped with the common memory 1, the attribute memory 2, and a decoder circuit 21A which selects those memories with a memory select signal 7 and a guard enable signal 8 inputted from outside and switches a memory for selection to the attribute memory 2 by inputting a signal 22 for memory selection switching control from outside while inputting a signal for common memory selection. Further, this device is equipped with an address inverting buffer 20 which outputs an inputted address signal to the internal address bus of the memories 1 and 2 when a signal for selecting the common memory 1 is inputted and inverts and outputs the inputted address signal to the internal address bus 15 of respective memories when a signal for selecting the attribute memory 2 is inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device in which address spaces of a plurality of memories incorporated in an IC memory card are combined by software to expand the address space.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a storage device in a conventional IC memory card. In the figure,
Reference numeral 1 denotes a common memory serving as a first memory that stores input / output data and an application program. When a common memory selection signal 14a of L level is input to the bar CE terminal, the common memory 1 is activated and the bar OE terminal of L level is input. When the output enable signal 16 is input, the upper 8 bits of data are output from the data terminals D0 to D15 to the upper data bus 16a and the lower 8 bits of data are output to the lower data bus 16b.
When the level write enable signal 18 is input, data is written into the data terminals D0 to D15. AD is an address terminal to which an address signal is input via the internal address bus 15.

Reference numeral 2 is an attribute memory serving as a second memory for storing card attribute information such as physical specifications of the IC memory card and format information of the data stored in the common memory 1. The terminal configuration is the same as that of the common memory 1, but data is read and written through the data terminals D0 to D7 in the lower 8 bit configuration.

Denoted at 3 is a decoder circuit, which is a common memory 1.
Alternatively, the common memory selection signal 14a and the attribute memory selection signal 14b for selecting the attribute memory 2 are selected.
Is output. The logic levels of the selection signals 14a and 14b are determined by the combination of the logic levels of the memory selection signal 7 and the card enable signal 8 input to the MS terminal and the CS terminal of the decoder circuit 3, respectively. Also AO
The terminal is a terminal for inputting a signal when outputting data in 8-bit configuration.

An address bus buffer 4 inputs the address signal input through the external address bus 11 to the address terminals AD of the common memory 1 and the attribute memory 2 through the internal address bus 15. Reference numeral 5 denotes a control buffer. When the L-level out control signal 12 is input to the OE terminal and the H-level write control signal 13 is input to the WE terminal, the output enable signal 16 becomes L-level and the common memory 1 and the attribute are set. It is input to the bar OE terminal of the memory 2 to put each memory into a read state. Also, H level out control signal 1 is applied to the OE terminal.
2, when the write control signal 13 of L level is input to the WE terminal, the write enable signal 18 becomes L level and is input to the bar WE terminals of the common memory 1 and the attribute memory 2 to put the memory in the write state.

A data bus buffer 6 has a bar OE.
When the L-level output enable signal 16 is input to the terminal, the upper data bus 16a and the lower data bus 1
The data appearing on 6b is transferred to the upper and lower external data buses 1
When the write enable signal 18 of L level is input to the bar WE terminal, the external data bus 1
The 16-bit data appearing at 7a and 17b are input to the common memory 1 through the upper and lower data buses 16a and 16b, and the lower 8-bit data of the 16-bit data is input to the attribute memory 2 through the lower data bus 16b. Other terminal configurations are the same as those of the other memories 1, 2 and the like.

Next, the operation of the conventional IC card memory shown in FIG. 4 will be described. First, when the common memory 1 is selected and data is output to the external data buses 17a and 17b, the memory selection signal 7 input to the decoder 3 is set to H level, the card enable signal 8 is set to L level, and the data is input to the control buffer 5. Output control signal 12
The level and the write control signal 13 are set to the H level. As a result, the common memory selection signal 14a input to the common memory 1 becomes L level and the attribute memory selection signal 14b becomes H level, so that only the common memory 1 is selected, and the common memory 1 and the attribute memory 12 are input. Output enable signal 16 is L
As the level becomes high, the write enable signal 18 becomes high, and the common memory 1 becomes in the read state.

Next, an address signal for data access is input to the address buffer 4 from the external address bus 11 and sent from the address buffer 4 to the address terminals AD terminals of the common memory 1 and the attribute memory 2 via the internal address bus 15. . As a result, the data is read from the common memory 1 and the upper and lower data buses 16a,
It is placed on 16b and sent to the data bus buffer 6. Like the common memory 1, the data bus buffer 6 has an L level memory selection signal 8 and an output enable signal 18.
Is input, the sent data is output to the external data buses 17a and 17b.

When externally writing data to the common memory 1, the logical level of each signal input to the decoder circuit 3 is the same as that at the time of data reading, and the output enable signal 12 input to the control buffer 5 is set to H level.
By setting the level and the write enable signal 13 to the L level, the common memory 1 and the data bus buffer 6 are in the data write state. When an address signal is sent to the internal address bus 15 of the common memory 1 in this state, the data bus buffer 6 is sent from the external data buses 17a and 17b.
The data output to the upper and lower data buses 16a and 16b through the are stored in a predetermined address of the common memory 1 according to the address signal.

Further, when data is accessed to the attribute memory 2, when the memory selection signal 7 is set to L level and the card enable signal 8 is set to L level, the common memory selection signal 14a becomes H level and the attribute memory selection signal 14b becomes L level. Then, the attribute memory 2 is selected. When writing or reading data thereafter, the logic level contents of the output enable signal 12 and the write enable 13 are changed in accordance with the data access contents as in the case of the common memory 1, and the bars of the memories 1 and 2 are changed. The logic levels of the output enable signal 16 and the write enable signal 18 input to the OE and the bar WE are changed. The data range in which the attribute memory 2 is accessed is lower 8-bit data, and data is exchanged with the outside through the lower data bus 16b, the data buffer 6 and the lower external data bus 17b.

[0011]

Since the conventional storage device is configured as described above, once the common memory is set as the first memory and the attribute memory is set as the second memory, and the data access is performed in each memory unit. When the operation is performed, the address areas of both memories cannot be continuously used. Therefore, there is a problem that when the area used in the address area of the attribute memory is small, the remaining address area is not used as a continuous address area of the common memory and is wasted.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a storage device which can use an unused address area of an attribute memory as a common memory area.

[0013]

A storage device according to the present invention is responsive to a first memory for storing main information, a second memory for storing subordinate information relating to the main information, and a memory selection command signal. Selecting means for selecting the first memory or the second memory, and selecting a first address signal and a second address signal obtained by inverting the first address signal in synchronization with the memory selection command signal. Address generating means for selectively outputting the main information in the first memory and the second memory respectively selected by the memory selecting means based on the first address signal, and storing the second information. The subordinate information is stored in the second memory based on a signal.

[0014]

In the memory device according to the present invention, when the second memory is accessed by the second address signal which is the inversion of the first address signal, the data can be written in the order of the address starting from the final address. The upper address area above the lower address area is an unused area. Therefore, the unused address area can be effectively used as the first memory by software-combining the unused address area with the final address area of the first memory.

[0015]

【Example】

Example 1. Hereinafter, a case where one embodiment of the present invention is applied to an IC memory card will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an IC memory card according to this embodiment. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts. In the figure, reference numeral 21 is a decoder circuit as a memory selecting means, and when the memory selection signal 7 is at the H level and the card enable signal is at the L level, the most significant address signal 22 is at the L level, the common memory selection signal 14a becomes It becomes L level and the attribute memory selection signal 14b becomes H level and the common memory 1 is selected.

When the memory select signal 7 is set to H level and the card enable signal is set to L level and the highest address signal 22 is set to H level, the common memory select signal 14a becomes H level and the attribute memory select signal 14b becomes L level. Then, the attribute memory 2 is selected. That is, the highest address signal 22 makes it possible to switch the memory to be selected while maintaining the logic level of each selection signal. Reference numeral 20 denotes an address buffer circuit having a function of inverting an address signal as an address generating means, and a bit forming an address signal with a buffer 21a for outputting an address signal input via the external address bus 11 to the internal address bus 15. Is inverted and output to the internal address bus 15 in an inversion buffer 21b connected in parallel.

Further, switching selection of each buffer is performed by the buffer 2
When the memory selection signal 7 applied to the strobe terminal (not shown) of 1a becomes H level, the address signal placed on the external address bus is output to the internal address bus 15 and the memory applied to the strobe terminal of the inversion buffer 21b. When the selection signal 7 becomes L level, the address signal is inverted and output. There are as many address buffer circuits 20 as there are addresses in the actual memory, and an address signal is input to each address inversion buffer 20 in bit units.

Next, the operation of this embodiment will be described.
The data read / write control is the same as in the conventional technique. First, when both the memory selection signal 7 and the card enable signal 8 input to the decoder circuit 21 are set to L level, the common memory selection signal 14a output from the decoder circuit 21 is set to H level and the attribute memory selection signal 14b is set to L level. Therefore, the attribute memory 2 is selected and becomes active. At this time, since the memory selection signal 7 applied to the strobe terminal of the inversion buffer 20b of the address buffer circuit 20 is at L level, the inversion buffer 20b inverts the input address signal and outputs it to the internal address bus 15.

As a result, even if the address signals are set from the first address of 0 to a predetermined address, for example, n, and are input to the address buffer circuit 20, the address signal is changed from the last address of m to m.
Since the address corresponding to the address inverted to -1 is output to the internal address bus 15, the attribute memory 2 in the active state writes the attribute information of the card from the address m to the address m-1. Further, since the attribute information of the card is about 200 to 300 bytes, the used address area is smaller than the memory capacity of the attribute memory 2, and the addresses 0 to m-2 are unused address areas as shown in FIG. 2B. Become.

Next, when the memory selection signal 7 is set to H level, the card enable signal 8 is set to L level, and the highest address signal 22 is set to L level, the common memory selection signal 14a.
Becomes the L level, the common memory 1 is activated, and the buffer 20a is selected. Therefore, the address signal input to the external address bus 11 is not inverted and is output from the buffer 20a to the address terminal AD of the common memory 1 through the internal address bus 15. Therefore, if the address signal is set from address 0 to address n, the common memory 1 is accessed in ascending order from address 0 to address n as shown in FIG.

Further, when the unused address area of the attribute memory 2 is used as a common memory, the memory selection signal 7 is set to H level, the card enable signal 8 is set to L level, and the highest address signal 22 is set to H level. When the signal 4b becomes L level, the attribute memory 2 is activated and the buffer 20a is selected. Therefore, the external address bus 11
The address signal input to the buffer is output from the buffer 20a to the address terminal AD of the attribute memory 2 through the internal address bus 15.

At this time, since the address assigned to the attribute memory 2 is the inverted address when the attribute data is read and written, the start address of the unused address area is assigned first. As a result, as shown in FIG. 3, the unused address areas of the common memory 1 and the attribute memory can be combined by software as a memory space with continuous absolute addresses.

Example 2. In the first embodiment, in order to allocate the unused address area of the attribute memory 2 from the start address, the address signal output to the attribute memory 2 is inverted by hardware, but the address signal may be inverted by software. Is also possible.

[0024]

As described above, according to the present invention, the first memory for storing the main information, the second memory for storing the subordinate information related to the main information, and the memory in response to the memory selection command signal are used. Memory selecting means for selecting the first memory or the second memory, and a first address signal and a second address signal obtained by inverting the first address signal in synchronization with the memory selection command signal. Address generating means for transmitting the main information to the first memory and the second memory respectively selected by the memory selecting means based on the first address signal and storing the main information in the second address signal. By storing the dependent information in the second memory based on the above, the unused address area of the second memory is software-combined with the final address area of the first memory. There is an effect that an unused address space since it is bets can be effectively used as the first memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a storage device according to the present invention.

FIG. 2 is a diagram illustrating address areas of a common memory and an attribute memory according to this embodiment.

FIG. 3 is a diagram illustrating a memory address area when an unused address area of an attribute memory in this embodiment is used as a common memory.

FIG. 4 is a block diagram showing an overall configuration of a conventional storage device.

[Explanation of symbols]

 1 common memory 7 memory selection signal 8 card enable signal 2 attribute memory 20 address buffer circuit 21A decoder circuit 22 highest address signal

[Procedure amendment]

[Submission date] October 22, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

Next, the conventional IC memory car shown in FIG.
The operation of the de described. First, when the common memory 1 is selected and data is output to the external data buses 17a and 17b, the memory selection signal 7 input to the decoder 3 is set to H level, the card enable signal 8 is set to L level, and the data is input to the control buffer 5. Output control signal 12
The level and the write control signal 13 are set to the H level. As a result, the common memory selection signal 14a input to the common memory 1 becomes L level and the attribute memory selection signal 14b becomes H level, so that only the common memory 1 is selected, and the common memory 1 and the attribute memory 12 are input. Output enable signal 16 is L
As the level becomes high, the write enable signal 18 becomes high, and the common memory 1 becomes in the read state.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

Further, when data is accessed to the attribute memory 2, when the memory selection signal 7 is set to L level and the card enable signal 8 is set to L level, the common memory selection signal 14a becomes H level and the attribute memory selection signal 14b becomes L level. Then, the attribute memory 2 is selected. When writing or reading data thereafter, the logical level contents of the output enable signal 12 and the write enable signal 13 are changed in accordance with the data access contents as in the case of the common memory 1.
The logic levels of the output enable signal 16 and the write enable signal 18 input to the bars OE and WE of the memories 1 and 2 are changed. The data range in which the attribute memory 2 is accessed is lower 8-bit data, and the lower data bus 16b and the data buffer 6 are
And data is exchanged with the outside through the lower external data bus 17b.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

[0013]

A storage device according to the present invention is responsive to a first memory for storing main information, a second memory for storing subordinate information relating to the main information, and a memory selection command signal. Selecting means for selecting the first memory or the second memory, and selecting a first address signal and a second address signal obtained by inverting the first address signal in synchronization with the memory selection command signal. Address generating means for selectively outputting the main information in the first memory and the second memory respectively selected by the memory selecting means based on the first address signal, and storing the second information. it is the ash so as to store the dependent information in the second memory based on the signal.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

[0015]

EXAMPLES Example 1. Hereinafter, a description will be given of the case of applying an embodiment of the invention the IC memory card to take diagram as an example. Figure 1
FIG. 3 is a block diagram showing the overall configuration of an IC memory card in this embodiment. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts. In the figure, reference numeral 21 is a decoder circuit as a memory selecting means, and when the memory selection signal 7 is at the H level and the card enable signal is at the L level, the most significant address signal 22 is at the L level, the common memory selection signal 14a becomes It becomes L level and the attribute memory selection signal 14b becomes H level and the common memory 1 is selected.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Further, switching selection of each buffer is performed by the buffer 2
When the memory selection signal 7 applied to the strobe terminal (not shown) of 1a becomes H level, the address signal placed on the external address bus is output to the internal address bus 15 and the memory applied to the strobe terminal of the inversion buffer 21b. When the selection signal 7 becomes L level, the address signal is inverted and output. The address buffer circuit 20 is address signal in bits is input to the fact was separated presence of the number of addresses in the memory each address inverting buffer 20.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

As a result, even if the address signals are set from the first address of 0 to a predetermined address, for example, n, and are input to the address buffer circuit 20, the address signal is changed from the last address of m to m.
Attribute memory 2 which is the Akti I blanking state to be outputted to the internal address bus 15 so as for the address was inverted to -1 will be written card attribute information of up to m-1 address from address m . Further, since the attribute information of the card is about 200 to 300 bytes, the used address area is smaller than the memory capacity of the attribute memory 2, and the addresses 0 to m-2 are unused address areas as shown in FIG. 2B. Become.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Next, the memory select signal 7 is set to H level, the card enable signal 8 is set to L level, and the highest address signal 2 is set.
When 2 is set to L level, the common memory selection signal 14a becomes L level to activate the common memory 1 and select the buffer 20a. Therefore address signal input to the external address bus 11 is outputted through the internal address bus 15 from bus Tsu <br/> fan 20a is not inverted to the address terminal AD of the common memory 1. Therefore, if the address signal is set from address 0 to address n, the common memory 1 can be read from address 0 to address n as shown in FIG.
The data is accessed in ascending order at the address.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

Further, when the unused address area of the attribute memory 2 is used as a common memory, the memory selection signal 7 is set to H level, the card enable signal 8 is set to L level, and the highest address signal 22 is set to H level. When the signal 4b becomes L level, the attribute memory 2 is activated and the buffer 20a is selected. Therefore, the external address bus 1
The address signal input to 1 is output from the buffer 20a to the address terminal AD of the attribute memory 2 through the internal address bus 15.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

[0024]

As described above, according to the present invention, the first memory for storing the main information, the second memory for storing the subordinate information related to the main information, and the memory in response to the memory selection command signal are used. Memory selecting means for selecting the first memory or the second memory, and a first address signal and a second address signal obtained by inverting the first address signal in synchronization with the memory selection command signal. Address generating means for transmitting the main information to the first memory and the second memory respectively selected by the memory selecting means based on the first address signal and storing the main information in the second address signal. based on the fact that the power sale by storing the said dependent information in the second memory, the software binds to an unused address space of the second memory the last address region of the first memory It is effective that can be effectively used as the first memory an unused address space because it is.

Claims (1)

[Claims] 1. A first memory for storing main information, a second memory for storing subordinate information relating to the main information, and the first memory or the second memory in response to a memory selection command signal.
Memory selecting means for selecting one of the memories, and address generating means for selectively issuing a first address signal and a second address signal obtained by inverting the first address signal in synchronization with the memory selection command signal. , Main information is stored in the first memory and the second memory that are respectively selected by the memory selecting means based on the first address signal, and the second memory is stored based on the second address signal. A storage device, wherein the subordinate information is stored in the storage device.