JPH06131250A - Data processor - Google Patents

Abstract

PURPOSE:To provide the data processor which easily performs high-speed stack operation and is low in cost and improved in system performance. CONSTITUTION:A central processor 3 is equipped with an address decision means 15 which decides whether a stack pointer SP and the address indicated by the stack painter SP are in an address range for a 1st storage means 5 in the address space of a data processor and a bank control means 13 which performs control so that the reading and writing of a stack area accompanying R stack operation instruction are performed through a dedicated bus BBUS when the address decision means 15 decides that the address indicated by the stack painter SP is in the address range for the 1st storage means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stack operation technique for a data processing device having a register bank function, and more particularly,
When performing a stack operation on the built-in bank RAM, the bank transfer bus having a high data transfer speed is used to access the data in the built-in RAM, thereby facilitating the high-speed stack operation. Data processing device The present invention relates to a data processing device.

[0002]

2. Description of the Related Art In a program of a data processing device such as a microcomputer, a data structure called a stack is often used to transfer and save data. In particular, stack operation is indispensable for processing subroutine calls and interrupts, and efficient stack operation is important for system design. Therefore, in many processors, a dedicated instruction (PUSH instruction / POP instruction) for performing a stack operation, an instruction (CALL instruction / RET instruction / RETI instruction, etc.) that is supposed to perform stack processing, and interrupt processing It has a mechanism.

The stack area is taken in the memory space,
The processor internally includes a register called a stack pointer, and accesses a memory address designated by the stack pointer as the top address of the stack area.

The push (PUSH) instruction is an instruction for storing specified data in the stack area. By this push instruction, first, the stack pointer is decremented by the size of the data to be written, and the data is written to the address designated by the subtracted stack pointer.

The POP instruction is an instruction for reading data from the stack area. By this pop instruction, data is read from the address indicated by the stack pointer, and then the stack pointer is incremented by the size of the read data.

When making a subroutine call, the return destination address is pushed to the stack area and then branched to the subroutine. When the processing in the subroutine is completed, the return destination address is popped from the stack area. Therefore, it is often performed to obtain the program address in the main routine and continue the processing of the program. Further, by using the stack, it is possible to cope with the case where the branch to the subroutine is multiply performed.

Call (CALL) instruction and return (RE)
The T) instruction is an instruction prepared in the processor to support a subroutine branch. The call instruction automatically pushes the return address onto the stack, loads the subroutine address (effective address of the destination operand of the call instruction) into the program counter, and executes the instruction from that address. At the end of the subroutine, a return instruction is executed. This return instruction is executed by popping the data at the address indicated by the stack pointer (that is, the return destination address), loading it into the program counter, and executing the instruction at that address. That is, the execution of the return instruction causes the stack and the stack pointer to return to the state before the execution of the subroutine, and the execution of the program is continued from the instruction following the call instruction.

The stack can also be used when passing parameters from the main routine to the subroutine. Before executing the call instruction, push the main program to store the required number of parameters in the stack. After that, the processing is shifted to the subroutine by the call instruction. When a parameter is required in the subroutine, the memory is accessed with a relative address from the stack pointer, the return address at the top of the stack is skipped, and the parameter is accessed for processing. At this time, if necessary, the result can be written back to the position where the parameter was and the result can be passed to the main program.
When the subroutine ends, a return instruction is executed to return the processing to the main program. In the main program,
Pop the stack and receive data from the subroutine. If there is no return data, simply increment the stack pointer to restore the original stack pointer value before the subroutine call.

Next, a stack operation in interrupt processing will be described. It is similar to the above-mentioned subroutine call in that even when an interrupt occurs, the process is transferred from the program currently being executed to the interrupt processing routine, and when the interrupt process is completed, the process of the original program is restarted. However, since it is not possible to anticipate the occurrence of an interrupt in the program being executed, when the interrupt processing routine ends and returns to the original program, not only the processing from the original program address is restarted, but also general-purpose registers and control registers. It is necessary to return all the contents of to the state before the interrupt occurred. Therefore, in the case of an interrupt, not only is the return address stacked on the stack, but some or all of the registers used in the interrupt processing routine are saved on the stack. There is a difference in the method of saving information when an interrupt occurs depending on the type of processor, and it is classified as follows.

(1) Only the return address (contents of the program counter) is automatically saved in the stack.

(2) The contents of a program counter and a processor status word (a register that holds the internal state of the processor such as a flag; hereinafter referred to as PSW) are automatically saved in the stack.

(3) Save all registers such as the program counter, PSW, and general-purpose registers in the stack.

(4) A function called a register bank is prepared and all registers are saved by switching the register bank.

In the method (1), the PSW and necessary general-purpose registers are saved in the stack using the push (PUSH) instruction in the program of the interrupt processing routine. Also, before returning from an interrupt (before executing a return from interrupt (RETI) instruction), the data saved in the stack is popped to return to the state before the interrupt occurred. With a return instruction from an interrupt, only the program counter is automatically restored,
The processing of the original program continues. This method is exactly the same as the call (CALL) instruction / return (RET) instruction in the case of a subroutine, and the processor supports only saving and restoring the stack of the return address, and the necessary registers including PSW All saving is performed by the program of the interrupt processing routine. Therefore, with this method, the load on the hardware is light, but since all the registers must be saved by instructions, it becomes slow when there are many registers to save.

In the method (2), the general-purpose registers necessary for the program of the interrupt processing routine are saved to the stack by using the push (PUSH) instruction. Before returning from the interrupt, the data of the general-purpose register saved in the stack is popped to return to the state before the interrupt occurred. Return from interrupt (RET
The I) instruction automatically pops the PSW and program counter values from the stack and restores the original state.
That is, in this method, in addition to (1), the PSW is automatically saved in the stack. It is necessary to save the PSW in most interrupt processing routines, and by automatically performing this, the interrupt processing time is shortened compared to the method (1). However, saving of general-purpose registers must be performed by an instruction, and thus it becomes slow when many general-purpose registers must be saved.

In the method (3), when the interrupt occurs, the processor automatically saves all the registers in the stack, so that the interrupt processing routine program can immediately start the original interrupt processing work. The return from interrupt (RETI) instruction automatically pops the contents of all registers from the stack and returns the processor to its original state. In this method, all the registers are automatically saved in the stack by the processor, so it is not necessary to save them in the interrupt processing routine. Therefore, in the case of interrupt processing that needs to save many registers, it is faster than the methods (1) and (2). However, in the interrupt processing in which only a small number of registers need to be saved, the registers that do not need to be saved are additionally saved, resulting in slower speed.

In the method (4), when an interrupt occurs, the processor switches the register banks and automatically saves the contents of all the registers. In this case, the save destination is not the stack but the internal RA used as a register bank.
It becomes a predetermined area of M. Since the registers are all saved by the processor, the original interrupt processing work can be immediately started in the interrupt processing routine program. The return from interrupt (RETI) instruction automatically pops the contents of all registers from the stack and returns the processor to its original state. The method (4) makes it possible to save all the registers at a high speed by providing a function called a register bank without using a stack. is there.

According to the present invention, the stack operation of the data processing device with the bank function has both the method (2) which is advantageous when the number of registers saved in the interrupt processing is small and the method (4) which is advantageous when the number of registers saved is large. Is further speeded up.

The operation of the prior art microcomputer to which the present invention is applied will be described below. Figure 5
FIG. 6 is a configuration diagram of a conventional microcomputer.

This conventional microcomputer 101
Is composed of a CPU core 103, a built-in RAM 105, and a bus interface 108, and is formed as one chip. The CPU core 103 and the built-in RAM 105 have a data bus ID (15: 0), an address bus IA (2
3: 0) and an internal system bus ISBUS composed of a control signal bus IC (5: 0). Further, the CPU core 103 and the built-in RAM 105 have a bank data bus BNKD (63:
0), bank address bus BNKA (10: 0), and bank control signal bus BNKC (3: 0). Further, the microcomputer 101 has a data bus OD (15:
0), an address bus OA (23: 0), and a control signal bus OC (5: 0), an external system bus OSBUS.
The external memory 109 is connected via.

FIG. 6 is a detailed block diagram of the CPU core 103. As shown in the figure, the CPU core 103 includes registers such as a stack pointer SP, a program counter PC, a processor status word PSW, general-purpose registers R0 to R15, bank pointers CBP and PBP, and an arithmetic circuit ALU such as an adder and a shifter. A sequence control circuit 21 that decodes machine instructions to control the operation of the internal circuits of the CPU core 103, a bus control circuit 123 that controls the interface of the internal system bus ISBUS, an address buffer AB, and a data buffer DB. A bank control circuit 125 for controlling the interface of the bank transfer bus BBUS. Further, in the sequence control circuit 21, an interrupt signal INT is input to the CPU core 103 to specify whether to save a register for a memory stack or a bank (internal RAM 105) during interrupt processing. The stack / bank flag SB is provided.

For instructions such as PUSH / POP / CALL / RET instructions, the CPU core 103 uses the internal system bus ISBUS and the external system bus OSBUS to
A stack operation is performed by reading / writing the stack area in the memory space designated by the stack pointer SP. The internal RAM 105 and the external memory 109 are arranged at appropriate positions on the address of the memory space, and CP
When the address output from the U core 103 is included in the area where the internal RAM 105 is arranged, the internal RAM 105 is accessed via the internal system bus ISBUS. Further, when the address output from the CPU core 103 is included in the area where the external memory 109 is arranged, the internal system bus ISBUS-bus interface 108
-External memory 10 via external system bus OSBUS
9 is accessed. Therefore, it takes two clock bus cycles to read and write data in the external memory 109 from the CPU core 103.

At the time of interrupt processing, depending on the value of the stack / bank flag SB inside the CPU core 103, the CPU
The content of interrupt processing performed by the core 103 changes.

When the stack / bank flag SB is "1", the CPU core 103 pushes the program counter PC which is the return address and the processor status word PSW to the stack area indicated by the stack pointer SP to program the interrupt handler routine. Branch to. The stack operation at this time is performed via the system bus. General-purpose register R0 in the interrupt handler routine
When it is necessary to save .about.R15, the contents of the general registers R0 to R15 are pushed onto the stack by using the push (PUSH) instruction described above in the interrupt handler routine.

Before executing the interrupt return (RETI) instruction at the end of the interrupt handler routine, the general registers R0 to R15 saved in the stack are read from the stack by the pop (POP) instruction, and the general registers in the CPU core 103 are read. Reload to R0 to R15. Then, by executing the RETI instruction, the program counter PC and the processor status word PSW are automatically loaded from the stack, and the program before the interrupt is generated is continued.

When the stack / bank flag SB is "0", the CPU core 103 sends all the registers (SP, P) inside the CPU core 103 via the bank transfer bus BBUS.
The contents of C, PSW, SB, CBP, PBP, R0 to R15) are saved in the internal RAM 105. Bank transfer bus B
Since the BUS has a 64-bit width and is a dedicated bus for the CPU core 103 and the built-in RAM 105, high-speed operation is possible and 4-word data transfer is possible with one bus clock. Therefore, the time required to save all the registers inside the CPU core 103 is as fast as 5 clocks.

The operation of the push (PUSH) instruction is performed as follows under the control of the sequence control circuit 21.

(1) The contents of the stack pointer SP are output to the internal bus and set in the arithmetic circuit ALU.

(2) The arithmetic circuit ALU performs a subtraction to decrement the stack pointer SP.

(3) The result of the arithmetic circuit ALU is output to the internal bus, and the value obtained by decrementing the stack pointer SP is set in the address buffer AB and the stack pointer SP. (4) Set the data to be pushed in the data buffer DB.

(5) Instruct the bus control circuit 123 to perform a write bus cycle with the data in the data buffer DB using the data in the address buffer AB as an address.

(6) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), the data in the data buffer DB to the data bus ID (15: 0), and the control signal bus IC
A necessary control code is put on (5: 0) and data writing is executed.

In the case of a pop (POP) instruction, it becomes as follows.

(1) The stack pointer SP is output to the internal bus and set in the address buffer AB.

(2) The bus control circuit 123 is instructed to perform a read bus cycle using the data in the address buffer AB as an address and read the data into the data buffer DB.

(3) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), and the necessary control code is placed on the control signal bus IC (5: 0) to execute a data read bus cycle.

(4) The stack pointer SP is output to the internal bus and set in the arithmetic circuit ALU. (5) The arithmetic circuit ALU performs addition and increments the value of the stack pointer SP.

(6) The calculation result of the calculation circuit ALU is output to the internal bus and written back to the stack pointer SP.

In the call (CALL) instruction, the program counter P is operated by the same operation as the push (PUSH) instruction.
Address buffer AB after pushing C onto the stack
Then, the branch destination address is set in the program counter PC, the instruction is fetched, the instruction is decoded, the sequence control circuit 21 is operated, and the processing of the instruction at the head of the subroutine is started.

In the return (RET) instruction, the pop (P
After the return address is popped from the stack by the same operation as the (OP) instruction, it is set in the program counter PC and the address buffer AB, the instruction is fetched, and the processing of the instruction of the return destination program is started.

The processing of saving information when an interrupt occurs is as follows:
Stack / bank flag S in the sequence control circuit 21
The processing differs depending on the value of B, and is as follows.

The interrupt processing when SB = 1 is performed as follows.

(1) The contents of the stack pointer SP are decremented by using the arithmetic circuit ALU and written in the address buffer AB and the stack pointer SP.

(2) The contents of the processor status word PSW are read out to the internal bus and set in the data buffer DB.

(3) The bus control circuit 123 is instructed to perform a write bus cycle with the data in the data buffer DB using the data in the address buffer AB as an address.

(4) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), the data in the data buffer DB to the data bus ID (15: 0), and the control signal bus IC
A necessary control code is put on (5: 0) and data writing is executed.

(5) The contents of the stack pointer SP are again decremented by using the arithmetic circuit ALU and written in the address buffer AB and the stack pointer SP.

(6) The contents of the program counter PC are read out to the internal bus and set in the data buffer DB.

(7) The bus control circuit 123 is instructed to use the data in the address buffer AB as an address to perform a write bus cycle with the data in the data buffer DB.

(8) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), the data in the data buffer DB to the data bus ID (15: 0), and the control signal bus IC
A necessary control code is put on (5: 0) and data writing is executed.

(9) The start address of the interrupt processing program is set to the program counter PC and the address buffer AB.
, The instruction fetch is performed, and the processing of the first instruction of the interrupt processing program routine is started.

The processing of the interrupt return (RETI) instruction when SB = 1 is performed as follows.

(1) The stack pointer SP is output to the internal bus and set in the address buffer AB.

(2) The bus control circuit 123 is subjected to a read bus cycle with the data in the address buffer AB as an address, and the data (in this case, the contents of the program counter PC before the interrupt) is read into the data buffer DB. Instruct them to come.

(3) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), and the necessary control code is placed on the control signal bus IC (5: 0) to execute a data read bus cycle.

(4) The stack pointer SP is output to the internal bus, the arithmetic circuit ALU performs addition, and the value of the stack pointer SP is incremented.

(5) The bus control circuit 123 is subjected to a read bus cycle using the data in the address buffer AB as an address, and the data (in this case, the contents of the processor status word PSW before the interrupt) is read into the data buffer DB. Instruct them to come out.

(6) The bus control circuit 123 transfers the contents of the address buffer AB to the address bus IA (2
3: 0), and the necessary control code is placed on the control signal bus IC (5: 0) to execute a data read bus cycle.

(7) The stack pointer SP is output to the internal bus, the arithmetic circuit ALU performs addition, the value of the stack pointer SP is incremented, and this value is written to the address buffer AB and the stack pointer SP.

(8) The data of the read processor status word PSW is set to the processor status word PSW.
Write to to restore the original value. Further, the read data of the program counter PC before the interruption is written in the address buffer AB and the program counter PC,
The instruction is fetched at that address and the processing of the program before the interrupt is started.

Further, the saving of the register inside the CPU core 103 when SB = 0 is directly performed by the bank control circuit 123 to the built-in RAM 105, and the processing is as follows. The symbol "!" Is a concatenation operator.

(1) The 64-bit data of the general-purpose registers R0 to R3 are transferred to the bank data bus BNKD (63: 0).
At the address (CBP)! 000 to the bank address bus BNKA (10: 0) respectively, and
Write to 05.

(2) The 64-bit data of the general-purpose registers R4 to R7 are transferred to the bank data bus BNKD (63: 0).
At the address (CBP + 1)! 000 to the bank address bus BNKA (10: 0) respectively, and the built-in RA
Write to M105.

(3) The 64-bit data of the general-purpose registers R8 to R11 are transferred to the bank data bus BNKD (63: 0).
At the address (CBP + 2)! 000 to the bank address bus BNKA (10: 0) respectively, and the built-in RA
Write to M105.

(4) The 64-bit data of the general-purpose registers R12 to R15 are transferred to the bank data bus BNKD (63:
0) to the address (CBP + 3)! 000 is output to the bank address bus BNKA (10: 0) and written in the internal RAM 105.

(5) Bank data bus B with the contents of the program counter PC, processor status word PSW, and bank pointer PBP as 64-bit data.
Address (CBP + 4) to NKD (63: 0)! 00
0 is output to the bank address bus BNKA (10: 0) and written in the internal RAM 105.

(6) The value of the bank pointer CBP is written in the bank pointer PBP via the internal bus.

(7) The bank number used in interrupt processing is read from the data buffer DB and written in the bank pointer CBP.

(8) The start address of the interrupt handler routine is read and set in the program counter PC and the address buffer AB, the fetch of the start instruction is started, and the interrupt handler process is performed.

Further, the interrupt return (RETI) instruction when SB = 1 is performed as follows.

(1) The contents of the bank pointer PBP are set in the bank pointer CBP via the internal bus.

(2) Address (CBP)! 000 is output to the bank address bus BNKA (10: 0) and the built-in RA
The data is read from M105 to the bank data bus BNKD (63: 0) and written in the general-purpose registers R0 to R3.

(3) Address (CBP + 1)! 000 to the bank address bus BNKA (10: 0), and the internal RAM 105 outputs the bank data bus BNKD (63:
The data is read to 0) and written in the general-purpose registers R4 to R7.

(4) Address (CBP + 2)! 000 to the bank address bus BNKA (10: 0), and the internal RAM 105 outputs the bank data bus BNKD (63:
The data is read to 0) and written in the general-purpose registers R8 to R11.

(5) Address (CBP + 3)! 000 to the bank address bus BNKA (10: 0), and the internal RAM 105 outputs the bank data bus BNKD (63:
0) read the data to general purpose registers R12 to R15
Write in.

(6) Address (CBP + 4)! 000 to the bank address bus BNKA (10: 0), and the internal RAM 105 outputs the bank data bus BNKD (63:
The data is read to 0) and written to the program counter PC, the processor status word PSW, and the bank pointer PBP.

(7) The value of the returned program counter PC is set in the address buffer AB, the instruction fetch is started, and the execution of the program before the interrupt processing is started.

[0078]

As described above, in the conventional data processing device, when the interrupt occurs and the stack / bank flag is "0", the bank transfer bus BBUS.
High-speed interrupt processing is possible because data is transferred at high speed via. However, the stack / bank flag S
When B is "1", when a general-purpose register is saved and restored by a stack operation instruction from the stack area, data is accessed via the system bus even if the save destination is the internal RAM 105. It takes 2 clocks to access the data at a low speed, and also when the stack operation is attempted to be performed in the built-in RAM 105 by a subroutine call or the like, the data access is performed via the system bus, which is a slow speed. there were.

The present invention solves the above problems.
The purpose is to access data in the built-in RAM using a bank transfer bus having a high data transfer speed when performing stack operation on the built-in bank RAM in a data processing device having a register bank function. It is to provide a low-cost data processing device with improved system performance that can easily perform high-speed stack operation by controlling the data processing.

[0080]

In order to solve the above-mentioned problems, the first feature of the present invention is to use a central processing unit 3 for processing a program and a bank as shown in FIG. 1 (1). And a second storage unit 7 for holding the program. The central processing unit 3, the first storage unit 5, and the second storage unit 7 include a system bus SBUS. And the central processing unit 3 and the first storage means 5 are connected by a dedicated bus BBUS,
In the central processing unit 3, the stack pointer SP and the first storage unit 5 in which the address indicated by the stack pointer SP is in the address space of the data processing unit.
When the address indicated by the stack pointer SP is judged by the address judging means 15 for judging whether or not it is in the address range for the first storage means 5. The bank control means 13 for controlling reading and writing to and from the stack area according to the stack operation instruction via the dedicated bus BBUS.

The second feature of the present invention is that FIG.
And (2), it comprises a central processing unit 3 ′ for processing a program, a first storage means 5 used as a bank, and a second storage means 7 for holding the program, Central processing unit 3 ', first storage means 5,
And the second storage means 7 are connected by a system bus SBUS, and the central processing unit 3 ′ and the first storage means 5 are
Connected by a dedicated bus BBUS, the central processing unit 3 '
Is the dedicated bus B for the first storage means 5.
A bank stack pointer BSP holding an address for accessing via the BUS, and reading / writing from / to a stack area in the first storage means 5 based on the address indicated by the bank stack pointer BSP, by using the dedicated bus BBUS. A bank control unit 13 'for controlling the execution of the register via a bank stack pointer BSP, and holds a plurality of registers in the central processing unit 3'at the address of the first storage unit 5 designated by the bank stack pointer BSP. This is to provide a machine instruction for performing stack operation by transferring data to be transferred at one time through the dedicated bus BBUS.

Furthermore, a third feature of the present invention is that in the data processing device according to claim 1 or 2, the central processing device 3 or 3 ′, the first storage means 5, and the second storage means 7 are provided. Is to be configured on one chip.

[0083]

In the data processing device of the first and third features of the present invention, as shown in FIG. 1A, the address determination means 15 in the central processing unit 3 causes the stack pointer S to move.
It is determined whether the address indicated by P is within the address range for the first storage means 5 in the address space of the data processing device, and the address indicated by the stack pointer SP is within the address range for the first storage means 5. If it is determined that, the bank control unit 13 controls to read / write the stack area in accordance with the stack operation instruction via the dedicated bus BBUS.

As a result, the address indicated by the stack pointer SP is automatically determined and the stack area is set to the first area.
When it is in the area of the storage means 5, the read / write can be performed at high speed by using the dedicated bus BBUS between the central processing unit 3 and the first storage means 5, and as a result, high-speed stack operation is facilitated. It is possible to realize a low-cost data processing device with improved system performance.

In the data processor of the second and third features of the present invention, as shown in (1) and (2) of FIG. 1, the bank stack pointer BSP is set as one machine instruction of the central processing unit 3 '. A machine instruction for performing stack operation by transferring data held by a plurality of registers in the central processing unit 3 ′ at a time to a designated address of the first storage means 5 through a dedicated bus BBUS to perform stack operation. At the time of issuing the machine instruction, the bank control means 13 'controls the reading and writing to the stack area in the first storage means 5 through the dedicated bus BBUS based on the address indicated by the bank stack pointer BSP.

As a result, at the time of issuing the machine instruction, the reading and writing of the data held by the register group in the central processing unit 3'to the stack area on the first storage means 5 is performed at high speed by the dedicated bus BBUS. As a result, it is possible to realize a low-cost data processing apparatus with improved system performance, which can easily perform high-speed stack operation.

[0087]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a data processing apparatus according to the first embodiment of the present invention. In the figure, the same parts as those in FIG. 5 (conventional example) are designated by the same reference numerals.

The data processor of this embodiment comprises a microprocessor (hereinafter abbreviated as MPU) 1 and an external memory 9 formed on one chip. The MPU 1 and the external memory 9 are connected to the data bus OD (15: 0). ), Address bus O
They are connected via an external system bus OSBUS composed of A (23: 0) and a control signal bus OC (5: 0).

In FIG. 1, the MPU 1 is composed of a CPU core 3, a built-in RAM 5 and a bus interface 8 and is formed as one chip. CPU core 3
The built-in RAM 5 has a data bus ID (15: 0), an address bus IA (23: 0), and a control signal bus IC (5:
0) connected via the internal system bus ISBUS, and the CPU core 3 and the built-in RAM 5 realize the bank function by using the bank data bus BNKD (63:
0), bank address bus BNKA (10: 0), and bank control signal bus BNKC (3: 0).

FIG. 2 shows a detailed configuration diagram of the CPU core 3 of the first embodiment. As shown in the figure, the CPU core 3 includes a stack pointer SP, a program counter PC, a processor status word PSW, and general-purpose registers R0 to R1.
5, registers such as bank pointers CBP and PBP,
An arithmetic circuit ALU such as an adder and a shifter, a sequence control circuit 21 that decodes machine instructions to control the operation of the internal circuit of the CPU core 3, a bus control circuit 23 that controls the interface of the internal system bus ISBUS, and an address. The buffer AB, the data buffer DB, the bank control circuit 25 that controls the interface of the bank transfer bus BBUS, the address determination circuit 27 that determines the address of the stack pointer SP, and the hit flag HIT that holds the result of the address determination circuit 27. And a memory stack flag MS indicating that it is a memory stack operation instruction
It consists of and.

In the sequence control circuit 21, C
The PU core 3 is provided with a stack / bank flag SB that designates whether the interrupt signal INT is input and the registers are saved in the memory stack or in the bank (internal RAM 5) during interrupt processing. . Further, the data buffer DB and the bank control circuit 25 are connected, and the output of the stack pointer SP is connected to the bank control circuit 25, which is different from the conventional example (FIG. 6). The hit flag HIT and the memory stack flag MS are connected to the bus control circuit 23 and the bank control circuit 25.

The memory stack flag MS is set when the machine instruction is decoded by the sequence control circuit 21 and the machine instruction is a stack operation instruction. The stack operation instructions are PUSH / POP / CALL.
There are instructions such as the / RET instruction.

Memory stack flag MS = 1: stack operation instruction Memory stack flag MS = 0: not stack operation instruction The hit flag HIT is set with the output of the address determination circuit 27 and the address SP of the stack pointer SP.
(23: 0) has information as to whether or not the internal RAM 5 is designated.

Hit flag HIT = 1: address where internal RAM 5 is located Hit flag HIT = 0: address other than internal RAM 5 2 [K bytes] from address 0 to address 2047 are allocated to internal RAM 5 When the stack pointer SP is present, the address determination can be performed by inverting the logical sum of the upper 13 bits of the stack pointer SP.

When the memory stack flag MS = 1 and the hit flag HIT = 1, it means that the stack area is on the internal RAM 5 by the stack operation instruction. Therefore, the stack operation instruction using the bank transfer bus BBUS is as follows. It is executed like.

First, the operation of the push (PUSH) instruction is as follows.
It is performed as follows.

(1) The stack pointer SP is output to the internal bus and set in the arithmetic circuit ALU. (2) The arithmetic circuit ALU performs subtraction and decrements the stack pointer SP.

(3) The result of the arithmetic circuit ALU is output to the internal bus, and the value obtained by decrementing the stack pointer SP is set in the address buffer AB and the stack pointer SP. (4) Set the data to be pushed in the data buffer DB.

(5) Since the memory stack flag MS = 1 and the hit flag HIT = 1, the data of the stack pointer SP is input to the bank control circuit 25 and output as an address to the bank address bus BNKA (10: 0). It Further, the data in the data buffer DB is input to the bank control circuit 25 and used as write data.
Then, the bank control circuit 25 is instructed to write to the built-in RAM 5.

(6) The bank control circuit 25 writes the data of the bank data bus BNKD (63: 0) to the position on the internal RAM 5 designated by the bank address bus BNKA (10: 0) according to the instruction.

The operation of the pop (POP) instruction is performed as follows.

(1) The stack pointer SP is output to the internal bus and set in the address buffer AB.

(2) Since the memory stack flag MS = 1 and the hit flag HIT = 1, the data of the stack pointer SP is input to the bank control circuit 25 and output to the bank address bus BNKA (10: 0) as an address. It Further, the bank control circuit 25 is instructed to read from the built-in RAM 5.

(3) The bank control circuit 25 follows the instruction from the internal RAM 5 to the bank data bus BNKD (63:
Since the data is read to 0), the data is set in the data buffer DB.

(4) The stack pointer SP is output to the internal bus and set in the arithmetic circuit ALU. (5) The arithmetic circuit ALU performs addition and increments the stack pointer SP.

(6) The result of the arithmetic circuit ALU is output to the internal bus and written back to the stack pointer SP.

With the call (CALL) instruction, the bank transfer bus BB is operated by the same operation as the push (PUSH) instruction.
After the contents of the program counter PC are pushed onto the stack via the US, the branch destination address is set in the address buffer AB and the program counter PC to fetch the instruction, decode the instruction and operate the sequence control circuit 21. , Start processing the first instruction of the subroutine.

In the return (RET) instruction, after the return destination address is popped from the stack via the bank transfer bus BBUS by the same operation as the pop (POP) instruction, the popped address is returned to the program counter PC and the address buffer AB. To fetch the instruction and start processing the instruction of the return destination program.

Further, in cases other than the memory stack flag MS = 1 and the hit flag HIT = 1, the operation is performed via the system bus as in the conventional case.

Next explained is a data processing device according to the second embodiment of the invention. The schematic configuration of the data processing device of the second embodiment is almost the same as that of the first embodiment, but C
The configuration of the PU core is different. A block diagram of the CPU core of the second embodiment is shown in FIG.

As shown in the figure, the CPU core 3'includes a stack pointer SP, a program counter PC, a processor status word PSW, and general purpose registers R0 to R1.
5, bank pointers CBP and PBP, bank stack pointer BSP and other registers, adder, shifter and other arithmetic circuits ALU, machine instructions are decoded to make CPU core 3
Sequence control circuit 21 for controlling the operation of the internal circuit of
A bus control circuit 23 'for controlling the interface of the internal system bus ISBUS, and an address buffer AB.
, A data buffer DB, and a bank control circuit 25 'for controlling the interface of the bank transfer bus BBUS.

In the sequence control circuit 21, C
The PU core 3 is provided with a stack / bank flag SB that designates whether the interrupt signal INT is input and the registers are saved in the memory stack or in the bank (internal RAM 5) during interrupt processing. .

In the CPU core 3'of this embodiment, the stack pointer SP and the bank pointer PBP are connected to the bank control circuit 25 ', and data transfer is possible via the bank transfer bus BBUS. A pointer BSP is added and can be accessed from the internal bus.
Further, it is different from the conventional example (FIG. 6) in that it is connected to the bank control circuit 25 ′ and data can be transferred via the bank transfer bus BBUS.

Further, in this embodiment, special instructions (PUSHB instruction and POPB instruction) for performing stack operation are added to the internal RAM 5 from the bank transfer bus BBUS. The PUSHB instruction and the POPB instruction are instructions that perform a stack operation in the memory area on the internal RAM 5 designated by the bank stack pointer BSP, and have 6 operands.
Multiple registers for 4 bits can be specified. The assembler format and operation specifications of these stack manipulation instructions are shown below.

(1) POPB instruction: transfer from stack area on internal RAM 5 [assembler format] POPB greg [operation] greg ← (BSP), BSP ← BS
Built-in RAM 5 indicated by P + 1 bank stack pointer BSP
8 bytes of data are transferred from the memory address ((BSP)! 000) to greg, and the bank stack pointer BSP is incremented by 1.

(2) PUSHB instruction: transfer to stack area on internal RAM 5 [assembler format] PUSHB greg [operation] BSP ← BSP-1, (BSP) ← g
reg First, the bank stack pointer BSP is incremented by 1, and then gr is stored in the memory address ((BSP)! 000) of the internal RAM 5 indicated by the bank stack pointer BSP.
The data of eg is transferred.

The registers that can be specified by greg are as shown in FIG.

The PUSHB instruction is processed inside the CPU core 3 as follows.

(1) The bank stack pointer BSP is output to the internal bus and set in the arithmetic circuit ALU.

(2) The arithmetic circuit ALU performs subtraction to decrement the bank stack pointer BSP.

(3) The result of the arithmetic circuit ALU is output to the internal bus, and the decremented value is the bank stack pointer B.
Write back to SP.

(4) For the bank control circuit 25 ', gr
The contents of the register group specified by eg are output to the bank data bus BNKD (63: 0), and the address ((BSP)! 000) of the internal RAM 5 generated from the bank stack pointer BSP is output to the bank address bus BNK.
The output is instructed to A (10: 0), and the writing is instructed.

(5) The bank control circuit 25 'writes the data of the bank data bus BNKD (63: 0) to the position on the internal RAM 5 designated by the bank address bus BNKA (10: 0) according to the instruction.

The operation of the POPB instruction is performed as follows.

(1) The stack pointer SP is output to the internal bus and set in the address buffer AB.

(2) The bank control circuit 25 'is made to output the address ((BSP)! 000) as the read address of the internal RAM 5 to the bank address bus BNKA (10: 0), and the instruction to read the internal RAM 5 is issued. Give out.

(3) The bank control circuit 25 'follows the bank data bus BNKD (63:
Since the data is read to 0), the data is written to the register group designated by greg.

(4) The bank stack pointer BSP is output to the internal bus and set in the arithmetic circuit ALU.

(5) The arithmetic circuit ALU performs addition, and the bank stack pointer BSP is incremented.

(6) The result of the arithmetic circuit ALU is output to the internal bus and written back to the bank stack pointer BSP.

[0132]

As described above, according to the present invention, in the central processing unit, the address determination means causes the address indicated by the stack pointer to be within the address range for the first storage means in the address space of the data processing apparatus. If it is determined that the address indicated by the stack pointer is within the address range for the first storage means, the bank control means performs exclusive read / write access to the stack area accompanying the stack operation instruction. Since the control is performed via the bus, the address indicated by the stack pointer is automatically determined. If the stack area is in the area of the first storage means, the central processing unit and the first It is possible to read and write at high speed using a dedicated bus between storage means, and as a result, high-speed stack operation can be easily performed. , It is possible to provide a data processing device with improved system performance at low cost.

Further, in the data processor of the second and third features of the present invention, as one machine instruction of the central processing unit, the central processing is performed for the address of the first storage means designated by the bank stack pointer. A machine instruction for performing stack operation by transferring data held by a plurality of registers in the device at a time via a dedicated bus is provided, and at the time of issuing the machine instruction, the address indicated by the bank stack pointer BSP by the bank control means. Based on the above, it is decided that reading and writing from and to the stack area in the first storage means are controlled via a dedicated bus. Therefore, when issuing the machine instruction, the stack area in the first storage means is
Data held by the registers in the central processing unit can be read and written at high speed with a dedicated bus, and as a result, high-speed stack operation can be performed easily, and data processing with improved system performance at low cost can be performed. A device can be provided.

Further, the speed of the subroutine call in the data processing device and the speed of the context switch when an interrupt occurs are realized, and the system performance can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention or a configuration diagram of a data processing device according to first and second embodiments of the present invention.

FIG. 2 is a detailed configuration diagram of a CPU core of the data processing device according to the first embodiment of the present invention.

FIG. 3 is a detailed configuration diagram of a CPU core of the data processing device according to the second embodiment of the present invention.

FIG. 4 is a POP in the data processing device according to the second embodiment.
6 is a list of registers that can be specified by greg of a B instruction and a PUSHB instruction.

FIG. 5 is a configuration diagram of a conventional data processing device.

FIG. 6 is a detailed configuration diagram of a CPU core of a conventional data processing device.

[Explanation of symbols]

 1 Microprocessor (MPU) 3,3 ', 103 Central Processing Unit (CPU Core) 5,105 First Storage Means (Built-in RAM) 7 Second Storage Means (Built-in ROM) 8,108 Bus Interface 9,109 External Memory 11 Bus control means 13, 13 'Bank control means 15 Address determination means SP Stack pointer BSP Bank stack pointer SBUS System bus OSBUS External system bus OD (15: 0) Data bus OA (23: 0) Address bus OC (5: 0) Control signal bus ISBUS Internal system bus ID (15: 0) Data bus IA (23: 0) Address bus IC (5: 0) Control signal bus BBUS Dedicated bus (bank transfer bus) BNKD (63: 0) Bank Data bus BNKA (10: 0) Bank address B BNKC (3: 0) Bank control signal bus INT interrupt signal PC program counter PSW processor status word R0 to R15 general purpose register CBP, PBP bank pointer ALU arithmetic circuit 21 sequence control circuit 23, 23 ', 123 bus control circuit AB address buffer DB data buffer 25, 25 ', 125 bank control circuit 27 address determination circuit HIT hit flag MS memory stack flag SB stack / bank flag

Claims (3)

[Claims] 1. A central processing unit for processing a program, a first storage unit used as a bank, and a second storage unit for holding the program, wherein the central processing unit and the first storage unit are provided. The storage unit and the second storage unit are connected by a system bus, the central processing unit and the first storage unit are connected by a dedicated bus, and the central processing unit includes a stack pointer and a stack pointer. An address determination unit that determines whether the address indicated is within the address range for the first storage unit in the address space of the data processing device, and the address indicated by the stack pointer is determined by the address determination unit. If it is determined to be within the address range for the first storage means, read / write to / from the stack area accompanying the stack operation instruction is performed. The data processing apparatus characterized by having a bank control means for controlling to perform via the bus of the dedicated. 2. A central processing unit that processes a program, a first storage unit that is used as a bank, and a second storage unit that holds the program, the central processing unit and the first storage unit. The storage unit and the second storage unit are connected by a system bus, the central processing unit and the first storage unit are connected by a dedicated bus, and the central processing unit is connected to the first storage unit. A bank stack pointer holding an address for accessing via the dedicated bus, and an address indicated by the bank stack pointer,
Bank control means for controlling reading and writing to and from the stack area in the first storage means via the dedicated bus, and with respect to an address of the first storage means designated by the bank stack pointer. And a machine instruction for performing stack operation by transferring data held by a plurality of registers in the central processing unit at a time via the dedicated bus. 3. The data processing device according to claim 1, wherein the central processing unit, the first storage unit, and the second storage unit are configured on a single chip.