JPH0612875A - Decoding circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption without hindering the high speed operation of a decoding circuit. CONSTITUTION:In the decoding circuit having a current changeover circuit CSO driven by an input code and a wired OR circuit connecting its output to plural decoding lines DL, an active current source AEF comprizing a current supply source Q5 connected to the respective decoding lines DL and a current control circuit Q6 controlling the current from the current supply source Q5 by the voltage corresponding to the potential of the decoding lines DL is provided. Both the current supplying terminal and the current control terminal of the active current source AEF are driven by decoding output signals the same in decoding logic as and different in voltage level from each other. Consequently, a large emitter follower current flows and a high speed response is attained hen the output potential of the decoding line is changed over and it is prevented that the active current source is driven by an excessive voltage and a large pass current does not flow to the active current source when the output potential is at a stationary potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit, and more particularly to a decoding circuit used for address decoding of a memory device and the like, and more particularly to a decoding circuit having a high speed and low power consumption.

[0002]

2. Description of the Related Art As a decoding circuit for a semiconductor memory device,
Conventionally, an emitter follower type wired OR / decode circuit as shown in FIG. 2 is known. The code signal decoded in this circuit is applied to the decode lines DL10 to DL13 via the current switching circuits CS0 and CS1 having an output circuit composed of a current switch and emitter follower transistors Q3 and Q4. IEF is a constant current source, CL10 to CL13, which is a source of the decode line current.
Is the load capacitance of the decode line.

In this circuit, the decode lines DL10-DL10 are used.
The rising edge of the signal at DL13 is very fast because the emitter follower transistors Q3 and Q4 transiently and rapidly charge the load capacitors CL10 to CL13. However, since the falling edge is determined by the discharge of the constant current source IEF, the constant current source IEF through which a large current flows is required for speeding up. The current of the constant current source IEF is the decode line DL.
It is constantly flowing even when the potentials of 10 to DL13 are stable at high potential or low potential. From the above, the conventional emitter follower type wired OR / decode circuit has a problem that it is difficult to reduce the power consumption.

On the other hand, in order to reduce power consumption, a logic circuit including an active emitter follower as shown in FIG. 3 has been proposed (Japanese Patent Laid-Open Publication No. 58-43628).
issue). This logic circuit is composed of a current switching circuit CS0 and an active emitter follower AEF. The active emitter follower AEF is composed of a multi-emitter npn transistor Q5, a diode D1 and a resistor R1 connected in series to one of the multi-emitters, and an emitter, a collector and a base of the other multi-emitter, respectively.
It is composed of a resistor R1 and a pnp transistor Q6 connected at a connection point of the diode D1 and the resistor R1. Parasitic capacitances CL and C1 are parasitic on the emitter and base of the transistor Q6, respectively.

The value of the parasitic capacitance of the logic circuit is usually CL
Since> C1, when the base potential of the transistor Q5 rises, the emitter potential of the transistor Q6 (output OU
The base potentials of Q5 and Q6 rise faster than T).
Therefore, during the transition, the base-emitter voltage VB of Q6
E decreases and the base-emitter voltage VBE of the transistor Q5 increases. As a result, the transistor Q5 is in a strong conductive state, the load capacitance CL is rapidly charged, and the output OUT rises at high speed.

On the other hand, when the base potential of the transistor Q5 falls, the emitter potential of the transistor Q6 (output OU
The base potentials of the transistors Q5 and Q6 fall faster than T). As a result, the base-emitter voltage VBE of Q5 decreases during the transition, and the voltage VBE of the transistor Q6 decreases.
BE increases. As a result, the transistor Q6 is in a strong conductive state, the load capacitance CL is rapidly discharged, and the output OU
T falls fast.

As described above, the active emitter follower A
In the EF, a large emitter follower current flows at the transition when the output potential switches, and a high speed response is achieved. Moreover,
The diode D1 and the transistor Q6 form a current mirror circuit, and by setting the current of the diode D1 to a small current, the transistor Q6 is turned on at a steady potential.
It is possible to allow only a small current to flow through 6. That is,
Transistor Q6 acts as an active current source. In this way, the active emitter follower is effective in achieving both high speed and low power consumption.

[0008]

It is possible to apply a logic circuit as shown in FIG. 3 to the decoding circuit of the semiconductor memory device. However, when wired OR-decoding is performed by the output of the active type emitter follower AFF, the emitter is output at the steady potential. A problem occurs that a through current flows through the follower AFF, which makes it difficult to reduce the power consumption of the decoding circuit. This problem will be briefly described with reference to FIG. FIG. 3 shows a wired OR decoding circuit in which the emitter followers Q3 and Q4 of the output circuit of FIG. 2 are replaced by the active emitter follower AFF of FIG. For example, the input I of the current switching circuits CS0 and CS1
If N0 and IN1 are both at low potential, the base potential of the transistor Q5 of the active emitter followers AEF00 to AEF11 is low at AEF00 and AEF10, and AE is low.
F01 and AEF11 have a high potential.

Therefore, by the wired OR / decode logic, only the potential of the decode line DL10 is low and the other decode line potentials are high. From the above potential relationship, the problem is that the emitter followers AEF00 and AEF are
This is the voltage VBEp applied between the base and emitter of the transistor Q7 of No. 10, and VBEp is given by the following equation.

VBEp = VBEd + Vα VBEd: forward voltage of the diode Vα: signal amplitude of the decode line Since the voltage value of VBEd + Vα is a voltage value for strongly conducting the pnp transistor, a large current always flows in the decode line. That is, the emitter follower A
The emitter (decode line) of the pnp transistor Q7 of EF00 and AEF10 is driven by a signal on which the wired OR / decode logic is executed, while the base is driven by the output signal of the current switching circuit. For this reason, the base-emitter voltage of the pnp transistor Q7 becomes excessively large even at a steady potential, a through current flows, and it becomes difficult to reduce power consumption. Therefore, an object of the present invention is to realize a decoding circuit which operates at high speed and consumes less power.

[0011]

To achieve the above object, a decoding circuit of the present invention inputs a current switch driven by an input code and the output of the current switch to generate a plurality of outputs of the same level. In a decoding circuit having a current switching circuit including an output circuit and a wired OR circuit in which the plurality of outputs are connected to a plurality of decoding lines, a current supply source connected to each of the plurality of decoding lines and the current. An active current source including a current control circuit for controlling the current of the supply source with a voltage corresponding to the potential of the first decode line is provided. In the above configuration, the configuration from the current switching circuit to the plurality of decode lines is substantially the same as the conventional decode circuit. In addition to the emitter follower AEF shown in FIG. 3, a preferred embodiment of the active current source is a signal in which the current supply source and the current control circuit as shown in the following embodiments have the same logic level but different voltage levels. It is configured to be driven by.

[0012]

According to the decoding circuit of the present invention, the wired O
An active current source is connected to each of the decode lines forming the R circuit, and the decoded signal is taken out via the output section of the active current source. Therefore, the line length of the plurality of decode lines directly connected to the current switching circuit can be shortened, the load capacitance can be reduced, and the current value of the constant current source connected to each decode line can be set low. In addition, a signal can rise and fall at high speed, and a large through current does not flow through the decode line, the current supply source, and the current control circuit portion when the signal is stationary, so that power consumption can be reduced.

[0013]

1 is a circuit diagram of a first embodiment of a decoding circuit according to the present invention. In the circuit of the present embodiment, the current switching circuit CS0 and the first plurality of decode lines DL11 to DL11.
The DL 13 part is substantially the same as the conventional emitter follower type wired OR / decode circuit described in FIG. 2, and the configuration and operation of the circuit AEF section itself are substantially the same as those of the active current source AEF in FIG. is there. In the circuit components, the same parts as those of the circuit components of FIGS. 2 and 3 are designated by the same reference numerals and detailed description thereof will be omitted.

A current switch (Q1, Q2, IC, etc.) driven by the input codes INO, IN1 and an output circuit (Q3, Q4) for receiving the outputs of the current switch and generating a plurality of outputs of the same level. A current switching circuit CS0, CS1 and a wired OR circuit in which the plurality of outputs are connected to a plurality of decode lines DL11 to DL13, and an active current source is provided to each of the plurality of decode lines DL11 to DL13. AEF0 to AEF3 are connected. Active current source A
Each of EF0 to AEF3 is composed of a current supply source composed of a multi-emitter transistor Q5 and a current control circuit composed of a transistor Q6 controlling the current of the current supply source. The potential of the decode line DL11 is supplied to the diode D1 at the base of the transistor Q6.
The voltage shifted by is applied. Further, the logic level signal is output from one emitter of the transistor Q5 to the output unit OU.
It is output as a decoded signal via T0.

Inputs IN0 and IN of the current switching circuit CSO
When 1 is switched and the potential of the decode line DL10 falls, p of the active emitter follower AEF0 is set as described above.
Emitter potential of np transistor Q6 (output OUT0)
The base potential falls faster. Therefore, during the transition, the base-emitter voltage VBE of Q5 of AEF0 decreases and the VBE of Q6 increases. As a result, the transistor Q6 is brought into a strong conductive state, the load capacitance CL20 is rapidly discharged, and the output OUT0 falls at a high speed. At the time of rising, the output OUT0 also rises at a high speed as described above.

FIGS. 5 and 6 are schematic circuit diagrams in which the conventional decoding circuit and the decoding circuit of the present invention are applied to a semiconductor memory having 256 word drivers, respectively. It will be described with reference to these drawings that the decoding circuit of the present invention consumes less power than the conventional decoding circuit. Since the word driver has three inputs and the output of the decoding circuit is added to 256 word drivers, the current switching circuits CS0 to CS7 are divided into groups of two circuits, three circuits and three circuits for decoding.

When the conventional emitter follower type wired OR / decode circuit of FIG. 3 is used in the decode circuit of the memory of FIG. 5, the word driver layout pitch is set to 1
When the length is 0 μm, the wiring length of the decode lines DL10 to DL13 is about 2560 μm. In addition, the maximum number of word drivers connected to one decode line is 64. Therefore, the values of the load capacitances CL10 to CL13 of the decode line become large, and the current of the constant current source IEF needs to be 2.5 to 3 mA in order to cause the fall of the decode line potential at high speed.

On the other hand, in the case of the embodiment of the present invention shown in FIG. 6, the lengths of the decode lines DL10 to DL13 directly connected to the current switching circuits CS0 to CS7 are the same as those of the active current source AEF and the current switching circuit CS0. ~ As much as necessary for wiring with CS7, the current switching circuit CS
It is determined by the layout pitch of 0 to CS7. Therefore, when the layout pitch of the current switching circuit is 100 μm, the maximum wiring length of the decode line is about 300 μm because it is about 3 circuits of the current switching circuit. Moreover, since the number of active emitter followers AEF connected to one decode line is one, the load capacitance CL10 of the decode line is
CL13 is reduced to about 1/10 as compared with the case of the conventional example. Therefore, the current of the constant current source IEF can be reduced to about 1/10. Further, the load capacitances CL0 to CL3 of the drive lines DL0 to DL3 of the word driver are as large as the load capacitances CL10 to CL13 of the conventional circuit,
Since the active emitter follower AEF is transiently charged and discharged, power consumption is not so large. From the above, low power consumption can be achieved by the present invention.

FIG. 7 shows a second decoding circuit according to the present invention.
3 is a circuit diagram of the embodiment of FIG. In this embodiment, n used in the active emitter follower of the first embodiment shown in FIG.
The level shift circuit by the pn transistor Q5 and the diode D1 is omitted. Instead, the level shift circuit is configured by the diodes D2 and D3 that are respectively provided in series between the first decode lines DL10 to DL13 and the constant current source IEF. A signal from the anode of the diode D2 drives the base of the npn transistor Q5 of the active emitter followers AEF0 to AEF3, and a signal from the cathode of the diode D3 drives the p of the active emitter followers AEF0 to AEF3.
It drives the base of the np transistor Q6. That is, the active emitter follower is driven by signals having the same decoding logic but different voltage levels. As a result, the npn transistor Q5 and the diode D1 of the embodiment of FIG.
The circuit and current required for the level shift due to are unnecessary, and the power consumption is further reduced as compared with the first embodiment.

FIG. 8 shows a third decoding circuit according to the present invention.
3 is a circuit diagram of the embodiment of FIG. In this embodiment, wired OR decoding is performed at the emitter of the pnp transistor Q6 of the active emitter follower AEF. That is, the signals generated by the current switching circuits CS0 and CS1 are wired-OR-decoded by the decode lines DL20 to DL23 to drive the emitter of the pnp transistor Q6 of the active emitter follower AEF. On the other hand, the signal wire-ORed and decoded by the decode lines DL10 to DL13 drives the base of the pnp transistor Q6 of the active emitter follower AEF. 1 and 7 described above.
In the embodiment shown in FIG. 1, after receiving the wired-OR decoded signal at the base of the npn transistor Q5, pnp
It was supplied to the emitter of the transistor Q6. Therefore,
This embodiment is one stage faster than the embodiment shown in FIGS. 1 and 7 by one emitter follower.

FIG. 9 shows a fourth decoding circuit according to the present invention.
3 is a circuit diagram of the embodiment of FIG. In the embodiments of FIGS. 1, 7, and 8, only the transistors Q3 and Q4 of the output circuits of the current switching circuits CS0 and CS1 drive the decode line having a large load capacitance. Therefore, high-speed operation of the current switching circuit may be hindered. The fourth embodiment is made to eliminate these problems.

In the present embodiment, the current switch of the current switching circuit CS0 and the transistors Q3a, Q4 of the output circuit.
An emitter follower (Q7, Q8) is provided between the emitter and a. This emitter follower includes a transistor Q7 and a diode D2, and a transistor Q8 and a diode D3.
It is composed of. Then, through the transistors Q7 and Q8, the output stage multi-emitter transistor Q3a,
The signals sent to Q4a are the decode lines DL20 to DL2.
3 is wired-OR-decoded to drive the emitter of the pnp transistor Q6 of the active emitter follower AEF. On the other hand, the signals sent to the transistors Q3b and Q4b in the output stage via the diodes D2 and D3 are wired-OR decoded by the decode lines DL10 to DL13 to drive the base of the pnp transistor Q6 of the active emitter follower AEF. In this way, by providing one stage of the emitter follower in the output circuit of the current switching circuit CS0, the speed of the decoding circuit can be increased.

FIG. 10 shows an active emitter follower AEF.
2 shows an alternative element of the pnp transistor Q6 of FIG. As shown in the figure, the pnp transistor Q6 is replaced with a PMOS transistor. Also, it can be replaced with a C-Bip circuit composed of a PMOS transistor and an npn transistor.

FIG. 11 is a circuit diagram of another embodiment of the current switching circuit implemented in the decoding circuit according to the present invention. The wired OR / decode line and the pnp transistor Q6 of the active emitter follower AEF are shown in FIG.
It is not shown because it is substantially the same as the embodiment of FIG. The embodiment of FIGS. 8 and 9 is an active emitter follower A.
The emitter and base of the EF pnp transistor Q6 were driven with the same amplitude. The circuit of FIG. 11 drives the emitter and base of the pnp transistor Q6 of the active emitter follower AEF with different amplitudes. As shown in the figure, in order to supply different amplitudes, the resistors that are collector loads of the current switching transistors Q1 and Q2 of the current switching circuit CS0 are divided into two. The signals obtained by these load resistors are sent to the transistors Q3a, Q4a, Q3b, Q4b in the output stage, either directly or via an emitter follower circuit as shown in the figure, and used as wired OR decode signals. To be done.

[0025]

As described above, according to the present invention, a large emitter follower current flows only during a transition in which the output potential of the decode line switches, and a high speed response is achieved. Moreover,
When the output potential of the decode line is a steady potential, it is possible to avoid driving the active current source with an excessive voltage, and a large through current does not flow in the active current source. Therefore, it is possible to reduce power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a decoding circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first example of a conventional decoding circuit.

FIG. 3 is a circuit diagram of a conventionally known logic circuit including an active emitter follower.

FIG. 4 is a circuit diagram of a decoding circuit considered from a conventional technique.

FIG. 5 is a schematic block diagram of a decoding circuit for explaining the problems of the conventional decoding circuit.

FIG. 6 is a schematic block diagram of a decoding circuit for explaining a reduction in power consumption of the decoding circuit of the present invention.

FIG. 7 is a circuit diagram showing a second embodiment of the decoding circuit according to the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the decoding circuit according to the present invention.

FIG. 9 is a circuit diagram showing a fourth embodiment of the decoding circuit according to the present invention.

FIG. 10 is an explanatory diagram of circuit components used in the decoding circuit according to the present invention.

FIG. 11 is a circuit diagram showing a fifth embodiment of the decoding circuit according to the present invention.

[Explanation of symbols]

 CS0 to CS1: current switching circuit, AEF0 to AEF3: active emitter follower circuits DL10 to DL13: decode line DL0 to DL3: word driver drive line IEF: constant current source for decode line CL10 to CL13: decode line load capacitance Q6: discharge Pnp transistor

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroaki Minami 1-280, Higashi Koikeku, Kokubunji, Tokyo Stock Company, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Yoji Ii 1-280, Higashi Koikeku, Kokubunji, Tokyo Stock Company (72) Inventor Kenichi Ohata, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Takeshi Kusu, 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (6)

[Claims] 1. A current switching circuit comprising a current switch driven by an input code and an output circuit for receiving outputs of the current switch and generating a plurality of outputs of the same level, and a plurality of outputs for the plurality of outputs. In a decode circuit having a wired OR circuit connected to a decode line, a current supply source connected to each of the plurality of decode lines and a current for controlling the current of the current supply source with a voltage corresponding to the potential of the decode line. A decoding circuit provided with an active current source composed of a control circuit. 2. The decoding circuit according to claim 1, wherein:
The current supply source is composed of a multi-emitter transistor having a base connected to the first decode line and having first and second emitters, and the current control circuit has an emitter connected to the first emitter and a base. Is connected to the second emitter via a voltage shift circuit, and is composed of the multi-emitter transistor and a transistor of an opposite conductivity type. 3. The decoding circuit according to claim 1, wherein:
The current supply source includes a first transistor whose base is connected to the decode line, and the current control circuit has an emitter connected to the emitter of the first transistor and a base connected to the first decode line. A decoding circuit, which is connected through a voltage shift circuit and is composed of a transistor of a conductivity type opposite to that of the first transistor. 4. The decoding circuit according to claim 1, wherein:
The current control circuit includes a first transistor whose base is connected to the decode line through a voltage shift circuit, and the current supply source is connected to the emitter of the first transistor from one of the plurality of output circuits. Which is composed of a line that is formed on the emitter and base of the first transistor,
A decoding circuit configured to receive a decoding output signal having the same decoding logic level but different voltage levels. 5. The decoding circuit according to claim 1, wherein
The output circuit is driven by the output of the current switch, an emitter follower circuit, a first multi-emitter transistor in which the first output potential of the emitter follower circuit is applied to the base, and the first output potential are shifted. A second multi-emitter transistor having a second output potential applied to the base, the multi-emitter of the second multi-emitter transistor being connected to the first plurality of decode lines, and the current control circuit being the base. Is a first transistor connected to the first decode line, and the current supply source is a line connected to the emitter of the multi-emitter of the first multi-emitter transistor. Decode output with the same decode logic but different voltage levels to the emitter and base of the Decoding circuit, characterized in that issue is configured to be added. 6. The decoding circuit according to claim 1, wherein
A first emitter follower circuit in which the output circuit is driven by the output of the current switch; a first multi-emitter transistor in which the first output potential of the emitter follower circuit is applied to the base; and the first output potential And a second multi-emitter transistor having the output of the second emitter follower circuit applied to the base, and the second emitter follower circuit having the second output potential shifted by The multi-emitter of the multi-emitter transistor is connected to the plurality of decode lines, the current control circuit is composed of a first transistor whose base is connected to the decode line, and the current supply source is the first multi-emitter. In the line where the multi-emitter of the transistor is connected to the emitter of the first transistor Made is, above the emitter and the base of the first transistor, the decoding circuit, wherein a decode logic voltage level at the same constructed as different decode output signal is applied.