JPH06124227A - Method and system for eliminating page fault - Google Patents

Abstract

PURPOSE: To minimize the input/output transfer wait time at the time of removal of a page fault. CONSTITUTION: Information from an I/θ bus from a memory controller 102 is inputted to a controller and guided to a register 300 together with a page protection register 200. A tag file 302 is necessary only when a cache memory is used. A comparison with an array of tags is made and when the both match each other, an address in a main memory 104 is generated. When not, on the other hand, a request data line is read out of the memory 104 thorugh the I/θbus and used to fill the cache of the memory 104. A process requesting a critical data line is started after mask bits are sets to prevent a processor from waiting until all pages are transferred to a local memory.

Description

Description: FIELD OF THE INVENTION The present invention relates to a computer.
For more information on memory management systems, see page
Critical day that caused the page fault
When a critical data line is received, the pattern
The rest of the page is written to local memory.
Page fault to clear the page fault immediately without waiting for
Related to the paging system
It BACKGROUND OF THE INVENTION As is well known to those skilled in the art,
The icroprocessor depends on the processes running on it.
Local memos to store data needed and needed
Is equipped with Local memory is on-board
Cache or microprocessor local
Memory). Also, the main to improve performance
-A cache may be provided in the memory. Typical
The local memory contains data that contains more than one page of memory.
Data to a microprocessor for high-speed access
Operates according to a locally stored paging system
It In such paging systems, microp
The data requested by the processor (hereinafter, the requested data
Is stored in local memory at that time.
If not found in the page, a page fault is issued.
Using well-known page decapsulation technology
The page containing the requested data is read from the slow second memory.
Local memory. Write this page (I
I / O transfer), the process that requests the data
All pages including requested data are written to local memory
Is stopped by the microprocessor until
It In this way the process is typically stalled
Also known as storage latency. Storage wait time is when waiting for I / O data transfer.
Search to find the desired data in the space and in the second memory
Access the data in the second memory to include time
That is usually more than access to data in local memory
Much slower. When searching relatively for the second memory
Since the time is long, the waiting time for I / O data transfer is
It occupies a relatively small percentage of the time. For example, typical
Pages requested in case of memory transfer from different disk
Can take 20 ms to find on disk
But to transfer it after the requested page is found
Only takes 2 ms (4 kB is transferred at 2 MB / s)
Assuming that). As a result, the waiting time of the storage device
Prior art efforts to reduce the
To reduce the time needed to find a page
The emphasis has been on. However, random access
As the cost of memory (RAM) decreases
As it is used more frequently as the second memory
Is becoming. As known to those skilled in the art, R
AM has a relatively short access time, and as a result, the above-mentioned system
System I / O data transfer wait time is waiting for storage
The part that takes up time has become larger than before. Obey
To eliminate page faults most efficiently.
Waiting for this I / O output data transfer
Save even more time and minimize storage latency
Is desired. The problem of I / O data transfer latency has been identified.
To be treated by choosing the page size of
Often. Page size selection is complex and machine
Predictions on how to use the, main memo
Resize prediction and microprocessor size alignment
Based on various constraints in hardware design such as the number of connections
Is done. Generally, the larger the page size, the more
Only microprocessor and virtual memory software
Is smaller and reduces complexity. System main
Larger page size if memory is large enough
Is the amount of data retrieved for each page fault
The process from the second memory by increasing
Also reduce the number of page faults required to load.
You can However, the main memory is the application
Holds all page sets needed by the application
If the page size is not large enough,
System performance is degraded rather than improved.
It This result is systematic due to the large page size.
Used for processes and processes that run on
Available effective memory is reduced and individual I / O requests
Waiting time increases. For example, one 4 bar per page
A process that requires a data item
Double page size with constant resize
Then the process can keep it in memory at the same time
The number of data items is halved, and pages from the second memory
The time required to transfer is doubled. Transfer time required
The time needed to find the requested page in second memory
Much longer, poor performance due to page transfer latency.
The bottom is quite large. In this way, the paging system
The trade-off between usage time and seek time.
Often occurs. If you increase the transfer scale,
The number of seeks required to pull the data into local memory
Decreased, and as mentioned immediately above, the granularity,
Page size) is the storage latency, that is, page size
Extremely large shadow on the time required to resolve the default
May have an impact. Small pages can also be used
You can, but if you actually use a small page, memory
As usage decreases and the number of page faults increases
Used at the cost of saying. A part of a page can be replaced with another part of a page
Systems that can be accessed before the part are generally
Is not known. However, in the translation table
An IBM that can lock some parts of the
Systems such as the RS 6000 are known. In addition
A page fault with a partial transfer of data in the page.
Systems that can be solved at the same time are generally known.
Not not. Similar technology is hardware cache hierarchy
Has been used to address latency issues within
However, such an external memory and virtual memory system
The application to this is not known to the inventors of the present application.
Yes. Therefore, it is possible to reduce page faults.
Waiting for storage to minimize the time required to
It is desirable to reduce the time. Preferably this wait
The microprocessor saves time by parsing partial page transfers.
Sometimes desired to reduce page faults and achieve
Good In particular, the problem day that caused the page fault.
As soon as the data line is received in local memory
That is, the rest of the lines on the page are transferred
The microprocessor can resume processing without waiting.
It is desirable to be able to Also, Kurity
Cull line is sent out first, i.e. the requested page
Page fault before any other data line in
To transfer a critical data line
Therefore, the waiting time for input / output data transfer can be further shortened.
Is desired. The present invention meets these needs
It was done for good. The object of the present invention is to solve the above-mentioned problems,
How to eliminate the page fault that occurred
And system. SUMMARY OF THE INVENTION To meet the above needs, the present invention is a
The processor that caused the page fault.
Tikal Line is the local memory of the microprocessor.
The process can be resumed as soon as it is received by Mori.
Critical line priority paging system (cri
tical line first paging system). Obey
The microprocessor resolves the page fault.
The entire page including the requested line is transferred before
Waits until the microprocessor resumes processing
The data transfer can be completed in the meantime. Well
Also, the present invention provides a critical that causes a page fault.
Cull data lines with respect to other lines on a page
Ignore the order and take out the critical line.
Page faults as soon as they are transferred to local memory
Providing technology that enables us to resolve
Is. According to this method, N is
I / O data transfer wait time is almost N
It can be shortened by a factor. The advantages of the present invention reside in the microprocessor.
Page faults received during the running process
It is achieved according to a new method of erasing. In the present invention
So, before clearing the page fault, first micro
Entire page data from external storage to processor
Read out the microprocessor operation
There is no need to write to memory. In the present invention, the following
After transferring a portion of the page, including steps,
It is possible to resolve the fault. Add request data line with page fault
Confirm the reply. Operate from the store of the page containing the requested data line.
Start transfer to rating memory. Request data line from storage to operating
-Detect whether or not it has reached the memory. Request data line from storage to operating
・ The arrival at the memory is detected in the above detection step.
Stop the process until known. Requested data line reaches operating memory
If you do, all data lines on that page will be remembered
Process immediately without waiting for the device to transfer
continue. Preferably, the invention further comprises request data
Line (critical line) to other pages on the page
Transferring the data line before transferring.
In this way, the page fault is the first data
Resolve as soon as the line is received from the I / O device
Is also possible. Further, according to an embodiment of the present invention,
The starting step is the page protection register the page address.
Data is stored in the
It includes the following steps: Transfer from storage device to operating memory
The address of the page of data that is in the page protection register
Compared with the address stored in. If these addresses are the same, the
Data line currently being transferred to the operating memory
Set the mask bit of the page protection register corresponding to
To do. Of the page protection register corresponding to the requested data line
Check desired mask bit. When the desired mask bit is set, the requested data
Data line has arrived in operating memory.
And to detect. The deactivation step is the detection step and this desired mask
-It ends when it is judged that the bit should be set. This
This is because the microprocessor has the appropriate mask bits set.
Request data periodically until fixed
Or set the appropriate mask bits
As soon as the requested data line is
Instructs the microprocessor that it has arrived at Mori
Can be achieved by The present invention preferably records one page of data.
Operating memory to remember and multiple pages
Second storage device for storing data of the
And a memory controller
Implemented on a computer system consisting of
Is desirable. For operation, see Microprocessor
For each data line requested by the process
Access operating memory and requested
Pages containing data lines are operating notes
If not present, receives page fault. This
If you receive a page fault like
The black processor is responsible for causing the page fault.
Check the address of the request data line, then enter the second
Request data from storage device to operating memory
Start the transfer of the page containing the line. Then the memory
-The controller ensures that the requested data line is from the storage
Detects when it has reached operating memory
And the requested data line is operated from the second storage device.
To the microprocessor until it reaches the
To stop the process of Request data line
Once received, the microprocessor processes the process.
To resume. In other words, the microprocessor
All data lines in the storage
The processing operation is continued without waiting for the transmission. In one embodiment of the present invention, a microprobe
The processor sends the requested data line to the other licenses on the page.
Transfer to operating memory before in
Means are provided for instructing the second storage device. sand
That is, the microprocessor pulls a page fault.
Raise the critical line you raised to another line on the page.
Instruct the second storage device to transfer before in
It Preferably, the memory controller is
.A page for storing the address of the page containing the line
Required by the protection register and microprocessor
Address stored in the page protection register.
It consists of a means to compare Comparators are
If the addresses match, STAL is sent to the microprocessor.
The L (stop) signal is output. The page protection register is
More preferably, multiple masks, one for each line of the page
Has a bit, and the comparison means further includes the page address described above.
Operating system from the storage device
Page protection for data lines being transferred to memory
Set the mask bit in the register. Request data file
If the mask bit for IN is set, STAL
The L signal turns off. As described above, during the I / O transfer, the second record
The data line read from the storage device is
Has an address that matches the address stored in the register
And page protection register corresponding to the requested data line
If the desired mask bit of
・ The controller is a microprocessor-based process
Stop processing. The microprocessor is
The desired mask for the page protection register associated with the line
Continue processing only if bit is set
can do. BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on Examples.
It will be described in detail with reference to FIGS. To those skilled in the art
Therefore, in the present specification in relation to these drawings,
The description provided is for illustrative purposes only.
It's not meant to limit the light at all
Is self-evident. The present invention solves the aforementioned storage latency problem.
It is something to erase. I / O links are typically
File in response to a page fault.
It doesn't support and so pages can be transferred at once
Cannot be performed and the data transmission itself will interfere with page writing.
It may cause a bruise. The present invention ensures that the entire page is transferred
The required data without the microprocessor waiting
To be able to immediately start processing
This obviates this hindrance. Hereafter
1 to 3 show a system and method for achieving the object of FIG.
It will be described based on. In a typical memory management system,
There is some software overhead for each page fault.
It involves bar heads and some hardware latency.
Part of the hardware wait time is I / O data transfer (link
) Waiting time, which is a part of the total data transfer time
There is. For example, a 4kB page and a 100MB link
In case of overhead, I / O data transfer
The waiting time is about 40 μs. However, each 4kB
A page is typically 64 data lines with 64 bytes
As it is configured, the first data line is the local
If the processor is ready to run as soon as
For example, the delay data transfer part is 1 microsecond (μs).
It can be shortened to (40/64 μs). The Criti that caused the page fault
As soon as the Cull Data line is returned,
A memory system that the sessa can execute is shown in FIG. Ma
The icroprocessor 100 processes the process in a typical way.
Process and request the data that the process needs. Special
In addition, the microprocessor 100 is connected via the I / O bus.
Communicates with the memory controller 102 to require the process.
The required data is stored in the local (main) memory 104.
Check whether the data is stored in the memory 104.
For example, the data is sent to the microprocessor via the I / O bus.
Returned to service 100. In this case, the microprocessor 1
00 continues processing. On the other hand, the requested data
Go to the current page stored in in-memory 104
For example, the virtual memory inside the microprocessor 100
A page fault is detected by the software. Ma
Icroprocessor 100 selects the physical memory page
To allocate a virtual page (instantiate) and start I / O
To fill the physical page with valid data.
Then, the processing is interrupted. Therefore, the memory controller 1
02 does not need to know anything about virtual addresses. Only
While described below, a microprocessor
100, request data arrives from the second storage device 106
Until the page is stored in the main memory 104
That Le Lines should be considered invalid
Can be notified to the memory controller 102
It Of course, in order to further improve the processing efficiency,
A cache may be provided in the main memory 104, or
Memory controller 102 with cache controller
May be provided. Of a typical cache memory system
If the memory controller 102 is the main memory
A tag file for identifying the data stored in 104.
Or other means similar thereto. Tag
Files, those tag files are
It is preferable to store it on the controller 102 itself.
The memory controller 10
2 is the main memory 104 (or
Microprocessor until its cache) is filled
Given the ability to shut down 100. Also memory
・ Maintaining I / O coherency in the controller 102
Clear the cache of main memory 104 as
It can also have a role of (flush). Only
However, the present invention uses a small number of special tag lines.
Memo by adding to Mori Controller 102
Main memory 104 (or its memory)
As soon as the appropriate line in
When the microprocessor 100 can be started
I found that. In other words, according to the invention
So that the system maintains granularity at the page level.
Page faults are line-based
It can be solved with a scan. As shown in FIG. 2, a memory controller
The special tag line above for 102 is a separate
It may be provided in the image protection register 200. Page protection
The register 200 is currently in the main memory 104.
Memory controller 10 for storing page addresses
2 Special tag registers inside and stored in them
Indicates which line of the page is valid. Bae
The tag line stored in the page protection register 200 is
The only memory location in main memory 104,
A tag / memory that points to a physical page (or line)
Consists of position bits. In other words, the tag / memory location
Is currently in the microprocessor's local memory
Point to the page at. Also, page protection register 2
00 contains which data line in which stored page
The mask, which is a bitmap showing whether the
It may be provided. According to the invention, this mask is I / O
Available for each data line when data is input from the system
Used to set the effect bit. Page address
Page stored in the page protection register 200.
Match the dress and its valid bit is not set.
In this case, the microprocessor 100 is the main memory 10
4 or trying to access the line in its cache
Then, the memory controller 102 becomes a microprocessor.
The function of the chair 100 is stopped. This outage is normal
Microprocessor 1 because it is part of a memory cycle
00 maps the requested data from the fault page
And continue operation as soon as I / O is started.
This allows you to operate in parallel with I / O, and
For pages with data lines, input / output data transfer
Reduces the effect of waiting time for sending by a factor close to N
Can be made. FIG. 3 shows the memory controller 1 of the present invention.
No. 02 is shown in more detail. Illustration
Address and data information from the I / 0 bus as
Enters the memory controller 102 and enters the page protection level.
I / O register 300 and tag unit with register 200
To the file 302. As above, Tag Phi
In the memory 302, the memory controller 102 caches
Only needed if memory is used. Tag file
At 302, the incoming address is a prior art message.
Similar to the Mori controller, compared to an array of tags,
If the two match, access the stored data or
Internal to main memory 104 to modify stored data
Is generated. If the two do not match,
The data request line is transferred to the main memory 104 via the I / O bus.
From the main memory 104 cache
Used to fill. In addition, the memory controller of the present invention
The tracker 102 is written to the main memory 104.
To perform directional access using write-through method
Both are possible. Thus, whether the microprocessor 100
From the memory request of the present invention.
When it arrives at the controller 102, the request goes through two passes.
Sent through the road. The normal route is to request the tag file
File 302 and check for any appropriate action.
It is a route to generate. On the other hand, according to the present invention,
For example, if the incoming address stored in the I / O register 300 is
Address stored in the page protection register 200.
Comparing the storage position bit and mask bit with the comparator 304
A new route is established. The incoming address is
If the match / storage bit matches, the request
Data in the pages stored in the main memory 104.
Is informed. On the other hand, the requested data
The valid bit in the mask corresponding to the line is set
If not confirmed, the comparator 304 outputs the tag file.
Override output of file 302 with STALL command
To do. This STALL command is, for example, an AND game.
Tag file 302
The output from the microprocessor 100 is the main memo
To not allow access to resource 104
Can be used for. This outage is due to I / O link
It lasts until cleared. However, data transfer
During this period, the incoming address of I / O register 300 is
And the tag / storage location bit in the page protection register 200.
If matched, the mask corresponding to the incoming data line
Valid bit of is set. This allows the memory
Stopped function depending on the output of the controller 102
Are all cleared and the microprocessor 100 immediately
(Ie before the rest of the page is transferred),
You can access the data line. the above
Is compared with the I / O register 300 and the page protection register.
Comparing the 200 high-order bits as address bits,
After that, it is compared with the mask in the page protection register 20.
Index to the lower bit of I / O register 300 for
It can be easily done by attaching. In one embodiment of the invention, the microprobe
The processor 100 is not limited to page addresses
The critical data error that caused the fault
Also check the inn's address. As a result,
The sessa 100 will transfer another line of the requested page.
Note the critical data line before
Request to external memory 106 to write to memory 104
be able to. In other words, the microprocessor 10
0 is the line that causes a page fault
You can check up to
I / O 100 or memory controller 102
Critical data lines in random order during O memory transfer
Instructing the external memory 106 to write at the same time
it can. This causes the microprocessor 100 to
Other data in the page containing the data is written
Read critical data before
Become. This "critical line priority" method is
Page protection register 200 requested new page
The I / O location bit and then I / O is complete.
It is performed by continuing the processing as if it were performed. Yo
The microprocessor 100 is parallel with the memory transfer.
And the critical data line is the main
Processing can continue as soon as it is received by the memory 104.
it can. As mentioned above, this process
Simple by using the mask bit corresponding to the in
Singularized, which corresponds to the requested data line
You can monitor the mask bit until it is set
It When this mask bit is set,
After the cessation of the cessor function is finished, the processing can be restarted.
It As shown in the figure, in this embodiment,
The output goes through the memory controller 102 and
It is controlled by the processor 100. Of course memory
-The controller 102 controls all input / output transfers.
It is also possible to change it. In addition, the present invention is
After the data line requested by the
To have a memory to save certain masks
It can be changed. This mask is micro
Processor 100 will again access the data line.
You can recover when you try. That is,
The request data line is immediately accessible
So, it will be set immediately. As shown in FIG. 3, the input / output is a memory controller.
This is done via the trolley 102. However,
Ming is a snooping (s
nooping) can be implemented using a cache controller
Both are possible. The output of the I / O register 300 is
It is not necessary to directly input to the comparator 304.
Data line and the corresponding mask bit is set
Comparator after checking to see if
Memory control according to STALL output from 304
It may be made to pass through the roller 102. According to the present invention, valid bits are applied to all lines.
It can also be designed to be provided. That is, the tag
Bits in memory controller 102 tag file
It is also possible to provide each line. However,
Such a configuration requires more silicon
The size and cost of the memory controller 102
It is thought that it will increase unnecessarily. In contrast to this
By comparison, the present invention requires less virtual memory hardware.
Greater granularity for page protection, not necessary
Can be secured. Thus, the present invention is not
One advantage over the other is that it is relatively small to implement.
This means that only a small chip area is required. example
Access each data line until I / O starts
Add a bit to indicate that should be stopped
It is possible to do so, but then the memory chip
Now we have to add another bit to each tag.
Become The second advantage of the present invention is that the page protection register 2
00 is provided locally, masking memory
・ Only one or two access to the controller 102
The point is that it can be set. On the other hand
And using a normal tag, the valid bit is
A separate operation is required to set each bird. In an embodiment of the present invention substantially the invention
Many other changes without departing from new disclosures and advantages.
It is easy for a person skilled in the art that further embodiments are possible.
It can be understood. For example, the method and hardware used in the present invention.
Ware references I / O locked data lines
To generate an out of band I / O request
To allow, or segmented paging (page requests
Cancel all the way to the middle and pollute the dirty line
If so, refer the entire page to main memory 104.
Paging) without rewriting)
You can also do it. The present invention also relates to a memory controller
102 bears most of the burden on the virtual memory system.
It can be extended to allow
The memory controller 102 becomes more complex.
Furthermore, when the access time of the second storage device is short (R
The best results are obtained using the AM, etc.)
Shall be implemented by the second storage device of all forms.
Is possible. Therefore, the various modifications described above are not
The present invention is included in the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a page fault resolution system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a page protection register used in an embodiment of the present invention. FIG. 3 is a schematic diagram of a memory controller used in an embodiment of the present invention. [Explanation of Codes] 100: Microprocessor 102: Memory Controller 104: Main Memory 300: Register 302: Tag File 304: Comparator 306: AND Circuit

Claims (1)

Claims: Pages received during the processing operation of the microprocessor.
A method of clearing a fault from external storage into the microprocessor's operating memory prior to the first reading of a new page of data, wherein the requested data causing the page fault
Determining the address of the line, initiating a transfer of the page containing the requested data line from the storage device to the operating memory, the requested data line arriving from the storage device to the operating memory Detect whether the requested data line is detected, do not wait until all the data lines have been transferred from the storage device, and do not wait until the requested data line arrives. A method for resolving a page fault including continuing the process. In a computer system that performs a certain processing operation, an operating memory that stores at least one page of data, a second storage device that stores a plurality of pages of data, a microprocessor that executes the processing, and the microprocessor Accesses the operating memory for each data line requested by the process, and the page containing the requested data line is not present in the operating memory,
Receiving a page fault, where upon receipt of a page fault, the microprocessor determines the address of the requested data line causing the page fault,
Initiating a transfer of the page containing the requested data line from the second storage device to the operating memory, detecting whether the requested data line has arrived at the operating memory. , A page having a memory controller that stops the process until it arrives and starts the process when it arrives without waiting for all the data lines of the page to be transferred to the second storage device.・ Fault elimination system.