JPH0612156A - Momentary power interruption protecting device for computer - Google Patents

Abstract

PURPOSE:To obtain the momentary power interruption protecting device for the computer which protects the contents of a memory and continuously perform processing even after a recovery from a power interruption even if the electric power supply from a battery is momentarily broken during operation. CONSTITUTION:This device is provided with a voltage drop detecting circuit 4 which detects the momentary break of the electric power supply from the battery during the operation and outputs a request signal for DMA while the momentary break is detected and a DMA controller 5 which refreshes a memory 9 according to the request signal outputted from this voltage drop detecting circuit 4 and also outputs an acknowledgement signal for DMA. Further, the device is equipped with a system clock control circuit 7 which stops the oscillation of a clock according to the request signal outputted from the voltage drop detecting circuit 4 and the acknowledgement signal outputted from the DMA controller 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a battery-powered computer, and more particularly, it protects the contents of the memory to recover from a power failure when the power supply from the battery is interrupted during operation. The present invention relates to a computer instantaneous power failure protection device capable of continuously performing processing afterward.

[0002]

2. Description of the Related Art Recently, portable devices equipped with a small computer have been provided as seen in laptop personal computers and word processors. Since these devices cannot be used by connecting a cord to a commercial power source as in the conventional case, batteries are used as a power source.

[0003]

In such a small-sized computer using a battery as a power source, the battery may be impacted during operation and the power supply to each circuit may be interrupted momentarily. Therefore, conventionally, a large-capacity capacitor that can supply power during a momentary interruption has been connected so that the computer continues to operate during the momentary interruption.

That is, the capacity C of the capacitor for supplying the necessary power at the time of momentary interruption is

[0005]

## EQU1 ## C = I.times.t / .DELTA.V where .DELTA.V is the voltage drop allowed during a momentary interruption, t is the momentary interruption time, and I is the current consumption of the system.

Assuming that ΔV = 0.5 V, t = 50 ms, I
= 200 mA, the capacitance C of the capacitor was C = 50 × 200 / 0.5 = 20,000 μF, which was very large and was difficult to mount with a small computer.

Even if it is composed of only a CMOS IC, power consumption is large when a clock is input, and a similar capacity is required.

In the present invention, attention is paid to the fact that the CMOS IC consumes extremely low power if it does not perform a switching operation, so that it is possible to supply power at the time of an instantaneous power failure with a small-capacity capacitor, and a refresh operation is required. It is an object of the present invention to provide a computer instantaneous power failure protection device capable of retaining the contents of various memories.

[0009]

In order to solve the above problems, an instantaneous power failure protection device for a computer according to the present invention detects an instantaneous interruption of power supply from a battery during operation in a computer powered by a battery. At the same time, the voltage drop detection circuit that outputs the DMA request signal during the detection of the instantaneous interruption, the memory refresh operation based on the request signal output from the voltage drop detection circuit, and the DMA acknowledge signal are performed. And a system clock control circuit for stopping clock oscillation based on a request signal output from the voltage drop detection circuit and an acknowledge signal output from the DMA controller.

[0010]

The voltage drop detection circuit detects a momentary interruption of the power supply from the battery during operation, and upon detecting the momentary interruption, outputs the DMA request signal during the detection period.

The DMA controller performs a memory refresh operation based on the request signal output from the voltage drop detection circuit and outputs a DMA acknowledge signal.

On the other hand, the system clock control circuit, based on the request signal output from the voltage drop detection circuit and the acknowledge signal output from the DMA controller,
Stop clock oscillation. As a result, even if the power supply from the battery is interrupted during operation, the contents of the memory are protected and the processing can be continued even after the power failure is recovered. Also, at the time of momentary interruption, all clocks are stopped, so there is no device that is switching, and the entire CM
When configured with an OS / IC, the current consumption can be suppressed to about one hundredth of that during operation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an electrical configuration of a computer instantaneous power failure protection device according to the present invention.

In the figure, the output of the battery 1 which is the power source of the computer is supplied to each circuit block through the power supply circuit 2 and the capacitor 3 for momentary interruption protection which becomes the power source when the battery 1 is momentarily interrupted. There is. In addition, the output of the battery 1 is a voltage drop detection circuit 4 that detects a voltage drop due to an instantaneous interruption of the battery 1.
The output of the voltage drop detection circuit 4 is
(Direct Memory Access) Controller 5 and system clock control circuit 7 via AND circuit 6.

The voltage drop detection circuit 4 detects a voltage drop by detecting a voltage drop when the battery 1 is momentarily cut due to a shock or the like, and a DMA request signal (DRQ signal) during the detection. Is output.

The DMA controller 5 receives the DRQ signal from the voltage drop detection circuit 4 and enters a DMA cycle, and at the same time, generates a DMA acknowledge signal (ACK signal), and outputs the acknowledge signal via the AND circuit 6 to the system clock. Output to the control circuit 7 and the like. Also, DMA
During the cycle, the DMA controller 5 and the memory 9 are directly connected by the address bus 11.

The system clock control circuit 7 supplies the DMA clock to the DMA controller 5 during operation and the CPU 8
CPU clocks are output to the DRQ signal from the voltage drop detection circuit 4 and the DMA controller 5 respectively.
When it receives the acknowledge signal from, the clock oscillation is stopped.

A memory 9 and an input / output control circuit 10 are bidirectionally connected to the CPU 8. The power supply voltage Vcc from the power supply circuit 2 is supplied to each of these circuit blocks 5, 7, 8, 9, and 10.

When the DMA controller 5 receives the DRQ signal from the voltage drop detecting circuit 4, the data bus, address bus, control bus, etc. of the CPU 8 are set to high impedance, the CPU 8 is disconnected from these buses, and the DMA controller 5 and the memory are separated. 9 is directly connected to the address bus 11 to refresh the memory 9.

Next, the operation of the instantaneous power failure protection device having the above configuration will be described.

When the computer is operating, the power supplied from the battery 1 is supplied to each circuit block 5, 7, through the power supply circuit 2.
Are supplied to the circuit blocks 5, 9, and 10.
7, 8, 9, and 10 operate by receiving power supply from the battery 1.

During such an operation, if the battery 1 is momentarily disconnected due to a shock or the like, each circuit block 5, 7,
After that, the power supplies 8, 9 and 10 are continuously supplied with power from the capacitor 3. At this time, the voltage drop detection circuit 4
When the instantaneous interruption of the battery 1 is detected by the voltage drop, the DRQ signal is supplied to the DMA controller 5 and one input of the AND circuit 6 during the detection period.

When the DMA controller 5 receives the DRQ signal from the voltage drop detection circuit 4, it enters a DMA cycle. That is, the data bus, address bus, control bus, etc. of the CPU 8 are set to high impedance,
CPU8 is disconnected from these buses, and DMA
The controller 5 and the memory 9 are directly connected by the address bus 11. As a result, the DMA controller 5 and the memory 9 enter the refresh cycle, and the refresh operation of the memory 9 is performed. As a result, even if the power supply from the battery 1 is momentarily cut off during operation, the contents of the memory 9 are retained, and continuous processing is possible even after the power failure is restored.

At this time, the DMA controller 5
A DMA acknowledge signal is generated, and this acknowledge signal is supplied to the other input of the AND circuit 6. The AND circuit 6 outputs an operation stop signal to the system clock control circuit 7 when the DRQ signal and the acknowledge signal are introduced to both inputs. The system clock control circuit 7 stops the clock oscillation based on this operation stop signal.

That is, when the system clock control circuit 7 is stopped, all clocks are stopped, and there is no device for switching. Therefore, when the whole is composed of CMOS IC, the current consumption is It can be suppressed to about one hundredth of that during operation.

Here, the time from the voltage stop to the refresh operation is 1 μs, and the current consumption during that time is 200 m.
A, the clock stop period is 50 μs, and the current consumption during that period is 500 μA, the capacitance C of the capacitor 3 for compensating for the instantaneous interruption of 50 ms is about 100 μF.

After that, when the instantaneous interruption is released, the output of the DRQ signal from the voltage drop detection circuit 4 is stopped. As a result, the system clock control circuit 7 starts clock oscillation and outputs the clock to the CPU 8. Also, DM
The A controller 5 releases the DMA cycle and
The connection between the controller 5 and the memory 9 via the address bus 11 is released. As a result, the CPU 9 is connected to each bus again, so that the CPU 8 can continue to operate again.

FIG. 2 is an explanatory diagram showing the flow of the operation of the main part of the above-mentioned instantaneous power failure protection device.

As described above, according to the momentary power failure protection device of the present invention, the contents of the memory 9 are retained when the battery 1 is momentarily interrupted, and the capacity of the capacitor 3 for momentary interruption protection is also 100.
Since a capacitor with a small capacity of μF is enough, the capacitor 3
Can be downsized.

[0031]

The computer instantaneous power failure protection device according to the present invention detects a momentary interruption of the power supply from the battery during operation, and outputs a DMA request signal during the detection of the momentary interruption. The voltage drop detection circuit, the DMA controller that performs the refresh operation of the memory based on the request signal output from the voltage drop detection circuit, and outputs the DMA acknowledge signal, the request signal output from the voltage drop detection circuit, and the DMA The system clock control circuit that stops the oscillation of the clock based on the acknowledge signal output from the controller is provided. The capacity of the capacitor may be small, and the size of the capacitor can be reduced. Further, by performing the refresh operation, it is possible to configure the computer with a large-capacity and low-cost D-RAM or pseudo S-RAM.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a computer instantaneous power failure protection device according to the present invention.

FIG. 2 is an explanatory diagram showing a flow of an operation of a main part of the instantaneous power failure protection device.

[Explanation of symbols]

 1 Battery 3 Capacitor 4 Voltage Drop Detection Circuit 5 DMA Controller 7 System Clock Control Circuit 9 Memory

Claims (1)

[Claims] 1. A battery-powered computer, comprising: a voltage drop detection circuit that detects a momentary interruption of power supply from a battery during operation and outputs a DMA request signal during detection of the momentary interruption. , A DMA controller that performs a memory refresh operation based on a request signal output from the voltage drop detection circuit and outputs a DMA acknowledge signal, a request signal output from the voltage drop detection circuit, and the D controller.
An instantaneous power failure protection device for a computer, comprising: a system clock control circuit for stopping clock oscillation based on an acknowledge signal output from the MA controller.