JPH06120522A - Semiconductor device for image processing - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device for image processing, which is formed small its occupation area on a chip and is easily increased its integration scale. CONSTITUTION:A semiconductor device for image processing has resonance tunnel transistors, which control the ratio of a resonance tunnel current, which is made to flow between an N-type ohmic electrode 109 and an N-type ohmic electrode 110, to a non-resonance tunnel current, which is made to flow between the electrodes 109 and 110, by changing the widths of deflection layers by an applying voltage to a control electrode 111, and the device s constituted into a structure wherein a plurality of pieces of these resonance tunnel transistors are coupled with each other in a reticular form.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing semiconductor device for performing image processing using a neural network, and more particularly to a circuit structure of an analog LSI and a structure of functional elements necessary for the circuit structure.

[0002]

2. Description of the Related Art Initial visual problems, which are positioned as preprocessing for image processing or image recognition technology, include surface interpolation, edge detection, shape restoration from shadows, velocity field estimation, color estimation, and structure from motion. There is an estimation. A method has been proposed in which these problems are formulated as optimization problems and approximately solved by an analog electronic circuit composed of a resistance network from the viewpoint of a neural network [Reference:
C. Mead, Analog VLSI and Neural Systems, Addison-Weis
ley, 1989.CAMead and MA Mahowald, "A Silicon Model
of Early Visual Processing, "Neural Networks, vol.
1, pp.91-97,1988.J.Hutchinson, C.Koch, J.Luo, and C.Me
ad, "Computing Motion Using Analog and Binary Resis
tive Networks, "IEEE Computer, vol.21, pp.52-63,1988.
Such].

A "line process" for modeling discontinuity of image data has been proposed [S. Geman and D. Ge.
man, "Stochastic Relaxation, Gibbs Distributions, a
nd the Bayesian Resolution of Images, "IEEE Trans.
Pattern Analysis and Machne Intelligence, vol.PAMI
-6, pp.721-741, 1984]. Furthermore, a technology has been proposed that realizes this on an analog electronic circuit with a "resistive fuse element" [JG Harris, C. Koch, and J. Luo, "A Two-D
imensional Analog VLSI Circuit for Detecting Disco
ntinuities in Early Vision, "Science, vol.248, pp.12
09-1211, 1990.]. In this circuit, data processing is performed in parallel in the vicinity of each pixel, so that real-world image data (several hundreds × several hundred pixels) can be processed in real time (about several microseconds).

The above contents are as follows: [Noboru Sonehara, "Processing of image information by neural network (4) -Realization of visual chip by analog VLSI-", Image Lab:
Vol. 3, No. 4, PP.76-80 (1992)]. Here, based on this commentary paper by Sonehara, a method of restoring image data containing noise by an analog neural network incorporating the resistive fuse element will be described.

This problem is formulated by minimizing a quadratic energy function as shown in the following mathematical expression 1 by using a constraint condition that surfaces other than discontinuous surfaces are smooth.

[0006]

[Equation 1]

Where d _i is the observation data at pixel i, f
_i is the estimated data at pixel i, σ ² is the variance of noise to be estimated, α and λ are free parameters, and h _i is a line process. The first term of the above equation (1) requires that the observation data d _i and the estimation data f _i be close to each other. The second term is a term representing the smoothness which requires that two adjacent values take close values to each other when there is no discontinuity in the line process h _i = 0. The third term is an increase in the cost of firing the line process, and whether or not the line process is fired is determined by the balance between the second term and the third term. That is, λ represents the degree of smoothness, and α is a scale that distinguishes noise from discontinuity in the original image.

The above equation (1) can be solved by examining the steady-state voltage distribution of the resistance network shown in FIG. Here, the conductance g (= 1
The resistance element r having / 2σ ² ) must have a non-linear characteristic as shown in FIG. That is, when the voltage difference ΔV = | f _i −f _i−1 | at both ends is less than √ (α / λ), it acts as a linear resistance of λ corresponding to the conductance g _(m) (line process h _i = 0). If not, the element is such that the connection is broken (line process h _i = 1).
This is called an ideal resistance fuse element R.

However, in the resistance network circuit shown in FIGS. 6 and 7, generally, the resistance is stabilized in the state of a local solution (so-called local minimum) depending on the initial condition,
The minimization of the energy function shown in equation (1) cannot always be achieved. Therefore, a method has been proposed in which a line process is made to correspond to a neuron having a sigmoid-type input / output function and the gain of the sigmoid function is changed to perform annealing in the mean-field approximation theory to obtain a suboptimal solution [JJ Hopfield, "Neurons with Graded Response Ha
ve Collective Computational Properties Like Those
of Two-state Neurons, "Proc.Natl.Acad.Sci.USA, vol.
81, pp. 3088-3092, 1984.].

In this case, when the internal state variable of the neuron corresponding to the line process h _i is m _i , the following equation 2 is obtained.

[0011]

[Equation 2]

Here, T is a temperature parameter. Since the neuron state takes an analog value, the energy function is the above equation (1) to which the following equation 3 is added. Note that C _G is a coefficient.

[0013]

[Equation 3]

The dynamics of the network is expressed by Equation 4 below.

[Equation 4]

Since the stable state of the change of the internal state variables m _i is the following Equation 5,

[0016]

[Equation 5]

The following expression 6 is obtained.

[0018]

[Equation 6]

Therefore, the required current-voltage (I-ΔV) characteristic of the resistance fuse element is expressed by the following equation (7).

[0020]

[Equation 7]

FIG. 8 shows this characteristic as a function of the temperature parameter T. The analog resistance fuse is
When the temperature parameter T is large, the characteristic of a normal linear resistance is shown, and when the temperature parameter T becomes small and approaches 0, it becomes close to the characteristic of the ideal resistance fuse element shown in FIG.

Regarding the method of realizing the above resistance fuse,
Reference [H. Lee and P. Yu, "CMOS Resistive Fuse Circuit
s, "in Symposium on VLSI Circuts, pp.109-110, 1991]
An example in which an analog CMOS circuit is used has been reported. Although this report proposes three types of circuits, the simplest circuit showing the principle is shown in FIG. This circuit includes a differential pair including transistors M1 to M5, and transistors M6 and M7 that operate as resistors.

In such a structure, first, the saturation currents of the transistors M4 and M5 are set to be slightly larger than I / 2, and the transistors M6 and M7 are made conductive in the triode region in a state close to the balanced state. And act as a linear resistor.
When the voltage between the first node N1 and the second node N2 increases, the balance of the differential pair is lost and the transistor M
6 or the transistor M7 becomes non-conductive, and the characteristics of the fuse resistance element can be realized.

In the circuit of FIG. 9, the resistance value is the first node N.
The transistor M6 and the transistor M6 have the drawback that they are affected by the absolute potentials of the first and second nodes N2.
An improved type in which another MOS transistor for determining the resistance value between the MOS transistor and the MOS transistor and three transistors for controlling the MOS transistor are added is proposed in the same document. As a result, the resistance value and the voltage difference at which the resistance is cut can be changed independently, and the characteristics close to those of the ideal resistance fuse shown in FIG. 7 can be realized.

[0025]

The CMOS described above
In the method of realizing the resistance fuse by the circuit, since it is necessary to combine 7 to 11 transistors in order to obtain the resistance fuse characteristics, there is a problem that the area occupied on the chip becomes large and high integration is difficult. . Since the analog circuit cannot receive the benefit of the submicron process technology based on the ordinary digital technology represented by the large-capacity DRAM, the resistance fuse circuit specifically requires an area of about 30 to 50 microns square. An actual chip needs a circuit for inputting / outputting data to / from each pixel, and more desirably, a photoelectric conversion element (photoreceptor or light emitting element) is provided for each pixel on the chip in order to perform data processing at high speed and with high efficiency. It is preferable that the data are input and output in parallel by arranging them in the same manner. Since it is desirable for the photoreceptor area to be large to increase the efficiency of data collection, it is desirable for the resistive fuse element or circuit to be as small as possible. With the above-mentioned configuration method, when the above-described resistive fuse circuit is used, it is estimated that the integration of about 100 × 100 pixels is the limit, and real-world pixel processing is difficult.

Therefore, the present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is to provide an image processing semiconductor device which occupies a small area on a chip and can be easily highly integrated. To do.

[0027]

In order to achieve such an object, the present invention utilizes the negative resistance characteristic due to the resonance tunnel effect. More specifically, the junction type FET structure is used to control the peak (resonant tunnel) current having a negative resistance characteristic, and simultaneously control the ohmic current due to the normal current flowing in parallel to this device to be approximately linear. The resistance characteristic to the ideal resistance fuse characteristic are continuously obtained.

[0028]

The semiconductor device for image processing according to the present invention can continuously generate an approximately linear resistance characteristic to an ideal resistance fuse characteristic with a single control voltage (gate voltage of the junction type FET). Further, since the above functions can be realized by a single device, the area occupied on the chip can be made extremely small (several square microns or less).

[0029]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of a resistance fuse element showing a configuration of a first embodiment of an image processing semiconductor device according to the present invention. In the figure, 101 is semi-insulating GaAs.
A substrate 102 is an n ⁺ -GaAs buffer layer having a thickness of about 3000 Å doped with Si of 2 × 10 ¹⁸ cm ⁻³ , and 103 is a thickness of 500 doped with Si of 5 × 10 ¹⁷ cm ⁻³ , for example.
Å n-GaAs layer, 104 is a first barrier layer made of undoped AlAs having a thickness of 20 Å, 105 is a quantum well layer made of undoped GaAs having a thickness of 50 Å, and 106 is also made of undoped AlAs having a thickness of 20 Å And the second barrier layer 107 is, for example, 5 × 10 ¹⁷ cm
^-3 Si-doped n-GaAs layer 500 Å thick,
Reference numeral 108 denotes, for example, an n ⁺ -GaAs contact layer having a thickness of 3000 Å doped with 2 × 10 ¹⁸ cm ^-3 of Si.

Crystal growth is performed by, for example, a molecular beam epitaxy method, and after the growth, a resonance tunnel diode having a two-step mesa structure is formed by mesa etching as shown in the figure.
Reference numerals 109 and 110 denote n-ohmic electrodes, respectively. The n-ohmic electrodes 109 and 110 are formed by vapor deposition, lift-off and alloying of AuGe / Ni, for example. 111 is Ni / Zn / Au / Ti
/ Au (eg 50Å / 160Å / 1000Å respectively
/ 1000Å / 1000Å) is deposited, for example about 400
A control electrode alloyed at ℃, 112 is the control electrode 11
It is a p ⁺ region formed by Zn diffused from 1. The n-ohmic electrode 109 and the n-ohmic electrode 110 can be alloyed and the control electrode 111 can be alloyed at the same time. The size of this emitter (the length of its short side in the case of a rectangle, its diameter in the case of a circle) is made sufficiently small,
The depletion layer from the control electrode 111 can close the current path. In the case of a circular shape, for example, the diameter may be about 0.5 μm. Reference numeral 113 is a high resistance layer formed by ion implantation of H ^+, for example. Although the high resistance layer 113 is not essential to the present invention, it is provided for the purpose of eliminating unnecessary capacitance for speeding up and reducing an unnecessary junction area which causes a gate leak current.

In such a structure, the AlAs barrier layer 104, the GaAs quantum well layer 105, and the AlAs barrier layer 106 form a well-known resonant tunnel diode. This diode has a current-voltage (IV) characteristic having a negative resistance as shown in FIG. 2 because only electrons whose energy matches the resonance level flow. When a voltage is applied to the control electrode 111 with this structure, the size of the depletion layer of the pn junction changes depending on whether the voltage is positive or negative. According to this, the area of the diode changes, and the current changes.

The current-voltage characteristics of the element thus constructed are shown in FIG. 3 as a function of the control voltage. In the figure, only the first quadrant is shown, and when V <0, it is symmetrical with respect to the origin. When the control voltage is changed as shown in the figure, not only the region 1 in which the entire IV characteristic changes in proportion but also the region 2 in which the current change in the valley portion is large can be obtained.
This region 2 is due to (a) a change in resonance energy due to band bending near the control electrode and (b) destruction of the resonance tunnel structure due to diffusion of Zn. The above (a) is
With the emitter mesa, it means that the resonance energy changes in the in-plane direction between the emitter electrode and the control electrode to blur the resonance point. Regarding (b) above,
It is understood as follows. As is well known, Zn diffusion destroys the AlAs / GaAs superlattice (mixing). Since the p region 112 is formed by Zn diffusion during alloying, AlAs / GaAs / A in this portion is formed.
The lAs resonance tunnel structure is destroyed (mixed crystal). Therefore, when the width of the depletion layer is reduced and the amount of current is increased, the non-resonant current passing through this mixed crystal region increases and the current in the valley portion (valley current) increases. Due to these effects, the IV characteristic of this element can be changed from the ohmic characteristic to the strong negative resistance characteristic by the control voltage as shown in FIG. Further, in the area 1 where the current changes, the resistance near the origin can be freely adjusted by the control voltage. Therefore, it is possible to realize the minimum energy state while controlling the parameter T described in the related art by moving the control voltage in the region 2 from the positive direction to the negative direction, and then adjust λ corresponding to the conductance in the region 1. is there. Due to these characteristics, this element can be used as a resistance fuse element of an image processing apparatus. Therefore, an image processing semiconductor device can be formed by connecting the elements in a mesh shape as described in the prior art. Since this device realizes the same function as that of the resistance fuse element which has conventionally required 7 to 11 transistors by one element, the area occupied by each pixel can be made extremely small, and high integration of cells can be realized.

Now, the voltage at which the fuse blows V _th = (α /
Although λ) ^1/2 cannot be controlled by this element, this can be equivalently performed by controlling the sensitivity of the light receiving element. Further, in this element, the IV characteristic is affected by the absolute potential (signal voltage) of the nodes at both ends. However, if the ohmic characteristics of the region 2 are obtained in the vicinity of the control voltage 0V, and the size of the element is set so that the value of the control voltage in which the energy function is minimized is, for example, about -10V. , It is possible to sufficiently reduce the influence of the signal voltage (about 0 to 1.0 V).

In a second embodiment of the present invention, a material having a lower conduction band energy is used for the well layer of the resonance tunnel structure. For example, in the first embodiment, the undoped GaAs quantum well layer 105 is replaced with In _x Ga.
It is replaced with a _1-x As mixed crystal layer. I in this structure
The energy of the quantum level in the well can be adjusted by changing the nAs composition x. For example, x = 0.2
And the energy of the quantum level is about 150m
eV lower.

In the first embodiment, the differential resistance near the origin is large (FIG. 3), which is different from the ideal fuse characteristic (FIG. 8). This portion occurs because the energy of the quantum level is too high and a certain voltage must be applied before the resonant tunneling current begins to flow. Therefore, by lowering the energy of the quantum level, this portion can be removed, and the ideal resistance fuse characteristic (FIG. 8) can be approximated.

FIG. 4 is a sectional view of a resistance fuse element showing a structure of a third embodiment of an image processing semiconductor device according to the present invention, and the same parts as those in the above-mentioned figures are designated by the same reference numerals. In the figure, reference numeral 114 is a Schottky electrode made of, for example, Ti / Au. In this embodiment, the control of the depletion layer width, which was performed by the pn junction in the first embodiment, is performed by the Schottky junction. Also in this case, by controlling the width of the depletion layer,
The amount of current can be controlled. However, the resonance tunnel structure is not destroyed by the diffusion of Zn described in the explanation (b) of the first embodiment, and this effect does not occur.

FIG. 5 is a sectional view showing the structure of a fourth embodiment of the semiconductor device for image processing according to the present invention, and the same parts as those in the above-mentioned figures are designated by the same reference numerals. In the figure, 102 'is a p-GaAs buffer layer and 110' is A.
uZn / Ni / Ti / Au electrode. In the fourth embodiment, the resistance fuse element according to the first to third embodiments and the rectifying diode connected in series are connected in parallel in the opposite direction and used as the resistance fuse element. is there. It is difficult for the resistive fuse elements described in the first to third embodiments to obtain a completely positive / negative symmetrical current-voltage characteristic, but by using in this way, a symmetrical current-voltage characteristic is obtained. can get. At this time, if a pn junction diode is used as the rectifying diode and is formed as a crystal layer structure as shown in the figure, an increase in cell area due to an increase in the number of elements can be suppressed to a minimum.

Although the GaAs / AlAs system is used as the resonant tunneling structure in the above-mentioned embodiments, the present invention is not limited to this and can be realized by using other materials. You can also For example, In _0.53 Ga _0.47 As or I that lattice-matches the InP substrate
If n _0.52 Al _0.48 As is used, a larger p / v (peak / valley) ratio can be obtained, and the effect is large. Here, pseudomorphic Al is used for the barrier layer.
You may use an As layer. In any case, it is sufficient if a resonant tunnel structure can be realized. Further, in order to prevent the diffusion of the dopant into the barrier, variations of the resonance tunnel structure, such as sandwiching the upper and lower sides of the resonance tunnel structure with undoped spacer layers, are also included in the present invention.

As the input element of the resistance network, a light receiving element such as MSM diode, PIN diode or phototransistor can be used. That is, the power source corresponding to the observation data d _i in FIG. 6 is configured by a combination of a light receiving element and a current-voltage conversion element (resistor, transistor, diode, etc.). Further, if a light emitting element such as a laser diode is integrated as an output (that is, the reading of the potential corresponding to the estimated data f _i of the resistance network in FIG. 6), all the input, calculation, and output are executed in parallel, and high speed operation is achieved. Operation and input / output are possible.

[0040]

As described above, according to the present invention,
Since an extremely highly integrated and high-performance network can be configured, it is possible to build a processing system (a neural network circuit that also incorporates an input / output system using photoelectric conversion elements) that can directly process real-world images on a single chip. It is possible to obtain an extremely excellent effect.

[Brief description of drawings]

FIG. 1 is a sectional view of a resistive fuse element showing a configuration of a first embodiment of an image processing semiconductor device according to the present invention.

FIG. 2 is a diagram showing current-voltage characteristics of a resonant tunnel diode.

FIG. 3 is a diagram showing current-voltage characteristics of the resistance fuse element according to the present invention.

FIG. 4 is a cross-sectional view of a resistive fuse element showing a configuration of a third embodiment of an image processing semiconductor device according to the present invention.

FIG. 5 is a sectional view showing the configuration of a fourth embodiment of the image processing semiconductor device according to the present invention.

FIG. 6 is a diagram showing a neural network circuit that removes noise from an image while holding discontinuous portions.

FIG. 7 is a diagram showing current-voltage characteristics of an ideal resistive fuse element that executes a line process.

FIG. 8 is a diagram showing current-voltage characteristics of an analog resistance fuse element that executes a line process based on a mean field approximation theory.

FIG. 9 is a diagram showing a resistance fuse circuit using conventional analog CMOS technology.

[Explanation of symbols]

101 semi-insulating GaAs substrate 102 n ⁺ -GaAs buffer layer 102 'p-GaAs buffer layer 103 n- GaAs layer 104 first AlAs barrier layer 105 GaAs quantum well layer 106 second AlAs barrier layer 107 n- GaAs layer 108 n ⁺ -GaAs contact layer 109 n-ohmic electrode 110 n-ohmic electrode 110 'AuZn / Ni / Ti / Au electrode 111 control electrode 112 p ⁺ region 113 high resistance layer 114 Schottky electrode

Claims (2)

[Claims] 1. A resonance tunnel for controlling a ratio of a peak current and a valley current flowing between a first terminal and a second terminal by changing a depletion layer width by a voltage applied to a third terminal. An image processing semiconductor device comprising a transistor, comprising a plurality of the resonant tunnel transistors connected in a mesh. 2. An n-type semiconductor layer made of a first semiconductor; a first barrier layer made of a second semiconductor having a conduction band higher in energy than a conduction band of the first semiconductor; A well layer made of a third semiconductor having a conduction band lower in energy than the conduction band of the second semiconductor; and a fourth well having a conduction band higher in energy than the conduction bands of the first semiconductor and the third semiconductor. A resonant tunneling structure having a second barrier layer made of a semiconductor and an n-type semiconductor layer made of a fifth semiconductor having a conduction band lower in energy than the conduction bands of the second semiconductor and the fourth semiconductor. A semiconductor device for image processing, comprising: an element including a control electrode having a Schottky or pn junction capable of extending a depletion layer in the resonant tunneling structure; and a circuit in which a plurality of the elements are connected in a mesh shape. .