JPH06113250A - Digital still picture recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain optimum error compensation in response to a part having an error by applying compression processing to digital picture data as division block data in the unit of blocks to implement the processing for a format without compression at high picture quality and for a format emphasizing consecutive shot performance almost the same. CONSTITUTION:Picture data read from division block memories 35,36 are used for consecutive data in the unit of division blocks and outputted to a PCM signal processing circuit 23 as a signal string through a memory output changeover switch 50 and a digital picture data compression circuit 21. In the case of the high picture quality mode, the circuit 21 is not in operation but passes through the received signal without any processing and a MIN/MAX circuit 33, the memories 35,36, the switch 50 and the circuit 21 are controlled by a recording picture processing controller 22. Recording mode information such as high picture quality mode/consecutive shot mode received from an input terminal 51 of the controller 22 is outputted to the PCM signal processing circuit 23, in which the recording mode information is recorded together with picture data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital still image recording / reproducing apparatus suitable for recording / reproducing a digital still image.

[0002]

2. Description of the Related Art Recently, a camera-integrated VTR is downsized,
The image quality has been improved along with the reduction in weight, and it is becoming easier to enjoy. Therefore, it is widely used for various purposes such as a child's growth record, travel, athletic meet, and skiing.

However, even if the image quality of the VTR is improved, the VTR still has sufficient performance for the purpose of watching a moving image, and the still image of the VTR has a resolution of a luminance signal and a color signal. At present, the image quality that can be applied to still photography is not reached in various points such as reproducibility. As a result, it is unavoidable to use a still camera together with a camera-integrated VTR, and it is a situation in which the still camera is used when it is desired to leave moving image recording to the camera-integrated VTR and leave it as a still image.

As an example of this solution, Japanese Patent Laid-Open No. 58-58
As disclosed in Japanese Patent No. 164383 and Japanese Patent Laid-Open No. 63-9378, a method has been proposed in which a still image is converted into digital data and recorded in an area provided by extending an end portion of a video signal recording track. As a result, not only is it possible to shoot still images at the same time as movie shooting with a single camera-integrated VTR, but the still image quality does not depend on the playback image quality of the VTR, and still photos can be taken according to the amount of recorded digital data. It is also possible to achieve high image quality that approaches that of.

[0005]

However, in order to obtain a high image quality, a large amount of digital data is required, so that the time required for recording becomes long. In particular, when still image digital data is recorded in an area provided by extending the end portion of the video signal recording track as in the above-mentioned conventional technique, the recording time required becomes longer because the digital data recording area is narrow. Therefore, when continuous shooting (characteristics indicating a minimum interval at which still images can be continuously recorded) is required, data compression-for example, sub-sampling or DPCM-should be performed at the expense of a slight deterioration in image quality. Therefore, since both high image quality and continuous shooting are important functions, the data format for high image quality-for example,
Both the format without data compression-and the data format with an emphasis on continuous shooting-for example, the format with data compression-have the same camera-integrated VTR.
In order to build a low-cost system, it becomes an issue to share these two data formats. In addition, when data compression is performed, if an error occurs during recording / reproduction, this error affects a wide range.

It is an object of the present invention to solve these problems and provide a low cost digital still image recording / reproducing apparatus having a high image quality mode and a continuous shooting mode.

[0007]

In order to achieve the above object, the present invention provides means for generating digital image data, a video memory for storing the digital image data, and image data stored in the video memory. A unit that divides the image data into a plurality of blocks, a unit that receives the image data in units of the divided blocks, and a unit that compresses the image data in units of the divided blocks, and a reference data required to decompress the image data in each of the divided blocks. At the beginning, and then, a means for arranging signals so that each piece of compressed image data is continuous, an output signal of the signal arranging means is input to a first input terminal, and an input signal of the compression means is input to a second input terminal. First switch means for inputting, means for controlling the first switch means according to the input recording mode information, and at least an output of the switch means Signal and recording mode information at the end of the recording track, means for reproducing a signal from the end of the recording track, means for discriminating the recording mode information from the reproduced signal, and reproduction Means for decompressing the reproduced signal into the original image data, the output signal of the decompressing means is input to the first input terminal, and the input signal of the decompressing means is input to the second input terminal. Inputting the second switch means, means for controlling the second switch means by the output signal of the discriminating means, means for detecting an error in the reproduced signal, and the error for the data expansion. Error determining means for determining whether it is necessary reference data or other compressed data, and error compensating means for performing error compensation on the expanded image data based on the output signal of the error determining means. It is configured.

[0008]

As described above, by using the digital image data as the divided block data and performing the compression process in the divided block unit, the data format at the time of high image quality-for example, the format without data compression-and the continuous shooting property It is possible to perform substantially the same format processing for both the data format with an emphasis on (eg, the format with data compression) by providing the switch means for bypassing the compression means and the decompression means. Further, by performing the compressed signal processing in units of divided blocks, it is possible to prevent error propagation in the block during expansion. Furthermore, error compensation can be detected separately for errors in the reference data (minimum value in the block and dynamic range) required for compression and decompression and errors in other portions, and optimal error compensation can be performed according to the error portion. It

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of a recording system block when the present invention is applied to a movie of a so-called 8 mm video format, which is a system capable of simultaneously shooting a moving picture and a digital still picture.

In the figure, reference numeral 1 denotes a camera block, which includes a lens 2, a CCD image pickup device 3, a CDS (correlated double sampling) / AGC (automatic gain adjustment) circuit 4, and an analog-digital conversion circuit (ADC) 5. , A camera signal processing circuit 6 and a digital-analog conversion circuit (DAC) 7. 8 is a VTR luminance signal processing circuit, 9 is V
TR chroma signal processing circuit, 10 FM for FM audio
Stereo circuit, 11 is a pilot signal generating circuit for tracking, 12 is a signal adding circuit, 13 is a recording amplifier, 1
4, 15 are rotary heads having different azimuth angles, 16 is a magnetic tape, 17 and 18 are audio input terminals for FM audio,
Reference numeral 19 is an addition circuit, 20 is a video memory for digital still images, 21 is a digital image data compression circuit, 22 is a recording image processing controller for recording processing of digital image data, and 23 is a PCM signal of 8 mm video 8 bit PCM format. A processing circuit, 24 is a memory for the PCM signal processing circuit 23, 33 is a MIN / MAX circuit for detecting the minimum value (MIN) and the maximum value (MAX) of the digital image data read from the video memory 20, and 35. , 36 are divided block memories for dividing the video memory 20 and storing the digital image data read from the divided blocks, 47 is an encoder circuit for converting the digital image data into an NTSC television signal, and 48 is 3 .58MHz modulation chroma signal output terminal, 49 is analog brightness Signal output terminal, 50 is a memory output selection switch, 51 is a continuous shooting mode input terminal, 52
Is a still image shutter input terminal.

An image input from the lens 2 is converted into an electric signal by the CCD image pickup device 3, low-frequency noise processing is performed by the CDS / AGC circuit 4, signal amplitude adjustment is performed, and then a digital signal is obtained by the ADC 5. Is converted to. The image signal converted into a digital signal is processed by the camera signal processing circuit 6
After the matrix processing, the gamma processing, and the like are performed, the luminance signal (Y signal) and the color difference signals (RY signal and BY signal) are output to the DAC 7 and the video memory 20 as digital signals. The digital luminance signal and color difference signal input to the DAC 7 are the analog luminance signal and 3.58
It is output after being converted into a modulated color signal in the MHz band.

The analog luminance signal is emphasized by the VTR luminance signal processing circuit 8 and then modulated into the FM luminance signal. The 3.58 MHz band modulated color signal is phase-inverted by the VTR chroma processing circuit 9 and then frequency-converted to the low frequency side of the FM luminance signal to become a low frequency converted color signal.
Also, the audio signal input from the input terminals 17 and 18 is
The FM stereo circuit 10 converts the signals into sum signals and difference signals, compresses the dynamic ranges of the signals, and then modulates the FM modulated audio signals (FM sum signal and FM difference signal). The pilot signal generation circuit 11 generates a 4-frequency pilot signal for tracking.

These FM luminance signal, low frequency conversion color signal, F
The M voice signal and the pilot signal are frequency-multiplexed by the signal adding circuit 12, and the recording amplifier 13, the rotary heads 14, 1
5 is recorded on the magnetic tape 16. The recording area is the video area shown in FIG.

On the other hand, the digital luminance signal and the digital color difference signal input to the video memory 20 are 1 field or 1 in accordance with the still image shutter signal from the input terminal 52.
It is temporarily stored in frame units. After that, with respect to the image data stored in the video memory 20, the input terminal 5
The processing corresponding to the mode set in 1 (continuous shooting mode or high image quality mode) is performed by the recording image processing controller 22.
And MIN / MAX circuit 33, divided block memory 3
5, 36, the memory output changeover switch 50, and the digital image data compression circuit 21.

That is, the digital image data is compressed in the continuous shooting mode, and the digital image is not compressed in the high image quality mode.

The recording image processing controller 22 and MIN /
The image data processed by the MAX circuit 33, the divided block memories 35 and 36, the memory output changeover switch 50, and the digital image data compression circuit 21 is stored in the PCM signal processing circuit 23 and the compression memory 24 as an 8 mm video PCM.
It has the same format as the audio recording data format.

It should be noted that 10- used in voice processing
The audio PCM signal processing circuit 23 is set in mode so that the 8-data compression conversion is not performed during still image recording.

The digital still image data, which is in the 8 mm video PCM audio recording data format in the PCM signal processing circuit 23, is multiplexed with the tracking pilot signal in the adding circuit 19 and is passed through the recording amplifier 13 and the rotary heads 15 and 16. It is recorded on the magnetic tape 16. Here, the digital still image data is recorded in the PCM area of the recording track shown in FIG.

Next, the recording image processing controller 22 and M
IN / MAX circuit 33, divided block memories 35, 3
6. The operations of the memory output changeover switch 50 and the digital image data compression circuit 21 will be described with reference to FIGS.

The digital luminance signal and the digital color difference signal output from the camera block 1 are 4 fsc sampling (f sc is the frequency of the color sub-carrier, NTS
It is about 3.58MHz in C method. ), 8 bits, 4: 2: 2
It has a format and the amount of information in one frame is 76.
It is 8 pixels x 484 lines. The digital luminance signal and the digital color difference signal are written in the video memory 20 in 1-frame units by the operation of the recording image processing controller 22 when a still image shutter which is timing information for recording a still image is input from the input terminal 52. .

Here, the video memory 20 stores digital image data (a _{1 1} , a _{1 2} , ..., A _{484 768} ) of 768 pixels × 484 lines, as shown in FIG.

In the high image quality mode, the digital image data (a _{1 1} , a _{1 2} , ..., A _{484 768} ) of 768 pixels × 484 lines stored in the video memory 20 is 8 pixels × as shown in FIG. It is divided into 11,616 blocks by 32 pixels of 4 lines. The divided digital image data is
The divided blocks are alternately stored in the divided block memories 35 and 36 through the MIN / MAX circuit 33. However,
In the high image quality mode, the MIN / MAX circuit 33 does not operate,
It works as a through circuit.

Therefore, for example, when the image data of the divided block 1 has been written in the memory A 35, the memory B is next written.
The image data of the divided block 2 is started to be written in 36, and the reading of the image data of the divided block 1 stored in the memory A 35 is started. Then, when the image data of the divided block 2 is written to the memory B36, the image data of the divided block 3 is started to be written to the memory A, and the memory B36 is started.
The reading out of the image data of the divided blocks 2 stored in the storage device starts. In this way, the writing and reading of the image data in the memory A35 and the memory B36 are sequentially and alternately repeated.

The image data read from the divided block memories 35 and 36 are a _{1 1} , a _{1 2} , ..., A _{1 8} , a _{2 1} ,
, A _{2 8} , a _{3 1} , ..., A _{4 8} as continuous data in divided block units, passing through the memory output changeover switch 50 and the digital image data compression circuit 21 to the PCM signal processing circuit 23 in divided block units. Are alternately transmitted in a signal arrangement as shown in FIG. In the high image quality mode,
The digital image data compression circuit 21 does not operate and functions as a through circuit. Here, each operation of the MIN / MAX circuit 33, the divided block memories 35 and 36, the memory output changeover switch 50, and the digital image data compression circuit 21 is controlled by the recording image processing controller 22. The recording image processing controller 22 also outputs recording mode information such as the high image quality mode / continuous shooting mode input from the input terminal 51 to the PCM signal processing circuit 23, and the PC
The M signal processing circuit 23 records the recording mode information together with the image data.

In the continuous shooting mode, digital image data (a _{1 1} , a _{1 2} , ..., A _{484 768} ) of 768 pixels × 484 lines stored in the video memory 20 is sub-sampled by the MIN / MAX circuit 33. , 4 as shown in FIG.
16,616 blocks each with 16 pixels of 4 pixels x 4 lines
(For example, a _{1 1} , a _{1 3} , a _{1 5} , ..., a _{4 6} and a _{4 8} are 1
Blocks are configured) and stored in the divided block memories 35 and 36 in units of divided blocks. Further, in the MIN / MAX circuit 33, the minimum value (MI
N) and the maximum value (MAX) are detected, and the digital image data compression circuit 21 detects the minimum value (MIN) and the maximum value (MA).
X) and are output. The image data stored in the divided block memories 35 and 36 is input to the digital image data compression circuit 21 through the memory output changeover switch 50. Here, the writing and reading of the image data to and from the memory A35 and the memory B36 are sequentially and alternately repeated as in the high image quality mode.

In the digital image data compression circuit 21, the luminance signal is data-compressed from 8 bits to 3 bits, and the chroma signal is data-compressed from 8 bits to 2 bits. These compressed data are sent to the PCM signal processing circuit 23 as continuous data in units of divided blocks as shown in FIG.

In the data compression, the method is completed within the divided blocks. For example, Japanese Patent Laid-Open No. 61-14
As shown in No. 4989, the minimum value (MIN) in the divided block is obtained, and the difference between this minimum value and each image data in the divided block is calculated. Next, based on the difference between the maximum value and the minimum value in the divided block (dynamic range (DR) of the divided block), the difference between each of the differences is divided into the dynamic range of the divided block after compression. Of the transmission data bit (for example, the luminance signal has 3 bits and the chroma signal has 2 bits). The calculation result becomes each compressed image data. Therefore, in the image data in the continuous shooting mode, as shown in FIG. After that, the compressed image data is sent to the PCM signal processing circuit 23 in a signal array in which the compressed image data are continuous.

With this configuration, the processing range of the recorded image data is the same in both the high image quality mode and the continuous shooting mode, so that the system can be shared.

FIG. 1 shows an embodiment of the reproducing system. In FIG. 1, reference numeral 25 is a preamplifier for amplifying the signals reproduced by the rotary heads 14 and 15, 26 is a VTR luminance signal reproduction processing circuit, 27 is a VTR chroma signal reproduction processing circuit, and 28.
Is a reproduction processing circuit for FM audio, 29 is a pilot signal processing circuit for reproduction tracking, 30 is a waveform equalization circuit for reproduction PCM signal, and 31 is for converting an output signal of the reproduction PCM signal waveform equalization circuit 30 into a digital signal. Data strobe circuit, 32 is a PCM signal reproduction processing circuit, 3
Reference numeral 4 is a digital image data expansion processing circuit for expanding the reproduction image data output from the PCM signal reproduction processing circuit 32, 37 is a reproduction image processing controller, 38 is a reproduction luminance signal output terminal, and 39 is a reproduction chroma signal output terminal. , 40 and 41 are reproduction audio signal output terminals, 42 is an output terminal for outputting a reproduction pilot signal to a servo circuit (not shown), and 45 is a memory output changeover switch.

From the magnetic tape 16 to the rotary heads 14 and 15
Each signal reproduced from the video area and the PCM area in FIG. 5 is amplified by the preamplifier 25. The signal reproduced from the video area is the VTR luminance signal reproduction processing circuit 2
6, VTR chroma signal reproduction processing circuit 27, FM audio reproduction processing circuit 28, and reproduction tracking pilot signal processing circuit 29. The VTR luminance signal reproduction processing circuit 26 extracts the FM luminance signal from the reproduction signal,
It demodulates M and outputs a reproduction luminance signal from the output terminal 38.
The VTR chroma signal reproduction processing circuit 27 extracts the low-frequency converted chroma signal from the reproduced signal, frequency-converts it to the original frequency band, and reverse-converts the phase invert to remove crosstalk from an adjacent track and output it. A reproduction chroma signal is output from the terminal 39. In the FM audio reproduction processing circuit 28, the FM sum signal and FM
The difference signal is extracted and FM demodulated to obtain a sum signal and a difference signal. After returning the dynamic range of the sum signal and the difference signal to the original dynamic range, they are converted into a right side audio signal and a left side audio signal by the matrix circuit and output terminal 4
It is output from 0, 41. The reproduction tracking pilot signal processing circuit 29 extracts a pilot signal from the reproduction signal, and multiplies the extracted pilot signal by the local pilot signal. After that, the pilot signals reproduced from both adjacent tracks are extracted by the respective filters, the level difference is detected, and output from the output terminal 42 to the servo circuit (not shown).

On the other hand, the signal reproduced from the PCM area is output to the data strobe circuit 31 after the intersymbol interference is corrected by the reproduced PCM signal waveform equalization circuit 30. The data strobe circuit 31 extracts a reproduction clock from the reproduction signal and identifies "0" or "1" of the reproduction signal based on this clock. The signal identified as “0” or “1” is output to the PCM signal reproduction processing circuit 32 together with the reproduction clock. The PCM signal reproduction processing circuit 32 uses the PCM memory 24 to extend the time axis and correct an error generated during recording and reproduction. Also, P
The CM signal reproduction processing circuit 32 determines the type of reproduced digital signal (still image signal, audio signal) and the recording mode (high image quality mode, continuous shooting mode).

The PCM signal reproduction processing circuit 32 outputs the data subjected to processing such as error correction and time axis expansion to the digital image data expansion processing circuit 34, and at the same time, as a result of the discrimination of the recording mode, an error indicating an uncorrectable error. The flag is output to the reproduction image processing controller 37. When the type of the reproduced digital signal is an audio signal, the reproduced image processing controller 37 does not perform image data processing in a system that does not support the reproduction of the audio signal as in this embodiment. The control signal is output to the processing circuit.

Since the signal processing differs depending on the recording mode (high-quality mode, continuous shooting mode), the high-quality mode and continuous shooting mode will be described separately below.

When the recording mode is the high image quality mode, the PCM
The image data output from the signal reproduction processing circuit 32 passes through the digital image data expansion processing circuit 34 and is stored in the divided block memories 35 and 36 in units of divided blocks. However, when the error flag is output (when an uncorrectable error occurs), the image data immediately before the error is stored again. In the high image quality mode, the digital image data expansion processing circuit 34 does not operate and the through operation is performed.

When the image data for one divided block is stored in the divided block memories 35 and 36, the divided block memory 3 is instructed by the reproduced image processing controller 37.
Image data are alternately transferred from 5, 36 through the memory output changeover switch 45 to the data interpolation circuit 46 in units of one divided block.

In the data interpolation circuit 46, the control signal generated based on the error flag input to the reproduction image processing controller 37 for the error data of only one pixel is used to generate the front, rear, left and right image data in the divided block. Image data subjected to interpolation processing (for example, calculating an average value of data before and after error) is created, and error data of only one pixel is replaced with the created interpolation data. The image data that has passed through the data interpolation circuit 46 is stored in the video memory 20 according to an instruction from the reproduction image processing controller 37. When one frame of image data is stored in the video memory 20 in this manner, the image data (luminance data, color difference) is transmitted to the encoder circuit 47 for converting the video memory 20 into an NTSC television signal according to an instruction from the reproduction image processing controller 37. Data) is output. The encoder circuit 47 outputs an analog luminance signal and a 3.58 MHz modulation chroma signal.

When the recording mode is the continuous shooting mode, P
The image data output from the CM signal reproduction processing circuit 32 passes through the digital image data decompression processing circuit 34 to be decompressed to the original 8-bit image data, and is then alternately divided into divided block memories 35 and 36 in units of divided blocks. Stored in. The digital image data expansion processing circuit 34 and the divided block memories 35 and 36 are controlled by the reproduction image processing controller 37.

However, when an uncorrectable error occurs in the minimum value (MIN) or the dynamic range (DR) in the divided block necessary for data decompression, the reproduced image processing controller 37 instructs the divided block memory 35,
The storage of the image data in 36 is stopped for a period corresponding to one divided block, and the chip select designating the write memory is reversed. That is, the memory A and the memory B are alternately stored in the divided block memory A35 and the divided block memory B36 in this order, and when the data is stored in the memory B, the minimum value (MIN) and the dynamic range ( When an uncorrectable error occurs in (DR), the storage of the data in the memory B is stopped and the next storage memory is set as the memory B again (corresponding to inverting the chip select). As a result, the minimum value (MIN) and the dynamic range (D) are set by the operation of the memory output changeover switch 45 which performs the changeover operation according to the chip select.
When an uncorrectable error occurs in R), the divided data immediately before the error occurs is read again.

When an uncorrectable error occurs in the compressed data other than the minimum value (MIN) and the dynamic range (DR), error detection and correction of the PCM signal reproduction processing circuit 32 are performed in 8-bit units. There are 3 to 4 errors in the compressed data composed of bits or 3 bits. Therefore, when an error flag is output for compressed data other than the minimum value (MIN) or dynamic range (DR), reproduction is performed so that 3 to 4 image data periods are replaced and stored with the image data immediately before the error. The image processing controller 37 uses the digital image data expansion processing circuit 3
4 and the divided block memories 35 and 36. With such a configuration, optimum error compensation can be performed according to the error occurrence location.

When the image data for one divided block is stored in the divided block memories 35 and 36, the divided block memory 3 is instructed by the reproduced image processing controller 37.
Image data are alternately transferred from 5, 36 through the memory output changeover switch 45 to the data interpolation circuit 46 in units of one divided block. The data interpolation circuit 46 interpolates and generates the image data thinned out by the sub-sampling performed at the time of recording.

In the continuous shooting mode, since there are 3 to 4 errors, interpolation data generation for error data as in the high image quality mode is not performed, and the data interpolation circuit 46 uses the image data immediately before the error. Using the replaced data, only the interpolation generation of the image data thinned out by the sub-sampling is performed.

The output image data of the data interpolation circuit 46 is
It is stored in the video memory 20 according to an instruction from the reproduction image processing controller 37. In this way, the video memory 20
When one frame of image data is stored in, the encoder circuit 4 for converting the video memory 20 into an NTSC television signal according to an instruction from the reproduction image processing controller 37.
Image data (luminance data, color difference data) is output to 7. The encoder circuit 47 outputs the analog luminance signal and 3.5.
It outputs an 8 MHz modulated chroma signal.

In this embodiment, the video memory 20 is set to 1
Although the video memory of the frame has been described, the video memory of one field may be used, or the video memory of one frame or more may be encountered.

[0045]

As described above, the digital image data is divided into a plurality of blocks, and in the continuous shooting mode, compression processing is performed for each divided block, and the reference data (minimum value in the block Dynamic range)
It is recorded in the signal array starting with. On the other hand, in the high image quality mode, data compression is not performed for each divided block, and the data is recorded as it is. In this way, the signal processing is performed on the same divided block regardless of the continuous shooting mode and the high image quality mode, so that the signal processing can be made common in both modes. Further, by performing the compressed signal processing in units of divided blocks, it is possible to prevent error propagation in the block during expansion. Furthermore, error compensation can be detected separately for errors in the reference data (minimum value in the block and dynamic range) required for compression and decompression and errors in other portions, and optimal error compensation can be performed according to the error portion. The effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a playback system of a camera-integrated VTR to which the present invention is applied.

FIG. 2 is a block diagram showing an example of a recording system of a camera-integrated VTR to which the present invention is applied.

FIG. 3 is a signal diagram for explaining the operation of FIG.

4 is a diagram showing a signal arrangement for explaining the signal processing operation of FIG.

5 is a diagram showing a recording track pattern of the camera-integrated VTR shown in FIGS. 2 and 3. FIG.

[Explanation of symbols]

20 ... Video memory, 21 ... Digital image data compression circuit, 22 ... Recording image processing controller, 23 ... PCM
Signal processing circuit, 32 ... PCM signal reproduction processing circuit, 33 ...
MIN / MAX circuit, 34 ... Digital image data expansion processing circuit, 35, 36 ... Divided block memory, 37 ...
Reproduction image processing controller, 45, 50 ... Changeover switch, 46 ... Data interpolation circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/92 H 4227-5C

Claims (4)

[Claims] 1. A time-axis-compressed digital signal is recorded at the end of each recording track that is sequentially formed on a magnetic tape obliquely with respect to its longitudinal direction, and a video signal is recorded at the other part of the recording track. In a magnetic recording / reproducing apparatus adapted to record data, means for generating digital image data, a video memory for storing the digital image data, and means for dividing the image data stored in the video memory into a plurality of blocks. Image data is input in units of the divided blocks, image data is compressed in units of divided blocks, and an output signal of the compression unit is input to a first input terminal,
First switch means for inputting the input signal of the compression means to the input terminal of the switch, means for controlling the first switch means according to the input recording mode information, and at least an output signal of the switch means and recording Means for recording mode information at the end of the recording track, means for reproducing a signal from the end of the recording track, means for discriminating the recording mode information from the reproduced signal, and the reproduced signal Means for decompressing the reproduced signal to the original image data, and an output signal of the decompressing means for inputting to the first input terminal.
Digital still image recording, characterized by having a second switch means for inputting the input signal of the decompressing means to the input terminal of and a means for controlling the second switch means by the output signal of the discriminating means. Playback device. 2. A time-axis-compressed digital signal is recorded at the end of each recording track formed on the magnetic tape in a diagonal direction with respect to its longitudinal direction, and a video signal is recorded at the other part of the recording track. In a magnetic recording / reproducing apparatus adapted to record data, means for generating digital image data, a video memory for storing the digital image data, and means for dividing the image data stored in the video memory into a plurality of blocks. Image data is input in units of the divided blocks, the image data is compressed in units of the divided blocks, the image data of each of the divided blocks is preceded by reference data necessary for data expansion, Means for arranging signals so that the compressed image data is continuous, and an output signal of the signal arranging means is input to the first input terminal,
A first input terminal to which the input signal of the compression means is input to the second input terminal
Switch means, means for controlling the first switch means in accordance with the input recording mode information, and means for recording at least the output signal of the switch means and the recording mode information at the end of the recording track. Means for reproducing a signal from the end of the recording track, means for discriminating recording mode information from the reproduced signal, and inputting the reproduced signal to expand the reproduced signal to original image data Means for inputting the output signal of the expanding means to the first input terminal,
Digital still image recording, characterized by having a second switch means for inputting the input signal of the decompressing means to the input terminal of and a means for controlling the second switch means by the output signal of the discriminating means. Playback device. 3. A time-axis-compressed digital signal is recorded at the end of each recording track that is sequentially formed on the magnetic tape obliquely with respect to its longitudinal direction, and a video signal is recorded at the other part of the recording track. In a magnetic recording / reproducing apparatus adapted to record data, means for generating digital image data, a video memory for storing the digital image data, and means for dividing the image data stored in the video memory into a plurality of blocks. A means for compressing the image data for each of the divided blocks, and the compressed image data for each of the divided blocks is preceded by reference data necessary for data decompression, and a signal is arranged so that each compressed image data is continuous. Means, a means for recording the signal arrangement at the end of the recording track, and a means for reproducing the signal arrangement from the end of the recording track. A stage, means for expanding the reproduced signal array into original image data, means for detecting an error in the reproduced signal array, whether the error is reference data necessary for the data expansion, and Digital still image recording having an error discriminating means for discriminating whether the compressed data is compressed data and an error compensating means for compensating the error of the expanded image data based on the output signal of the error discriminating means. Playback device. 4. A time-axis-compressed digital signal is recorded at the end of each recording track that is sequentially formed on the magnetic tape obliquely with respect to its longitudinal direction, and a video signal is recorded at the other part of the recording track. In a magnetic recording / reproducing apparatus adapted to record data, means for generating digital image data, a video memory for storing the digital image data, and means for dividing the image data stored in the video memory into a plurality of blocks. Image data is input in units of the divided blocks, the image data is compressed in units of the divided blocks, the image data of each of the divided blocks is preceded by reference data necessary for data expansion, Means for arranging signals so that the compressed image data is continuous, and an output signal of the signal arranging means is input to the first input terminal,
A first input terminal to which the input signal of the compression means is input to the second input terminal
Switch means, means for controlling the first switch means in accordance with the input recording mode information, and means for recording at least the output signal of the switch means and the recording mode information at the end of the recording track. Means for reproducing a signal from the end of the recording track, means for discriminating recording mode information from the reproduced signal, and inputting the reproduced signal to expand the reproduced signal to original image data Means for inputting the output signal of the expanding means to the first input terminal,
Second switch means for inputting the input signal of the decompressing means to the input terminal, a means for controlling the second switch means by the output signal of the discriminating means, and an error in the reproduced signal is detected. Means, an error discrimination means for discriminating whether the error is the reference data necessary for the data decompression or other compressed data, and the decompressed image data of the decompressed image data based on the output signal of the error discrimination means. A digital still image recording / reproducing apparatus comprising: an error compensating means for compensating for an error.