JPH06112867A - Equalization system - Google Patents

Abstract

PURPOSE:To reduce a training failure probability by implementing duplicate equalization comprising forward equalization and backward equalization and selecting information bits equalized in an equalizing direction in which an average equalization error is smaller between the forward equalization and backward equalization. CONSTITUTION:I, Q signals are fed respectively to an A/D converter 15 and digitized at a demodulation circuit 14 by using a demodulation clock, and the digital signal is fed to a DSP 17 of an equalizer 16. On the other hand, the I, Q signals outputted from the circuit 4 are fed to an identification circuit 21, where a QPSK data pattern is identified, fed to a frame signal detection circuit 22 and a training bit location of each burst is informed to the DSP 17. The DSP 17 uses a training bit of a specific burst to implement forward equalization and uses a training bit of a succeeding burst to implement backward equalization and recovered information bits are stored in a RAM 18. Then the DSP 17 selects the information bits in the equalizing direction having a less average equalization error after equalization and gives them to a decoder 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalization system, and more particularly to an equalization system for an equalizer used in a digital radio communication receiver.

[0002]

2. Description of the Related Art A TDMA (Time Division Multiple Access) is used as a multiple access system in which multiple stations transmit to one repeater at the same carrier frequency by time division and communicate with each other.
s Synchronization) method.

In the TDMA system, as shown in FIG. 4, a plurality of bursts (time slots) T _{1 to} T ₃ in one frame are assigned to each station. A training bit TB is transmitted at the burst tip of each burst T _{1 to} T ₃ , and subsequently an information bit DB is transmitted.

The equalizer of the TDMA digital radio communication receiver is composed of an adaptive digital filter.
The conventional equalizer automatically adjusts the equalizer parameters with the training bits in the burst assigned to its own receiver, and then adaptively changes the filter parameters to reproduce the information bits.

[0005]

In the conventional equalizer, the training bit at the burst tip automatically adjusts the equalizer parameter to reproduce the subsequent information bit while adaptively changing the parameter of the filter. To perform equalization,
If the transmission line is a non-minimum phase system, the training does not converge, or if the transmission line becomes a non-minimum phase system during adaptive equalization, adaptive equalization diverges and there is a problem that information bits cannot be equalized well. It was

On the other hand, IEICE Transactions B-II Vo
l. J74-B-II No3 pp91-100 dual mode equalization system for digital mobile radio is provided with training bits at the leading and trailing ends of each burst and forward equalization by training using the training bits at the leading end. , It is described that the probability of training failure is reduced by performing backward equalization by training using the trailing end training bit and selecting an equalization direction with a small average equalization error after equalization. ing.

However, this double equalization system requires training bits at the leading and trailing ends of each burst, so the format must be changed, and the ratio of training bits to information bits becomes large. There was a problem that the transmission efficiency deteriorates.

The present invention has been made in view of the above points,
An object of the present invention is to provide an equalization method that does not require a change in frame format, does not deteriorate transmission efficiency, reduces the training failure probability by double equalization, and performs effective equalization.

[0009]

According to the equalization method of the present invention, an equalization method for equalizing a transmission digital signal in which a frame is composed of a plurality of bursts consisting of training bits and information bits is assigned to its own device. Form a pseudo burst with a specific burst in the specified frame and the training bit of the subsequent burst, perform forward equalization by training using the training bit of the specific burst in the pseudo burst, and train the next burst. Backward equalization is performed by training using bits, and an information bit equalized in the equalization direction having a small average equalization error between the above-mentioned forward equalization and backward equalization is selected.

[0010]

According to the present invention, the training failure probability is reduced by the double equalization including the forward equalization and the backward equalization to effectively perform the equalization, and the training bit of the next burst is added to the specific burst. By forming the burst, it is not necessary to change the frame format and the transmission efficiency does not deteriorate.

[0011]

2 is a block diagram of an embodiment of a digital communication receiver to which the system of the present invention is applied.

In the figure, the TDM received by the antenna 11
QPSK (Quadrature Phase Shift Keying) of A communication
The modulated high frequency signal is selectively tuned by the receiving unit (Rx) 12 and output as an intermediate frequency signal. This intermediate frequency signal is amplified by the automatic gain control circuit (AGC) 13 and supplied to the demodulation circuit (DEM) 14, where the I signal and Q
The signal is demodulated.

Each of the I signal and the Q signal is supplied to the A / D converter 15, where it is digitized by using the demodulation clock CLK obtained by the demodulation circuit 14, and then parallel / serial converted to obtain a digital signal. It is supplied to the processor (DSP) 17. DSP17 is RAM1
8 constitutes an equalizer 16 and the information bits in the burst equalized by the equalizer 16 are supplied to a decoder 19.

On the other hand, the I signal and the Q signal output from the demodulator 14 are supplied to the identification circuit 21, where the QPSK data pattern is identified, and this data is supplied to the frame signal detection circuit 22. The frame signal detection circuit 22 compares this QPSK data pattern with a unique pattern included in a predetermined position of each time slot, and determines the start position of each frame and the training bit position of each burst from the position where the QPSK data pattern matches the unique pattern. The detection is performed, the head position of each frame is notified to the intermittent reception control unit 23, and the training bit position of each burst is notified to the DSP 17.

The intermittent reception control unit 23 intermittently receives and demodulates only the training bit section of the burst assigned to the own receiver and the subsequent burst in each frame, the receiving unit 12, the AGC 13, the demodulation circuit. 14,
Control each one.

Thus, in the frame format of the TDMA system as shown in FIG. 3, the burst T is transmitted to the own receiver.
_{If 1} is assigned, the entire burst T ₁ and the training bits of the subsequent burst T ₂ are demodulated and the digitized I and Q signals are equalized by the equalizer 1.
6 is stored in the RAM 18. DSP 17 of the equalizer 16
Considers the training bits of burst T ₁ (specific burst) and burst T ₂ (next burst) shown in FIG. 1A as a single pseudo burst having training bits at the leading and trailing ends, and training of burst T ₁ The information bit reproduced by forward equalization in the direction of arrow X ₁ by the training using the bits is stored in the RAM 18, and the backward equalization in the direction of arrow X ₂ by the training by the training bit of the burst T ₂ is performed and reproduced. The generated information bit is stored in the RAM 18. After this, DSP
Reference numeral 17 denotes an information bit reproduced by selecting an information bit in the equalization direction having a small average equalization error after equalization among the information bits obtained by the forward equalization and the information bit obtained by the backward equalization.
8 to the read decoder 19.

Instead of selecting the information bit in the equalization direction having a small average equalization error in the DSP 17, the information bit in the equalization direction having a small equalization error in each of the front equalization and the rear equalization may be selected. .

In the conventional double equalization system, as shown in FIG. 1 (B), training bits are required at the leading end and the trailing end of the burst T ₁ and the format must be changed. However, in the method of the present invention shown in FIG. 1A, since the training bit of the burst T ₂ following the burst T ₁ is used to perform double equalization, the burst T ₁ Alternatively, even if a large amount of noise is locally superimposed on the training bit of T ₂ , the probability of training failure is reduced, effective equalization can be performed, and there is no need to change the format, and there is no deterioration in transmission efficiency. .

Although the above embodiment has described the case where the training bit is at the leading end of each burst, when the training bit is at the trailing end of each burst, the training bit at the trailing end of the specific burst and the immediately preceding burst is used. Should be regarded as a pseudo burst, and is not limited to the above embodiment.

[0020]

As described above, according to the equalization method of the present invention, there is no need to change the frame format, the transmission efficiency is not deteriorated, and the training failure probability is reduced by double equalization, which is effective. It can be converted into a polymer and is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a system of the present invention.

FIG. 2 is a block diagram of a receiver to which the system of the present invention is applied.

FIG. 3 is a diagram for explaining a demodulation section of the method of the present invention.

FIG. 4 is a diagram showing a frame format.

[Explanation of symbols]

 14 Demodulation circuit 15 AD converter 16 Equalizer 17 DSP 18 RAM 21 Discrimination circuit 22 Frame signal detection circuit 23 Intermittent reception control section

Claims (2)

[Claims] 1. In an equalization method for equalizing a transmission digital signal in which a frame is composed of a plurality of bursts each including a training bit and an information bit, a specific burst in a frame assigned to its own device and its adjacent Form a pseudo burst with the training bit of the burst, and perform forward equalization by training using the training bit of the specific burst in the pseudo burst, and perform backward equalization by training using the training bit of the next burst, An equalization method characterized by selecting information bits equalized in an equalization direction having a small average equalization error between the above-mentioned forward equalization and backward equalization. 2. The equalization method according to claim 1, wherein instead of the information bit equalized in an equalization direction having a small average equalization error between the forward equalization and the backward equalization, the forward equalization is performed. An equalization method characterized by selecting information equalized in an equalization direction with a small equalization error with backward equalization.