JPH06112835A - Alternating current generating circuit with pseudo waveform by pulse width modulation - Google Patents

Abstract

PURPOSE:To relieve the load of arithmetic operation or the like of a microprocessor, to attain high speed processing and to reduce cost. CONSTITUTION:A circuit consists of a pulse width data output circuit 2, a pulse width conversion circuit 3, and an inverter circuit 4. Pulse width data using one period of a pulse width corresponding to a voltage at each of equal division points being equal divisions of one period of an alternating current as one group are stored in a nonvolatile memory 9 of the pulse width data output circuit 2 by plural command voltages. When a voltage command and a frequency command are inputted from a microprocessor 1, the pulse width data corresponding to the voltage command are repetitively outputted from the memory 9 at a time interval corresponding to the frequency command and converted into an alternating current with a pseudo waveform at the inverter circuit 4 via the pulse width conversion circuit 3 and the resulting current is fed to a load 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-waveform AC generation circuit by pulse width modulation used for controlling the rotation speed of a single-phase or multi-phase AC induction motor by the output of a microprocessor or the like.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 9, a logic circuit for obtaining a pseudo sine wave alternating current with a variable voltage and a variable frequency by pulse width modulation has a sine wave command signal S and a reference triangular wave T (or a ramp wave). And a pulse wave P that is pulse width modulated by comparing
Then, by outputting this to an inverter circuit, a pseudo sine wave alternating current by pulse width modulation supplied to a load was obtained.

In addition, under the increasing necessity of control by a microprocessor of a computer or the like, pulse width modulation is performed by giving a digital voltage and frequency command from the microprocessor or the like instead of the above-mentioned sine wave analog command signal. There is a method of generating the generated pulse wave. Figure 10
In the circuit, is a counter b to which a voltage command is given from the microprocessor a, a function generator c connected thereto, a D / A converter d to which a frequency command is given from the microprocessor a, and a function generator c. D / A converter e for generating digital sine wave by combining digital data corresponding to the voltage command output from the D / A converter d with the control signal of the frequency command analogized by the D / A converter d
And a pulse width generator f for generating a reference triangular wave and a pulse width generator g for comparing the triangular wave output from this with a sine wave to obtain a pulse width modulated pulse wave proportional to the pseudo sine wave. .

The circuit shown in FIG. 11 is a circuit utilizing the arithmetic function of a microprocessor. This circuit receives a frequency command from the microprocessor a and outputs a counter b ₁
Generates a trigger signal corresponding to the phase of the triangular wave of 0 °, 90 °, 180 °, 270 °, interrupts the microprocessor a with this trigger signal, calculates the value of the sine wave corresponding to this point, and counts it. b ₂ is outputted as a voltage command to the counter b ₂ is based on operating the bistable circuit h the voltage command, and outputs a pulse which is now a pulse width modulation.

[0005]

In the above circuit, the command for outputting the pulse width-modulated pulse is given by a sine wave once replaced with an analog amount, or the command is given by using the arithmetic function of the microprocessor. Because
There was a problem in cost increase and high speed operation.

It is an object of the present invention to eliminate the interposition of the above analog signals, reduce the load of the microprocessor for operations, etc., increase the speed and reduce the cost.

[0007]

In order to achieve the above object, the alternating current generating circuit according to the first aspect divides one cycle of alternating current of a sine wave or other arbitrary waveform corresponding to a command voltage,
It includes a non-volatile memory storing a plurality of groups corresponding to a plurality of command voltages as pulse width data in which one cycle of a pulse width value corresponding to the voltage value at each of the equal points is included as a group. By the voltage command output from, the pulse width data of the group corresponding to this,
A pulse width data output circuit repeatedly output from the non-volatile memory at fixed time intervals corresponding to a frequency command output from a microprocessor or the like; and a group of pulse width data corresponding to a voltage command output from the output circuit, A pulse width conversion circuit that converts a pulse width signal into a repetitive pulse width signal at fixed time intervals corresponding to the frequency command, and an inverter circuit that exchanges the pulse width signal output from the pulse width conversion circuit into a pseudo-waveform alternating current, Claim 2
The described alternating current generation circuit equally divides one cycle of alternating current of a sine wave or other arbitrary waveform corresponding to a command voltage, and defines one cycle of pulse width value corresponding to the voltage value at each of the equally divided points as one group. As the pulse width data to be stored, a basic phase non-volatile memory storing a plurality of groups corresponding to a plurality of command voltages,
The pulse width data for each of a plurality of groups corresponding to a plurality of command voltages stored in the non-volatile memory is sequentially shifted in each group according to a phase change in a polyphase alternating current having a predetermined phase change. The stored non-volatile memory, select a plurality of the non-volatile memory by the same address line by the voltage command output from the microprocessor, etc., the pulse of the multi-phase group corresponding to the selected voltage command A pulse width data output circuit that repeatedly outputs width data from the plurality of nonvolatile memories at fixed time intervals corresponding to a frequency command output from a microprocessor or the like, and a voltage command output from the output circuit. The pulse width data of the phase group is
A pulse width conversion circuit that repeatedly converts into a multi-phase pulse width signal at fixed time intervals corresponding to the frequency command, and a multi-phase pulse width signal output from the pulse width conversion circuit is exchanged with a pseudo-waveform multi-phase AC. And an inverter circuit that operates.

[0008]

According to the alternating current generating circuit of the first aspect, in the nonvolatile memory of the pulse width data output circuit, one cycle of alternating current of an arbitrary waveform such as a sine wave corresponding to the command voltage is equally divided, and the like. The pulse width data for one group of one cycle of the pulse width value corresponding to the voltage value for each minute point is stored for a plurality of groups corresponding to a plurality of command voltages, and the voltage command output from the microprocessor etc. When input to the non-volatile memory, the pulse width data of the group corresponding to the voltage command is repeatedly output from the non-volatile memory at fixed time intervals corresponding to the frequency command output from the microprocessor, and the pulse width data of this group is output. Is converted into a pulse width signal by a pulse width conversion circuit, and this pulse width signal is exchanged with an alternating current having a pseudo waveform which is pulse width modulated by an inverter circuit.

According to the alternating-current generating circuit of the second aspect, when the non-volatile memory for the number of phases of the multi-phase alternating current is selected by the same address line by the voltage command output from the microprocessor or the like, it corresponds to the voltage command. The pulse width data of the multi-phase group is repeatedly output from the nonvolatile memory for the number of phases at fixed time intervals corresponding to the frequency command output from the microprocessor, etc. Is converted into a multi-phase pulse width signal by a pulse width modulation circuit, and this multi-phase pulse width signal having a phase change is converted into a pseudo-phase multi-phase AC by an inverter circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a single-phase pseudo sine wave AC generating circuit.

In the figure, 1 is a microprocessor,
Reference numeral 2 is a pulse width data output circuit connected to the microprocessor 1, 3 is a pulse width conversion circuit, 4 is an inverter circuit, and 5 is a load such as a capacitor type induction motor.

The pulse width data output circuit 2 comprises a pulse generating circuit 6, a frequency dividing circuit 7, a counter 8 and a non-volatile memory 9 (hereinafter simply referred to as a memory).

FIG. 2 shows a pseudo sine wave alternating current by pulse width modulation in which one cycle is divided into 16 equal parts, and the pulse width value at each equal point is the voltage value at the corresponding equal point of the original sine wave alternating current. Corresponding to. The memory 9 stores, for example, 16-byte pulse width data in which one cycle of the pulse width value constitutes one group, and the pulse width data has a constant interval (5
At 0 Hz, it is repeatedly output to the pulse width conversion circuit 3 every 1.25 milliseconds), and the pulse width signal obtained from the pulse width conversion circuit 3 is output to the inverter circuit 4 so that the inverter circuit 4 can continuously generate pseudo signals. A sinusoidal alternating voltage is obtained, which is supplied to the load 5.

Since the pulse width data in which one cycle of the pulse width value corresponds to one group corresponds to one voltage command,
For variable voltage output, a plurality of groups of pulse width data are stored in the memory 9 according to the voltage range and the resolution accuracy. When the pseudo sine wave has a variable frequency, the interval at which the pulse width data is output is variable.

According to the circuit shown in FIG. 1, a pseudo sinusoidal alternating current having a variable voltage and a variable frequency can be obtained.

Next, the circuit shown in FIG. 1 will be described in detail.

The microprocessor 1 outputs a pseudo sine wave frequency command as 8-bit data (DF0 to DF7).
In addition, the voltage command is 8-bit data (DV0 to DV
It is designed to output in 7). The pulse generation circuit 6 outputs a pulse train (102,400 CPS at a frequency of 50 Hz, referred to as a clock pulse here) in accordance with the frequency command of the 8-bit data. The frequency dividing circuit 7 divides the pulse train into 1/128, and the divided pulse train is used as an address pulse and a data set pulse used in the pulse width conversion circuit 3 described later. The counter 8 is, for example, a 4-bit counter and sequentially counts the address pulses, and the count value is the address A of the memory 9.
0 to A3, which form the lower 4 bits of the address, which corresponds to the above-described command voltage, for example, one cycle of the pulse width value corresponding to the voltage value at each equal point of the sinusoidal AC waveform. It is used to sequentially select 16 bytes as one group.

On the other hand, the voltage command from the microprocessor 1 is output to the addresses A4 to A11 of the memory 9, which constitutes the upper 8 bits of the address and is used to select the group for the variable voltage output. To use. Therefore, according to the memory 9, the voltages of 256 groups can be selected by the addresses A0 to A11. The memory 9 outputs the pulse width data selected by the addresses A0 to A11 from the terminals DB0 to DB7 each time the address pulse is input to the counter 8.

This pulse width data has positive and negative polarities and pulse width information, and is stored in the memory 9 as 8-beat data including a two's complement calculated so that the output of the inverter 4 becomes a pseudo sine wave. , -128 to 0 to +127 (10
)) Pulse width. The pulse width conversion circuit 3 is
For example, the previously proposed circuit (Japanese Patent Application No. 4-223017) shown in FIG. 3 is used.

In the 8-bit pulse width data output from the memory 9, the most significant bit (MSB) indicates positive or negative polarity, when it is "0", it is positive, and the remaining 7 bits indicate the pulse width. Therefore, 0 to 7F is displayed in hexadecimal notation (0 to 127 in decimal notation). On the other hand, when "1" is negative,
It is represented by 2's complement and represents FF to 80 in hexadecimal notation (-1 to -128 in decimal notation). The half cycle of the pseudo sine wave alternating current by pulse width modulation is expressed as positive and the remaining half cycle is expressed as negative.

The 8-bit pulse width data output from the memory 9 is latched in the counters 10 ₁ and 10 ₂ shown in FIG. 3 by the above-mentioned data set pulse transmitted simultaneously with the pulse width data. This pulse width data is immediately output to D00 to D03 of the counters 10 ₁ and 10 ₂ . When the pulse width data is "0" or the counters 10 ₁ and 10 ₂ are in the initial state, all the outputs are "0", and the OR gate 11
Is also "0", but the output of OR gate 11 is "1" when the latched pulse width data is other than "0".
Then, the AND gate 12 is opened, so that the counter 10 ₂ starts counting the clock pulses. The most significant bit of the pulse width data is a data set pulse, which is a 1-bit data latch circuit (hereinafter D latch circuit) 1
It is latched by 3, and its output is input to the addition / subtraction terminals (Up / Down) of the counters 10 ₁ , 10 ₂ , and when the pulse width data is positive, the counting operation is in the subtraction mode.

When the counting result becomes "0", OR gate 1
Since the output of 1 also becomes 0 and the AND gate 12 is closed, the counting operation of the counter 10 ₂ is stopped. This stop condition is maintained until the next data set pulse is sent.

When the pulse width data is negative, the counting operation is in the addition mode. As in the positive case, as a result, the time Td until the pulse width data and this count value match becomes the pulse width signal output. To do. At the same time, positive and negative polarity signals of the pulse width data are obtained from the output of the D latch circuit 13. According to this circuit, positive / negative binary evolution digital parallel data including a two's complement can be converted into a polarity and a pulse width signal with an extremely simple circuit.

In FIG. 1, a + pulse width signal and a −pulse width signal, and a + polarity signal and a −polarity signal are a logic circuit and an inverter in which the pulse width signal and the positive / negative polarity signal of FIG. 3 are combined with an AND gate and an inverter. Can be obtained by inputting each into a logic circuit using.

FIG. 4 shows pulse width data stored in the memory 9 when a short-wave AC output is obtained.

FIG. 5 shows a two-phase pseudo sine wave AC generating circuit.

The clock pulse is a clock proportional to the frequency of the above pseudo sine wave alternating current (at a frequency of 50 Hz,
102,400 CPS), with counters 14 ₁ and 14 ₂ and NAND gate 15, 1 as shown in FIG.
A data set pulse divided by / 128 is obtained, which is the same as the basic of the single-phase pseudo sine wave AC circuit described above.

In FIG. 5, 9A and 9B are phases A and B.
In the phase memory, 1/4 cycle of the pulse width data at equal points obtained by dividing one cycle of the waveform stored in the address of the A phase memory 9A into 16 equal parts is shifted and stored in the address of the B phase memory 9B. That is, the data at addresses 0 to B of the A phase memory are sent to addresses 4 to F of the B phase memory, the data of addresses C to F of the A phase memory are sent to addresses 0 to B of the B phase memory.
The B-phase memory 9A and the B-phase memory 9 are stored after shifting to B
The same address line of B is connected to each other. As a result, FIG.
As shown in, the data terminal DB0 of the B-phase memory 9B
The pulse width data output to DB7 is data that is phase-shifted by an electrical angle π / 2 with respect to the pulse width data output to the data terminals DA0 to DA7 of the A-phase memory 9A shown in FIG. A two-phase pseudo sine wave alternating current can be obtained.

In FIG. 5, 16A and 17A are FETs forming an A-phase inverter circuit, and the gate input of the FET 16A is the pulse No. 1 of FIG. 0-No.
The gate input of FET17A corresponds to pulse N
o. 8 to No. A pulse width signal is input from the A-phase pulse width conversion circuit 3A so as to correspond to signal 15. Also, 16
B and 17B are FETs that form a B-phase inverter circuit, and the gates of the FETs 16B and 17B have a pulse shifted from the A-phase by an electrical angle π / 2 phase from the B-phase pulse width conversion circuit 3B, similarly to the A-phase. The width signal is input. As a result, the two-phase pseudo sine wave alternating current shown in FIGS. 7A and 7B is obtained in the inverter circuit 4a and supplied to the load 5a such as a two-phase induction motor. Where FET1
6A and 16B and FETs 17A and 17B are shown in FIG.
Corresponding to + pulse signal and-pulse width signal of
A and 17A and 16B and 17B do not turn on at the same time.

In the case of a three-phase pseudo sine wave alternating current, the pulse width data is set to an integer multiple of 3 which is an equal fraction of one cycle, and the pulse width data whose phase is changed by an electrical angle of 2π / 3 is used for three U-phase, V-phase and W-phase. By storing in the memory, a three-phase pseudo sine wave alternating current can be similarly obtained.

FIG. 8 shows a three-phase pseudo sine wave AC generation circuit used for the load 5b such as a three-phase star-type induction motor. This circuit has three U-phase, V-phase and W-phase memories. 9
U, 9V, 9W, three U-phase, V-phase, W-phase pulse width conversion circuits 3U, 3V, 3W, and three-phase inverter circuit 4b
Is used, which is the same as the operation principle of the two-phase pseudo sine wave AC generation circuit in FIG.

[0033]

According to the present invention, due to the configuration, it is possible to reduce the load of calculation of the microprocessor, speed up the operation, and reduce the cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention taking a single phase as an example.

FIG. 2 is a waveform diagram of a pseudo sine wave AC voltage.

FIG. 3 is a circuit diagram of a pulse width conversion circuit.

FIG. 4 is a waveform diagram of a pseudo rectangular wave AC voltage.

FIG. 5 is a circuit diagram of an embodiment of the present invention in which two phases are taken as an example.

6 is a waveform diagram of each part of the circuit of FIG.

7 (A) and (B) are waveform diagrams of pseudo sine wave alternating current of phase A and phase B having a 90 ° phase difference.

FIG. 8 is a circuit diagram of an embodiment of the present invention in which three phases are taken as an example.

FIG. 9 is an explanatory view of the principle of conventional pseudo alternating current generation.

FIG. 10 is a block diagram of an example of a conventional pseudo AC generation circuit.

FIG. 11 is a block diagram of another example of a conventional pseudo AC generation circuit.

[Explanation of symbols]

 1 Microprocessor 2 Pulse width data output circuit 3 Pulse width conversion circuit 3A, 3B A phase, B phase pulse width conversion circuit 4, 4a, 4b Inverter circuit 5, 5a, 5b Load 9 Memory 9A, 9B A phase, B phase Memory 9U, 9V, 9W U phase, V phase, W phase memory

Claims (2)

[Claims] 1. A pulse in which one cycle of an alternating current of a sine wave or another arbitrary waveform corresponding to a command voltage is equally divided, and one cycle of a pulse width value corresponding to a voltage value at each of the equally divided points is set as one group. As the width data, it includes a non-volatile memory storing a plurality of groups corresponding to a plurality of command voltages, and the pulse width data of the group corresponding to this is output from the microprocessor etc. by a voltage command output from the microprocessor etc. A pulse width data output circuit repeatedly output from the non-volatile memory at fixed time intervals corresponding to the frequency command, and a group of pulse width data corresponding to the voltage command output from the output circuit correspond to the frequency command. A pulse width conversion circuit that repeatedly converts a pulse width signal at regular time intervals and a pulse width signal output from the pulse width conversion circuit A pseudo-waveform AC generation circuit by pulse width modulation consisting of an inverter circuit that exchanges AC with a similar waveform. 2. A pulse in which one cycle of an alternating current having a sine wave or other arbitrary waveform corresponding to a command voltage is equally divided, and one cycle of a pulse width value corresponding to a voltage value at each of the equally divided points is set as one group. As the width data, a basic phase non-volatile memory storing a plurality of groups corresponding to a plurality of command voltages, and pulse width data for each group corresponding to a plurality of command voltages stored in the non-volatile memory are defined. A plurality of non-volatile memories according to a voltage command output from a microprocessor or the like. Is selected with the same address line, and the pulse width data of the multi-phase group corresponding to the selected voltage command is used as the frequency command output from the microprocessor or the like. A pulse width data output circuit for repeatedly outputting from the plurality of nonvolatile memories at corresponding corresponding constant time intervals, and pulse width data of a group for multiple phases corresponding to a voltage command output from the output circuit, the frequency command. And a pulse width conversion circuit for repeatedly converting into a multi-phase pulse width signal at a constant time interval, and an inverter circuit for exchanging the multi-phase pulse width signal output from the pulse width conversion circuit into a pseudo-waveform multi-phase AC. An alternating current generation circuit of pseudo waveform by a pulse width modulation signal consisting of.