JPH06112832A - A/d converter and signal processor employing the same - Google Patents

Abstract

PURPOSE:To provide a function (VOX function) detecting the existence of an input analog signal sound on the A/D converter. CONSTITUTION:A voice input voltage 5 is monitored by using plural voltage comparators 1-n in the inside of the A/D converter, a threshold level discrimination circuit 21 generates a signal 7 used to inform non-voice when the input voltage is less than a threshold voltage and voiced sound when the input voltage is in excess of the threshold voltage and a power supply for a circuit section whose operation is not required is controlled to be suppressed in the case of non-voice. Thus, the control of VOX having been implemented by a microprocessor in a conventional A/D converter for a mobile radio communication terminal equipment employing the A/D converter is implemented by the A/D converter on behalf of the microprocessor to relieve the load of the microprocessor and the cost and power consumption are reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter and a signal processing apparatus using the AD converter, and more specifically, an AD converter whose operation mode changes depending on the level of an input analog signal and a mobile radio communication terminal using the AD converter. The present invention relates to a device for processing an audio signal.

[0002]

2. Description of the Related Art A mobile radio communication system is composed of mobile radio terminals that perform radio communication with a fixed base station. A mobile wireless terminal carried by a user mainly uses a battery as a power source thereof in order to enhance portability. Therefore, the continuous use time of such a mobile radio terminal is governed by the life of the battery, like other battery-operated devices. Therefore, various means for reducing power consumption are adopted in mobile radio terminals, among which VOX (Voice Operated
Transmitter Voice OperatedTra
There is a so-called nsmitter). This is to reduce power consumption in a wireless device by putting the transmitter in an inoperative state when there is no audio signal to be transmitted.

Generally, in a digital mobile radio terminal, the function of this VOX is a digital signal processor (D
(Abbreviated as SP) judges whether there is voice or not by comparing the voice signal converted into the digital value input from the AD converter in the voice input system with the reference value, and determines whether the voice is present or not.
N / OFF is controlled. For details of this, for example, “GSM 06.32 standard version 1.
5.0 ”.

[0004]

However, when the processing of the VOX function is performed by the digital signal processor, the time required for the processing inevitably oppresses other signal processing, and a certain amount is fixed within a predetermined time. It is necessary to increase the processing speed of the digital signal processor in order to process the signal. Increasing the processing speed requires high voltage and high power consumption, is contrary to the purpose of power saving, and an expensive DSP must be used. Accordingly, it is an object of the present invention to provide a circuit means having the function of silence detection that reduces the load on the digital signal processor. Another object of the present invention is to provide an audio signal processing device which consumes less power and reduces the device cost.

[0005]

In order to achieve the above object, the present invention has realized an AD converter for converting an analog signal into a digital signal capable of processing the VOX function. That is, the AD converter of the present invention compares a sample and hold circuit for sampling and holding an analog signal, a converter circuit for quantizing the output of the sample and hold circuit into a code signal, and an output of the sample and hold circuit with a threshold value. ,
A detection means for detecting the presence or absence of voice in the analog signal by a continuous number equal to or less than a threshold value or more and a means for notifying the output of the detection means to the outside are provided. Further, means for limiting the operation of the AD converter itself to reduce power consumption when the analog input is silent is provided.

A voice signal is converted into a digital signal A
When the AD converter of the present invention is used in a signal processing device having a D converter, and a means for comparing a reference voltage having a value serving as a criterion for judging whether there is sound or a sound with an analog input is provided to judge that there is no sound. The A / D converter itself and other parts of the signal processing device, which consume power, are provided with means for limiting the power. The AD converter is not particularly limited, and a successive approximation type,
It can be configured by a parallel comparison type or pipeline type AD converter.

[0007]

According to the AD converter of the present invention, the presence / absence of a voice signal can be detected by an AD converter having a simpler structure than that of a digital signal processor, and the AD converter is detected by the detection signal of the presence / absence of a voice signal. The power consumption of the AD converter can be reduced by controlling the opening / closing operation of the power supply of the AD converter so that the AD conversion is performed only when there is an audio signal. Furthermore, the AD converter of the present invention is used in a signal processing device having an audio signal processing unit such as a mobile radio terminal,
By using the detection signal of the presence or absence of the audio signal to control the opening / closing operation of the power supply of the AD converter and other circuit parts, power saving of the mobile radio terminal can be performed, and the mobile radio terminal is used. Since the VOX processing of the DSP is reduced and the speedup for that is not required, the cost of the device can be reduced.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. For simplification of description, a state in which each signal line is active is represented by “H”, and an inactive state is represented by “L”. FIG. 1 is a block diagram showing the configuration of a first embodiment of an AD converter according to the present invention. In this example,
It is composed of a successive approximation type AD converter. The clock control circuit is omitted in FIG. 1 for simplification. FIG. 3 is a timing chart of the successive approximation AD converter for explaining the operation of the embodiment shown in FIG.

The operation of each unit will be described. The input analog signal 5 is sampled by the sample and hold circuit 4,
It is stored and held for one conversion cycle. The voltage comparator 1 compares the voltages supplied from the sample and hold circuit 4 and the DA converter 3 and supplies the result to the successive approximation logic circuit 2. Where some time n sample values of the analog signal to the hold circuit 4 is stored V _IN (n), when the value of the output of the DA converter 3 and V _R (n), the voltage comparator 1 V _IN (n)> output at _{V R (n) ... (1} ) is to be the "H".

The successive approximation logic circuit 2 stores the output of the voltage comparator 1 and controls the DA converter 3 according to the value to generate a new reference voltage to be supplied to the voltage comparator 1. Such a cycle of operation is referred to as one conversion operation, and this conversion operation is performed by the number of bits required for conversion digital output. For example, when the final resolution is 8 bits and there is one voltage comparator as in this example, as shown in the timing chart of FIG.
That is, a sample period for converting one sample value into a code signal is formed.

In the initial state, the successive approximation logic circuit 2 performs the operation required for normal AD conversion and simultaneously monitors the AD conversion result. The successive approximation logic circuit 2 compares the conversion result V _IN (n) with the threshold value V _TH1, and a plurality of sample periods (T1) are continuously established where the condition of V _IN (n) <V _TH1 (2) is established. Then, the threshold judgment signal 7 is set to "H" which means significant. For example, if the threshold value V _TH1 is set to a small value, the AD converter itself can notify the outside that the analog input is interrupted at that time.

While the threshold judgment signal 7 is "H", D
The A converter 3 is controlled, and the output of the DA converter 3 is set to the threshold value V _TH2.
Fixed to. After fixing to the threshold value V _TH2 , only the conversion operation of a specific cycle (for example, LSB in FIG. 3) in each conversion cycle is performed, and the other parts, other conversion operations (from MSB to 7th)
To stop. By stopping the operation in this way, power consumption is reduced. When a plurality of sample periods (T2) in which the condition of V _IN (n + k)> V _TH2 (3) is established continuously, the original state, that is, the normal sequential sequence shown in the timing chart of FIG. Return to comparative AD conversion. In this embodiment, the LSB (least significant bit) in each conversion cycle
The conversion result and the threshold value are compared during the conversion operation.
FIG. 3B is an example in which the threshold value determination signal 7 is immediately set to "H" when the state of the expression (2) occurs. When the digital output is determined by the conversion operation of (i) in the figure and the condition of Expression (2) is satisfied, the threshold determination signal 7 is set to "H" and the output of the DA converter 3 is fixed to the threshold V _TH2 . After that, the threshold value V _TH2 is compared with the analog input during the conversion operation corresponding to the LSB of each conversion cycle. FIG. 3C is an example of a case where the state of the expression (3) occurs, and shows a case where the normal state is immediately restored when the state of the expression (3) is established.

FIG. 2 is a block diagram showing the structure of the successive approximation logic circuit 2 shown in FIG. The operation of each part will be described. The shift register 8 fetches and stores the output 15a of the voltage comparator 1 for each conversion operation of the AD converter. When the digital output 6 is a parallel output, the shift register 8 takes in a predetermined number of bits, outputs it as the digital output 6 at a time, and stores it in the latch 12b. After that, the shift register 8 erases its own contents and starts taking in the next conversion cycle. If the digital output 6 is a serial output,
The output 15a of the voltage comparator 1 is stored in the shift register 8 and at the same time taken in by the latch 12b, which is output as the digital output 6. In this way, one bit is output for each conversion operation.

When one conversion cycle ends, the digital comparator 9a compares the value stored in the shift register 8 with the value stored in the storage device 10a. Here, the output of the shift register 8 is the analog input V _IN (n),
The value stored in the storage device 10a is the threshold value V _TH1 . The digital comparator 9a sets the output to "H" when the condition of the equation (2) occurs. When the output of the digital comparator 9a is “H”, the value of the counter 11a increases by 1,
In the case of "L", the content is cleared. That is, the number of times that the output of the digital comparator 9a becomes "H" in a continuous conversion cycle is counted. The digital comparator 9b is a counter 11a
Is compared with the value stored in the storage device 10b, and when the output of the counter 11a exceeds the value of the storage device 10b, the output is set to "H". Here, the value stored in the storage device 10b is the threshold value T1. If the waiting time is not required after the condition of Expression (2) is satisfied, this part is not necessary. Alternatively, the value T1 of the storage device 10b may be set to 0.

The output of the digital comparator 9b is given to the latch circuit 12a. The latch circuit 12a stores the output of the digital comparator 9b. The output of the latch circuit 12a is output as the threshold value judgment signal 7, and the AND circuit 1
4a. The output 15a of the voltage comparator 1 is added to the other input of the AND circuit 14a. The output of the AND circuit 14a is input to the counter 11b, and the counter 11b counts how many conversion cycles the output of the AND circuit 14a has become "H". The output of the counter 11b and the output of the storage device 10c are input to the digital comparator 9c, and when the output of the counter 11b becomes larger than the value of the storage device 10c, the output becomes "H". The value of the storage device 10c is T2, which is a reference value of how many times the state of the periodic expression (3) is determined to determine that the input is restored.

The output of the digital comparator 9c is the counter 11
It is connected to the clear terminals of a and 11b and the latch circuit 12a, and when this output becomes "H", the output of each circuit becomes "L". Therefore, the threshold determination signal 7 also becomes "L". The DA converter control circuit 13 normally receives the output of the shift register 8 and receives the reference voltage V for the next conversion operation.
_The control word required to generate _R (n) is generated and output as the DA converter control signal 16. However, the latch circuit 1
When the output of 2a is "H", the DA converter 3 is controlled so that V _R (n) = V _T2 (4) at all times.

If V _IN (n) <V _T2 (5) in this state, there is no change in the state, and if V _IN (n)> V _T2 (6), the output of the voltage comparator 1 15a becomes "H",
In response to this, the output of the AND circuit 14a also becomes "H",
As described above, if the state continues for the conversion cycle of the value T2 stored in the storage device 10c, the threshold value determination signal 7
Becomes "L".

FIG. 4 is a block diagram showing the configuration of the second embodiment of the AD converter according to the present invention. This embodiment is AD
The converter is composed of a parallel comparison type AD converter.

The operation of each part will be described. A reference voltage is applied to the reference voltage input terminals 17a and 17b. The reference voltage V _RT is applied to 17a, and the reference voltage V _RB is applied to 17b.
The potential difference between the reference voltages at the two terminals is divided by the ladder resistance formed by the resistor 18, and the divided reference voltage is supplied to one input of the voltage comparator 1. The reference voltage supplied to the i-th voltage comparator is V _Ri . The voltage comparator 1 compares the reference voltage V _Ri with V _IN given from the analog input 5, and if V _Ri <V _IN (7), sets the output to “H”. Therefore, the outputs of the voltage comparator groups 1-1 to 1-6 are “H” on the low reference voltage V _Ri side.
Therefore, the high reference voltage side is “L”. The plurality of EXOR circuits 19-1 to 9-6 detect a point where the outputs of the voltage comparator groups 1-1 to 1-6 change from “H” to “L”, and only the output of the EXOR circuit in that portion is detected. It becomes "H". The encoder circuit 20 receives the EXOR output, converts the position number of the output which has become “H” into a digital value, and outputs it as a digital output 6.

On the other hand, the output of the voltage comparator 1-5 in the figure is
The output 15b of the voltage comparator is given to the threshold value judgment circuit 21. The reference voltage supplied to the voltage comparator 1-5 is V _Ri = V _T1 (8). Further, the output of the voltage comparator 1-1 is given to the threshold value judgment circuit 21 as the voltage comparator output 15c. The reference voltage supplied to the voltage comparator 1-1 is V _Rii = V _T2 (9). The threshold value judgment circuit 21 outputs the threshold value judgment signal 7 when the voltage comparator output 15b continues to be “L” for a certain conversion cycle, that is, when the state of V _IN <V _T1 (10) continues for T1 cycles. H ". Further, when the threshold judgment signal is "H" and the voltage comparator output 15c continues to be "H" during the T2 conversion cycle, that is, when the condition of V _IN > V _T2 (11) continues, the threshold judgment signal 7 To "L".

FIG. 5 is a block diagram showing the configuration of the threshold value judgment circuit 21 of FIG. The operation of each part will be described. The output 15b of the voltage comparator 1-5 is inverted by the NOT circuit 24 and ANDed with the clock signal 23 synchronized with the conversion operation of the AD converter main body by the AND circuit 14b. The counter 11c counts the number of conversion cycles in which the result becomes "H". That is, the number of conversion cycles in which the voltage comparator output 15b is "L" is counted. The digital comparator 9d outputs the value of the output of the counter 11c and the value T stored in the storage device 10d.
1 is compared, and when the output of the counter 11c becomes large, the output is set to "H". The latch 12c latches the output of the digital comparator 9d. The output is output as the threshold determination signal 7.

On the other hand, the output 15c of the voltage comparator 1-2 is A
It is input to the ND circuit 14c. The clock signal 23 and the threshold value determination signal 7 are also input to the AND circuit 14c. A
The output of the ND circuit 14c is given to the counter 11d. That is, when the threshold determination signal 7 is “H”, the voltage comparator output 1
The number of cycles in which 5c is "H" is counted. The output of the counter 11d and the value of the storage device 10e are given to the digital comparator 9e, and when the output of the counter 11d exceeds the value T2 stored in the storage device 10e, the digital comparator 9e.
Output becomes "H". The output of the digital comparator 9e is given to itself, the counter 11c, and the latch circuit 12c as a reset signal. As a result, the threshold judgment signal 7 is also cleared. Further, while the threshold value judgment signal 7 is “H”, the operations other than the threshold value judgment circuit 21 and the voltage comparator 1-2 in FIG. 4 are stopped. This can be realized by, for example, stopping the supply of the clock to the circuit. By doing so, power consumption can be reduced.

FIG. 6 is a block diagram showing the configuration of the third embodiment of the AD converter according to the present invention. This embodiment is composed of a pipeline type AD converter. The operation of each part will be described. The input analog signal 5 supplied to the first sub AD converter block 29a is stored in the sample hold circuit 4. The sub A / D converter 24a AD-converts the output of the sample and hold circuit 4, and outputs an m (integer) bit digital value as the sub A / D converter output 26a. The sub D / A converter 25a outputs the output 26 of the sub A / D converter.
A is DA converted and an analog signal is output.

Output of sample hold circuit 4, sub DA
The output of the converter 25a and the output 26a of the sub A / D converter are given to the second sub A / D converter block 29b. The residual amplifier 28a is connected to the output of the sample and hold circuit 4 and the sub D
The difference between the outputs of the A converter 25a is obtained and stored. The output logic circuit 27a also stores the output 26a of the sub A / D converter. In this way, when all outputs are completed, the first sub A / D converter block 29a takes in a new analog input 5 to the sample hold circuit 4 and starts the next conversion operation.

On the other hand, the second sub AD converter block 29b
Performs AD conversion on the output of the residual amplifier circuit 28a. The sub AD converter 24b AD-converts the output of the residual amplification circuit 28a,
The n-bit sub-AD converter output 26b is output. The sub D / A converter 25b and the output logic circuit 27a receive it, and the sub D / A converter 25b converts it to an analog value again and the output logic circuit 27a outputs the stored output of the sub A / D converter block 29a. And synthesize.
The output of the residual amplification circuit 28a, the output of the sub D / A converter 25b, and the output of the output logic circuit 27a are sent to the third sub A / D converter block. Third sub AD converter block 29
When c receives these values, the second sub A / D converter block 29b receives a new value from the first sub A / D converter block 29a and starts the next conversion operation.

The residual amplification circuit 28b is the residual amplification circuit 28a.
Of the sub DA converter 25b and the output of the sub DA converter 25b are amplified and stored. The sub A / D converter 24c is the residual amplification circuit 2
The output of 8b is AD-converted and a p-bit sub-AD converter output 26c is output. The output logic circuit 27b synthesizes the m + n-bit output and the p-bit sub AD converter output, which have already been obtained, and outputs them as the m + n + p-bit digital output 6 to the outside.

FIG. 7 is a timing chart showing the operation of the AD converter of FIG. In the present embodiment, the sub AD converter 24a uses the AD converter of the first or second embodiment, outputs the threshold value determination signal 7 according to the set threshold value, and the second, Power consumption is reduced by stopping the operation of the third sub A / D converter block. Although the three embodiments of the AD converter according to the present invention have been described above, it goes without saying that they can be realized by other circuit configurations and other methods. Also V
There is no problem even if the magnitude relationship between _Ri and _VRii is reversed, and it is possible to realize even with the same value.

FIG. 8 is a block diagram showing a configuration example of an embodiment of a mobile radio terminal according to the present invention. In the figure, 30 is an antenna, 31 is a high frequency signal processing unit, 32 is a modulation unit, 33 is a demodulation unit, 34 is a baseband signal processing unit, 35 is a synchronization bit addition circuit, 36 is a synchronization detection unit, 37 is a scrambler, 38 Is a descrambler, 39 is an encoder, 40 is a decoder, 41 is an AD converter, 42 is a DA converter, 43 is a microphone, 44 is a speaker, 45 is an input / display unit, 46
Is a microprocessor.

The present embodiment is the same as the conventionally known mobile radio terminal except for the configurations of the AD converter 41 and the silence detection signal 47, but the function of each part will be briefly described. The audio signal input from the microphone 43 is converted into a digital signal by the AD converter 41 in the baseband signal processing unit 34. The digital signal is subjected to processing such as compression by the encoder 39, processing such as encryption by the scrambler 37, framing processing by the synchronization bit adding circuit 35, and sent to the high frequency signal processing unit 31. In the high frequency signal processing section 31, the antenna 30 is passed through the modulation section 32.
Is output as antenna power.

On the other hand, the antenna power received by the antenna 30 passes through the demodulation section 33 of the high frequency signal processing section 31 and is given to the synchronization detection section 36 of the baseband signal processing section 34.
The received signal synchronized here is subjected to processing such as decryption by the descrambler 38, subjected to signal expansion by the decoder 40, converted into an analog signal by the DA converter 42, and converted into an audio signal by the speaker 44. Is output. The microprocessor 46 processes numerical operations and the like required in each digital processing.

In the conventional digital mobile radio terminal, VOX is used.
The processing was mainly performed by the microprocessor 46,
In this embodiment, processing is performed in the AD converter 41. As the AD converter 41, any of the AD converters described in the first to third aspects of the present invention is used. Here, the threshold value V _T1 is set to the silence determination reference value, and the threshold value V _T2 is set to the reference value for determining that the silence state has returned to the normal state.
The times T1 and T2 are set appropriately. Then, when the voice input from the microphone 43 is cut off, the AD converter 41 detects it and sets the silence detection signal 47 to "H". On the contrary, when the voice is input again from the silent state, the silent detection signal 47 becomes "L" to notify it. When the silence detection signal 47 is “H”, a part of the circuit inside the AD converter 41, the modulator 32, the synchronization bit addition circuit 35, and the scrambler 37.
And the power consumption part of the encoder 39 is cut off. Although the above-mentioned embodiment is a digital mobile radio terminal, the present invention can be applied to a signal processing circuit which uses a battery as a power source and A / D converts and processes voice.

[0032]

As described above, according to the present invention, A
By adding a simple circuit to the D converter, the AD converter itself can have a function of judging the presence or absence of input, and the AD converter can be used in a signal processing device such as a digital mobile radio communication terminal. As a result, the AD converter can perform the VOX processing that was conventionally performed by the microprocessor, the load on the microprocessor can be reduced, and the cost of the microprocessor can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a successive approximation type AD converter according to the present invention.

FIG. 2 is a block diagram showing a configuration of a successive approximation logic circuit 2 shown in FIG.

FIG. 3 is a diagram showing a timing chart of the successive approximation type AD converter of the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of a parallel comparison type AD converter according to a second embodiment of the present invention.

5 is a block diagram showing a configuration of a threshold value judgment circuit 21 in FIG.

FIG. 6 is a pipeline type A according to a third embodiment of the present invention.
It is a block diagram which shows the structure of a D converter.

FIG. 7 is a diagram showing a timing chart of the pipeline type AD converter of the embodiment of FIG.

FIG. 8 is a block diagram showing a configuration of a wireless communication terminal according to a fourth exemplary embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Voltage comparator, 2 ... Successive approximation logic circuit, 3 ... DC converter, 4 ... Sample hold circuit, 5 ... Analog input,
6 ... Digital output, 7 ... Signal threshold judgment signal,
8 ... Shift register, 9a-9e ... Digital comparator, 10a-10e ... Storage device, 11a
-11d ... Counter, 12a-12c ... Latch circuit, 13 ... DC converter control circuit, 14a
˜14c ... AND circuit, 15a to 15c ... Voltage comparator output, 16 ... DC converter control output, 17a, 17b ...
Reference voltage input terminal, 18 ... Resistor, 19 ... EXOR circuit, 20 ... Encoder circuit, 21 ... Knowledge threshold determination circuit, 22 ... Fixed bias terminal, 23 ... Clock signal, 24a-2
4c ... Sub AD converter, 25a, 25b ... Sub DC converter, 26a to 26c ... Sub AD converter output, 27
a, 27b ... Output logic circuit, 28a, 28b ... Residual amplification circuit, 29a-29c ... Sub AD converter block, 30 ... Antenna, 31 ... High frequency signal processing section,
32 ... Modulator, 33 ... Demodulator,
34 ... Baseband signal processing unit, 35 ... Sync bit addition circuit, 36 ... Sync detection unit, 37 ... Scrambler, 38 ... Descrambler, 3
9 ... Encoder, 40 ... Decoder,
41 ... AD converter, 42 ... DC converter, 43 ... Microphone, 44 ... Speaker, 45 ... Input and display section, 46 ... Microprocessor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Murakami 1-280, Higashi Koikeku, Kokubunji, Tokyo Stock company Hitachi Central Research Laboratory (72) Inventor Masao Horita 1-280, Higashi Koikeku, Kokubunji, Tokyo Central Research Laboratory of Hitachi, Ltd.

Claims (6)

[Claims] 1. An AD converter for converting an analog signal into a digital signal, a sample and hold circuit for sampling and holding the analog signal, a conversion circuit for quantizing the output of the sample and hold circuit into a code signal, and the sample. An AD converter having a detection means for comparing the output of the hold circuit with a threshold value and detecting the level of the analog signal by a continuous number equal to or less than the threshold value, and a means for notifying the output of the detection means to the outside. 2. The AD converter according to claim 1, further comprising means for notifying driving of the conversion circuit when the level of the analog signal is low by means for notifying the output of the detection means to the outside. AD converter. 3. The AD converter according to claim 1, wherein the conversion circuit compares the output of the sample hold circuit with the output voltage of the DA converter, and the output of the voltage comparator. The successive approximation logic circuit as an input and the output of the successive approximation logic circuit are used as inputs of the DA converter, and the detection means compares the conversion result at the time of the conversion operation of the specific bit of the successive approximation logic circuit with the threshold value. AD converter composed of a circuit for 4. The AD converter according to claim 1, wherein the conversion circuit comprises a plurality of voltage comparators having different reference voltages and outputs of the sample hold circuit as inputs, and the plurality of voltage comparators. A reference voltage equal to the threshold among the plurality of voltage comparators, the logic circuit specifying and coding a voltage comparator to which a reference voltage close to the output of the sample hold circuit is applied from the input. A parallel-comparison type AD converter having means for inputting the output of the voltage comparator to which is added to determine the number of significant samples and means for comparing the number of samples with a predetermined number. . 5. The AD converter according to claim 1 or 2, wherein the AD conversion circuit is composed of a pipeline type AD conversion circuit, and the element A in the pipeline type AD conversion circuit.
An AD converter using the AD converter according to the first or second aspect as a D conversion circuit. 6. A battery as a power source, an AD converter that uses the battery as a power source and converts an analog signal into a digital signal, and a processing circuit that uses the battery as a power source and processes an output of the AD converter. In the signal processing device, the above A
An AD according to any one of claims 1 to 5 as a D converter.
A signal processing device having means for stopping the driving of a processing circuit for processing the output of the AD converter, when the converter is used and it is detected that the level of the analog signal is low.