JPH06112449A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To lessen the number of transistors and the number of program points so far as they are required regarding a semiconductor integrated circuit device, in particular regarding the constitution of the circuits of the fundamental cells of a programmable FPGA, and to constitute multiple types of fundamental logic circuits. CONSTITUTION:A semiconductor integrated circuit device is provided with first to fourth transistors T1 to T4 and a plurality of various program switches PD1, PD2, PS1, PS2 and P1 to P14, each gate 9 of the transistors T1 to T4 is connected to an input wiring Lin and extraction electrodes SD1 to SD6 of sources or drains of the transistors T1 to T4 are connected to first and second power conductors VDD and VSS, frist and second output wirings Lout 1 and Lout 2, first and second spare wirings LP1 and LP2 for high potential side use or first and second spare wirings LN1 and LN2 for low potential side use in such a way as to make the first and second program switches PD1 and PD2 for high potential side use, the first and second program switches PS1 and PS2 for low potential side use and the first to 14th program switches P1 to P14 interpose between them.

Description

Detailed Description of the Invention

[Table of Contents] Industrial Application Field Conventional Technology (FIG. 78) Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 to 12) Action Example (1) First Example (Figs. 13 to 15) (2) Description of the second embodiment (Fig. 16) (3) Description of the third embodiment (Figs. 17 to 33) (4) Description of the fourth embodiment (Fig. 34 to 53) (5) Description of fifth embodiment (Fig. 54 (a)) (6) Description of sixth embodiment (Fig. 54 (b)) (7) Description of seventh embodiment (Fig. 55 (a)) (8) Description of eighth embodiment (FIG. 55 (b)) (9) Description of ninth embodiment (FIG. 56) (10) Description of tenth embodiment (FIG. 57) (11) Description of the eleventh embodiment (FIGS. 58 to 67) (12) Description of the twelfth embodiment (FIGS. 68 to 77)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of the circuit configuration of a basic cell of a programmable gate array (hereinafter referred to as FPGA).

In recent years, with the demand for higher integration, higher density and higher functionality of semiconductor integrated circuit (hereinafter referred to as LSI) devices, FPGAs (Field Programmable Gate Arrays) have attracted attention as programmable ASICs at the user's hand. Has been done. The FPGA can be provided to the user at an early stage, and is mainly used as a chip for new development and a prototype of an electronic product.

For example, in an FPGA, an AND-OR plane is programmed by a fuse (or an antifuse), and a PLD (Programmable Logic Device) is programmed.
Alternatively, there is a type in which the circuit block and the switch box are programmed by the information stored in the memory.

Further, like the conventional gate array, there is a type which is composed of a circuit block row and a wiring area and is programmed by a fuse or an antifuse. According to this, a basic cell that allows only a specific logic circuit to be combined is applied, and it is the minimum unit. Therefore, the number of transistors forming the basic cell increases.

Further, the transistor pair tile portion and R
In the basic cell whose minimum unit is two types, that is, the AM logic tile portion, the circuit usage rate decreases when the usage rates of the number of macros provided in the chip are different.

Therefore, the number of transistors and the number of program points are reduced as much as necessary without depending on many transistors involved in the circuit configuration of the basic cell,
There is a demand for an apparatus capable of forming various kinds of basic logic circuits by performing the combination and the program processing.

[0008]

2. Description of the Related Art FIG. 78 is an explanatory diagram of a semiconductor integrated circuit device according to a conventional example and shows a configuration diagram of a logic circuit included in a basic cell of an FPGA. For example, as an ASIC that can be programmed at the user's hand, FPGA (Field Pro
The basic cells that make up the grammable gate array are I
EEE JOURNAL OF SOLID-STATE CIRCUITS VOL 24.NO
3. Logic circuits as seen in JUNE 1989 (Logic mod
ule schematic) is applicable.

In FIG. 78, according to the logic circuit, 6
Two-input AND circuit (hereinafter simply referred to as first to sixth AND circuits) AND1 to AND6, three inverter circuits (hereinafter simply referred to as first to third inverters) IN1 to IN3, 3
Two 2-input OR circuits (hereinafter simply referred to as first to third OR circuits) OR1 to OR3, one two-input NOR circuit NOR and 1
It consists of one buffer circuit BUF.

Further, it is possible to form, for example, a 3-input logic circuit, a 4-input logic circuit, a 2-input exclusive OR circuit, and a D-type latch circuit by the function of one unit of the logic circuit. A D-type flip-flop circuit can be configured by the function of two units in which two logic circuits are combined.

Wiring regions are provided between the logic circuits, and program points are provided at horizontal and vertical intersections of the wirings reaching each circuit. Further, the plurality of program points are made of antifuses or fuse elements, and it is possible to arbitrarily build a logic gate circuit at the user's hand. When a prototype of an electronic device using these FPGAs is manufactured, after verifying its operation, the chip gate array is remade and the mass production is started.

[0012]

According to the logic circuit applied to the basic cell of the conventional example, the first to sixth ANs are used.
D circuits AND1 to AND6, first to third inverters IN1 to
IN3, first to third OR circuits OR1 to OR3, and a buffer circuit BUF.

Therefore, there is a first problem that the number of transistors forming a basic cell increases. For example, assuming that one 2-input AND circuit is composed of four transistors, the first to sixth AND circuits AND1
~ AND6 requires 24 pieces, and if one inverter circuit is composed of two transistors,
The first to third inverters IN1 to IN3 require six.

Also, one two-input OR circuit and two-input NO circuit
If each R circuit is composed of four transistors, the first to third OR circuits OR1 to OR3 require twelve and the two-input NOR circuit requires four.
Further, if one buffer circuit BUF is composed of two transistors, a total of 48 transistors must be incorporated in the basic cell.

Thus, when there is a request to configure the D-type flip-flop circuit, at least 96 transistors are required since the function of the logic circuit requires two units.

Further, the basic macro (logical circuit) which is the minimum unit can realize only a specific combinational circuit such as a three-input logical circuit, a four-input logical circuit, a two-input exclusive OR circuit and a D-type latch circuit. As a result, there is a second problem in that when a logic gate circuit having many small circuits such as an inverter circuit and a two-input NAND circuit is assembled, its use efficiency (circuit utilization rate) is reduced.

As another basic cell, there is one in which the minimum unit is two types, that is, a transistor pair tile portion that realizes a combinational circuit and a RAM logic tile portion that realizes a flip-flop or the like. However, since two types of basic macros are required at the time of programming, if the usage rates of the number of macros provided in the chip differ, the circuit usage rate will decrease.

In order to shorten the programming time of the FPGA, it is desirable that the number of program points connecting the transistors forming the basic cells and the wirings leading to the transistors be small. Further, since the program point after the program processing has a contact resistance of about 50 to 500 [Ω], it is necessary to reduce the number of program points as much as possible in order to speed up the transistor operation.

The present invention was created in view of the problems of the conventional example, and does not depend on many transistors related to the circuit configuration of the basic cell, and the number of transistors and the number of program points are not limited as much as necessary. Less,
It is an object of the present invention to provide a semiconductor integrated circuit device capable of forming various kinds of basic logic circuits by performing the combination and the program processing.

[0020]

1 to 12 are principle views (Nos. 1 to 12) of a semiconductor integrated circuit device according to the present invention.

As shown in FIG. 1, the first semiconductor integrated circuit device of the present invention has first to fourth transistors T1 to T4.
And a plurality of various program switches PD1 and PD for connecting the first to fourth transistors T1 to T4 and wirings.
2, PS1, PS2, P1 to P14, and the gate G of each of the first to fourth transistors T1 to T4 is an input wiring L.
connected to in and the first to fourth transistors T1 to T
The four source or drain extraction electrodes SD1 to SD6 are the first and second high potential side program switches PD1 and PD2,
First and second low potential side program switches PS1 and PS2
And the first to the 14th program switches P1 to P14, the first and the second power supply lines VDD and VSS, the first and the second output lines Lout1 and Lout2, and the first and the second high potential side. Preliminary wirings LP1, LP2 or the first and second low potential side preliminary wirings LN1,
It is characterized in that it is connected to LN2.

In the first semiconductor integrated circuit device of the present invention, the extraction electrode SD1 of the source or drain of the first transistor T1 has the first high potential side program switch PD1 interposed therebetween. Power supply line VDD and first
Second output wiring Lout2 with the program switch P1 interposed therebetween, the first output wiring Lout1 with the second program switch P2 interposed, and the first high potential side spare wiring L.
P1 is connected to the first and second transistors T1,
The source or drain extraction electrode SD2 of T2 is connected to the first power supply line VDD via the second high potential side program switch PD2 and the first output line Lout1 via the third program switch P3. And the extraction electrode SD3 of the source or drain of the second transistor T2.
The first output wiring Lout1 with the fourth program switch P4 interposed, the second output wiring Lout2 with the fifth program switch P5 interposed, and the first program wiring Pout6 with the sixth program switch P6 interposed. High potential side spare wiring LP1
The source or drain extraction electrode SD4 of the third transistor T3 is connected to the second power supply line VSS through the first low potential side program switch PS1.
It is connected to the first output wiring Lout1 via the eighth program switch P8, the second output wiring Lout2 via the ninth program switch P9, and the first low potential side spare wiring LN1. , The third and fourth transistors T
The source or drain extraction electrodes SD5 of T3 and T4 have a second power supply line VSS with a second low potential side program switch PS2 interposed therebetween and a second output wiring with a tenth program switch P10 interposed therebetween. Connected to Lout2, and the fourth
The source or drain extraction electrode SD6 of the transistor T4 of the second output line Lout2 and the twelfth program switch P12 with the eleventh program switch P11 interposed therebetween.
Is connected to the first output wire Lout1 and the thirteenth program switch P13 to be connected to the first low potential side spare wire LN1. The first output wire Lout1 is connected to the seventh program switch Lout1. The second output wiring Lout2 is connected to the second high potential side preliminary wiring LP2 via the P7, and the second output wiring Lout2 is connected to the second low potential side preliminary wiring LN2 via the fourteenth program switch P14. It is characterized by

As shown in FIG. 2, the second semiconductor integrated circuit device of the present invention is the same as the first semiconductor integrated circuit device, except that the source or drain extraction electrode SD3 of the second transistor T2 is the third Is connected to the first power supply line VDD through the high potential side program switch PD3, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the third low potential side program switch P3.
It is characterized in that it is connected to the second power supply line VSS via S3.

Further, as shown in FIG. 3, a third semiconductor integrated circuit device of the present invention is the same as the first semiconductor integrated circuit device, but in the first semiconductor integrated circuit device, the extraction electrodes of the source or drain of the first and second transistors T1 and T2. A first bypass program switch PB1 is connected between SD1 and SD3,
A second bypass program switch PB2 is connected between the extraction electrodes SD4 and SD6 of the sources or drains of the fourth transistors T3 and T4.

As shown in FIG. 4, a fourth semiconductor integrated circuit device of the present invention is the same as the first semiconductor integrated circuit device, except that the source or drain extraction electrode SD3 of the second transistor T2 is the third Is connected to the first power supply line VDD through the high potential side program switch PD3, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the third low potential side program switch P3.
It is connected to the second power supply line VSS via S3, and the first bypass program switch PB1 is connected between the extraction electrodes SD1 and SD3 of the sources or drains of the first and second transistors T1 and T2. A second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4.

In the first to fourth semiconductor integrated circuit devices of the present invention, the first and second transistors T1,
T2 is a p-type field effect transistor, and the third and fourth transistors T3 and T4 are n-type field effect transistors.

Further, in the first to fourth semiconductor integrated circuit devices of the present invention, the various program switches PD1 to PD
It is characterized in that D3, PS1 to PS3, P1 to P14, PB1 and PB2 are composed of fuse elements, antifuse elements, and p-type or n-type field effect transistors.

Furthermore, as shown in FIG. 5, the fifth semiconductor integrated circuit device of the present invention has first to fourth transistors T1.
To T4 and a plurality of various program switches PD for connecting the first to fourth transistors T1 to T4 and wirings
1, PD2, PS1, PS2, P1 to P16, the gates G of the first to fourth transistors T1, T2, T3 and T4 are connected to the input wiring Lin, and the first to fourth transistors The source or drain extraction electrodes SD1 to SD6 of T1 to T4 are the first and second high potential side program switches PD1 and PD2, the first and second low potential side program switches PS1 and PS2, and the first to the first. 16 program switches P1
Through P16, the first and second power supply lines VDD and VSS, the first and second output lines Lout1 and Lout2, the first and second high potential side spare lines LP1 and LP2, or the first and first lines. It is characterized in that it is connected to the second low potential side spare lines LN1 and LN2.

In the fifth semiconductor integrated circuit device of the present invention, the extraction electrode SD1 of the source or drain of the first transistor T1 has the first high potential side program switch PD1 interposed therebetween. Power supply line VDD and first
Second high-potential-side spare wiring LP2 via the program switch P1 and second high-potential-side spare wiring LP2 via the second program switch P2 and the first high-potential-side spare wiring The lead-out electrode SD2 of the source or drain of the first and second transistors T1 and T2, which is connected to the line LP1, is connected to the first power supply line VDD through the second high-potential-side program switch PD2. It is connected to the second high potential side spare wiring LP2 via the third program switch P3, and the extraction electrode SD3 of the source or drain of the second transistor T2 interposes the fourth program switch P4. And the second high-potential-side spare line LP2,
The second low-potential-side spare line LN2 and the sixth program switch P6 are interposed with the fifth program switch P5 interposed.
Is connected to the first high potential side spare wiring LP1 and the source or drain extraction electrode SD4 of the third transistor T3 is connected to the first low potential side program switch PS1. The second power line VSS, the second high-potential side spare line LP2 with the eighth program switch P8 interposed, and the second low-potential side spare line LN2 with the ninth program switch P9 interposed. , The first low potential side spare line LN1 and the source or drain extraction electrodes SD5 of the third and fourth transistors T3 and T4.
However, the second power source line VSS and the tenth program switch P2 are interposed with the second low potential side program switch PS2 interposed.
10 is connected to the second high potential side spare wiring LP2, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the eleventh program switch P11.
The second low potential side preliminary wiring LN2, the twelfth program switch P12 are interposed, the second high potential side preliminary wiring LP2, and the thirteenth program switch P13 are interposed. Connected to the low potential side spare wiring LN1, the second high potential side spare wiring LP2 is connected to the seventh program switch P7, and the second low potential side spare wiring LN2 is connected to the 14th The second auxiliary wiring for high potential LP2 is connected to the program switch P14, the second auxiliary wiring for high potential LP2 is connected to the first output wiring Lout1 through the fifteenth program switch P15, and the second auxiliary wiring for low potential LN2 is connected. Is connected to the second output line Lout2 through the 16th program switch P16.

As shown in FIG. 6, the sixth semiconductor integrated circuit device of the present invention is the same as the fifth semiconductor integrated circuit device, except that the extraction electrode SD3 of the source or drain of the second transistor T2 is the third one. Is connected to the first power supply line VDD through the high potential side program switch PD3, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the third low potential side program switch P3.
It is characterized in that it is connected to the second power supply line VSS via S3.

Furthermore, as shown in FIG. 7, a seventh semiconductor integrated circuit device of the present invention is the same as the fifth semiconductor integrated circuit device, but in the fifth semiconductor integrated circuit device, the extraction electrodes of the source or drain of the first and second transistors T1 and T2. A first bypass program switch PB1 is connected between SD1 and SD3, and a second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4. Are connected.

As shown in FIG. 8, an eighth semiconductor integrated circuit device of the present invention is the same as the fifth semiconductor integrated circuit device, except that the source or drain extraction electrode SD3 of the second transistor T2 is the third Is connected to the first power supply line VDD through the high potential side program switch PD3, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the third low potential side program switch P3.
A first bypass program switch PB1 is connected to the second power supply line VSS via S3 and between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors T1 and T2. A second bypass program switch PB2 is connected between the lead-out electrodes SD4 and SD6 of the sources or drains of the third and fourth transistors T3 and T4.

Further, in the fifth to eighth semiconductor integrated circuit devices of the present invention, the first and second transistors T1 and T
2 is a p-type field effect transistor,
The fourth transistors T3 and T4 are characterized by being n-type field effect transistors.

Further, in the fifth to eighth semiconductor integrated circuit devices of the present invention, the various program switches PD1 to PD1 to
It is characterized in that PD3, PS1 to PS3, P1 to P16, PB1 and PB2 are composed of a fuse element, an antifuse element and a p-type or n-type field effect transistor.

The ninth semiconductor integrated circuit device of the present invention is shown in FIG.
, The first to eighth transistors T1 to T8
And a plurality of various program switches PD1 to PD for connecting the first to eighth transistors T1 to T8 and wirings.
4, PS1 to PS4, P1 to P22, and the gates G of the first to eighth transistors T1 to T8 are input wiring lines L.
connected to in and the first to eighth transistors T1 to T
8 source or drain extraction electrodes SD1 to SD12 are first to fourth high potential side program switches PD1 to PD4,
First to fourth low potential side program switches PS1 to PS4
It is characterized in that it is connected to the first and second power supply lines VDD and VSS and the first and second output lines Lout1 and Lout2 with the first and the twenty-second program switches P1 to P22 interposed.

In the ninth semiconductor integrated circuit device of the present invention, the extraction electrode SD1 of the source or drain of the first transistor T1 has the first high potential side program switch PD1 interposed therebetween. Power supply line VDD and first
Of the first and second transistors T1 and T2 connected to the second output wiring Lout2 via the program switch P1 and to the first output wiring Lout1 via the second program switch P2. Alternatively, the drain extraction electrode SD2 is the second high potential side program switch PD2.
Is connected to the first power supply line VDD and the first output line Lout1 via the third program switch P3, and the extraction electrode SD3 of the source or drain of the second transistor T2 is 4 program switch P4
And a second output line Lout2 with a fifth program switch P5 interposed therebetween.
The extraction electrode SD4 of the source or drain of the third transistor T3) via the sixth program switch P6.
The source or drain extraction electrode SD4 of the third transistor T3 is connected to the first power supply line VDD and the seventh program switch P7 via the third high potential side program switch PD3. The second output wiring Lout2 is connected to the first output wiring Lout1 via the eighth program switch P8, and the third and fourth output wirings Lout2 are connected to the first output wiring Lout1.
The source or drain extraction electrode SD5 of each of the transistors T3 and T4 is a fourth high potential side program switch P.
It is connected to the first power supply line VDD via D4 and the first output line Lout1 via the ninth program switch P9, and the extraction electrode SD6 of the source or drain of the fourth transistor T4 is Tenth program switch P
The output electrode SD7 of the source or drain of the fifth transistor T5 is connected to the first output line Lout1 via 10 and the second output line Lout2 via the eleventh program switch P11. The second power supply line VSS and the first low potential side program switch PS1 are interposed.
The first and second output lines Lout1 and Lout2 are connected to each other through the thirteenth program switch P12 and the fourteenth program switch P13, respectively.
Of the source or drain of the transistors T5 and T6 of the second transistor P5 is the second low potential side program switch P.
It is connected to the second power supply line VSS via S2 and the second output wiring Lout2 via the 14th program switch P14, and the extraction electrode SD9 of the source or drain of the sixth transistor T6 is Fifteenth program switch P
The second output line Lout2 with 15 in between, and the first output line Lout1 with the 16th program switch P16 in between.
Is connected to the source or drain extraction electrode SD10 of the seventh transistor T3) via the seventeenth program switch P17, and the source or drain extraction electrode SD10 of the seventh transistor T7 is The second power supply line V with the potential side program switch PS3 interposed
The first through the SS and the 18th program switch P18
Of the output wiring Lout1 and the second output wiring Lout2 via the nineteenth program switch P19, and the extraction electrode SD11 of the source or drain of the seventh and eighth transistors T7 and T8 is connected to the fourth output wiring Lout1. Second power line VSS through the low potential side program switch PS4 and the second output wiring L through the twentieth program switch P20.
The extraction electrode SD12 of the source or drain of the eighth transistor T8, which is connected to out2, is connected to the second output wiring Lout2 via the twenty-first program switch P21.
It is characterized in that it is connected to the first output wiring Lout1 through a 22nd program switch P22.

As shown in FIG. 10, the tenth semiconductor integrated circuit device of the present invention is the ninth semiconductor integrated circuit device, wherein the extraction electrode SD3 of the source or drain of the second transistor T2 is the fifth one. Is connected to the first power supply line VDD via the high potential side program switch PD5, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the sixth high potential side program switch P5.
Is connected to the first power supply line VDD through D6,
Of the transistor T6 is connected to the second power source line VSS through the fifth low potential side program switch PS5, and the source or drain of the eighth transistor T8 is connected to the source or drain of the transistor T6. SD12
Is connected to the second power supply line VSS through the sixth low potential side program switch PS6.

Further, as shown in FIG. 11, the eleventh semiconductor integrated circuit device of the present invention is the same as the ninth semiconductor integrated circuit device, except that the extraction electrodes of the source or drain of the first and second transistors T1 and T2 are included. SD1, SD3 and third and fourth
The first and second bypass program switches PB1 and PB2 are connected between the source or drain extraction electrodes SD4 and SD6 of the transistors T3 and T4, respectively.
Source or drain extraction electrodes SD7 and SD9 of the sixth transistors T5 and T6 and the seventh and eighth transistors T
7, T8 source or drain extraction electrodes SD10, S
Third and fourth bypass program switch PB between D12
3 and PB4 are connected respectively.

As shown in FIG. 11, the twelfth semiconductor integrated circuit device of the present invention is the ninth semiconductor integrated circuit device, wherein the source or drain extraction electrode SD3 of the second transistor T2 is the fifth semiconductor integrated circuit device. Is connected to the first power supply line VDD via the high potential side program switch PD5, and the source or drain extraction electrode SD6 of the fourth transistor T4 is connected to the sixth high potential side program switch P5.
Is connected to the first power supply line VDD through D6,
Of the transistor T6 is connected to the second power source line VSS through the fifth low potential side program switch PS5, and the source or drain of the eighth transistor T8 is connected to the source or drain of the transistor T6. SD12
Is connected to the second power supply line VSS via the sixth low potential side program switch PS6, and the source or drain extraction electrodes SD1 and SD3 of the first and second transistors T1 and T2. And the extraction electrodes SD4 of the source or drain of the third and fourth transistors T3, T4,
Between SD6, the first and second bypass program switches P
B1 and PB2 are connected to each other, and the extraction electrodes S of the sources or drains of the fifth and sixth transistors T5 and T6 are connected.
The third and fourth bypass program switches PB3 and PB4 are connected between D7 and SD9 and the extraction electrodes SD10 and SD12 of the sources or drains of the seventh and eighth transistors T7 and T8, respectively.

In the ninth to twelfth semiconductor integrated circuit devices of the present invention, the first to fourth transistors T1 to T are used.
4 is a p-type field effect transistor,
The eighth transistors T5 to T8 are characterized by being n-type field effect transistors.

Further, in the ninth to twelfth semiconductor integrated circuit devices of the present invention, the various program switches PD1 to PD.
6, PS1 to PS6, P1 to P22 and PB1 to PB4 are characterized by being composed of a fuse element, an antifuse element and a p-type or n-type field effect transistor.

Furthermore, a thirteenth semiconductor integrated circuit device of the present invention is configured by connecting two or more basic cells formed of the first to fourth semiconductor integrated circuit devices or by combining the basic cells to form various logic circuits. It is characterized by doing.

In the fourteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the fifth to eighth semiconductor integrated circuit devices are connected, or the basic cells are combined to form various logic circuits. It is characterized by

Further, in the fifteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the ninth to twelfth semiconductor integrated circuit devices are connected, or the basic cells are combined to form various logic circuits. Is characterized by.

In the sixteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the first to twelfth semiconductor integrated circuit devices are connected, or the basic cells are combined to form various logic circuits. The above object is achieved.

[0046]

[Operation] According to the first semiconductor integrated circuit device of the present invention, as shown in FIG.
To T4 and a plurality of various program switches PD1, PD2, PS1, PS2, P1 to P14 for connecting between them and between wirings
Is provided.

Therefore, the four transistors T1 to T4
And a total of 18 program switches PD1, PD2, PS
1, PS2, and P1 to P14 form a minimum unit basic cell. For example, among the basic cells, the first and second high potential side program switches PD1 and PD2, the first and second low potential side program switches PS1 and PS2, and the fourth and twelfth
Program processing of the fuse element, antifuse element, and p-type or n-type field effect transistor which form the program switches P4 and P12.

As a result, the source or drain extraction electrode SD1 of the first transistor T1 and the first power supply line VDD
Are connected via a first high potential side program switch PD1 and the source or drain extraction electrodes SD2 of the first and second transistors T1 and T2 and the first power supply line VDD are connected to the second high potential side. Is connected via the program switch PD2.

The source or drain extraction electrode SD3 of the second transistor T2 and the first output line Lout1 are connected via the fourth program switch P4, and the source or drain of the third transistor T3 is extracted. The electrode SD4 and the second power supply line VSS are connected via the first low potential side program switch PS1 and the extraction electrode S of the source or drain of the third and fourth transistors T3 and T4.
D5 and the second power supply line VSS are connected via the second high potential side program switch PS1. Furthermore, the source or drain extraction electrode SD6 of the fourth transistor T4 and the first output wiring Lout1 are connected to the twelfth program switch P.
Connected via 12.

This makes it possible to form an inverter circuit by the second transistor T2 made of a p-type field effect transistor and the fourth transistor T4 made of an n-type field effect transistor. From this,
18 program switches PD1, PD2, PS1, P
By appropriately programming S2 and P1 to P14, the basic logic of an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, etc., by four transistors T1 to T4. It becomes possible to configure cells.

The 7th and 14th program switches P
It is possible to connect the first output wiring Lout1 and the second output wiring Lout2 to the vertical basic cells by performing selective conduction (programming processing) of 7 and P14.

Further, according to the second semiconductor integrated circuit device of the present invention, as shown in FIG. 2, the first to fourth transistors T1 to T4 are connected to each other and a plurality of interconnections are formed. Various program switches PD1, PD2, PS1, PS2, P1
To P14, the third high potential side program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor T2 and the first power supply line VDD, and the fourth transistor A third low potential side program switch PS3 is connected between the source or drain extraction electrode SD6 of T4 and the second power supply line VSS.

Therefore, the four transistors T1 to T4
And a total of 20 program switches PD1 to PD3, PS1
.About.PS3 and P1 to P14 form a minimum unit basic cell. For example, among the basic cells, the fuses forming the first and third high potential side program switches PD1 and PD3, the first low potential side program switch PS1 and the third and twelfth program switches P3 and P12 A two-input NAND circuit can be configured by performing a programming process on the element, the antifuse element, and the p-type or n-type field effect transistor.

As a result, the number of program switches is increased by two as compared with the first semiconductor integrated circuit device, but an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit. Etc. can be combined.

Further, according to the third semiconductor integrated circuit device of the present invention, as shown in FIG. 3, a plurality of first to fourth transistors T1 to T4 and a plurality of interconnections between them and between wirings are connected. Various program switches PD1, PD2, PS1, PS2, P
1 to P14 are provided, and the first and second transistors T1,
A first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of T2,
A second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4.

Therefore, the four transistors T1 to T4
And a total of 20 program switches PD1, PD2, PS
1, PS2, P1 to P14, PB1 and PB2 form a minimum unit basic cell. In addition, the first bypass program switch PB1 causes the first and second transistors T
1, T2 source or drain extraction electrodes SD1, SD3
Can be directly connected to each other without using the first output wiring Lout1. Similarly, the second bypass program switch PB2 can be used to draw out the source or drain extraction electrodes of the third and fourth transistors T3 and T4. It becomes possible to directly connect between SD4 and SD6 without using the second output wiring Lout2.

As a result, the number of program switches is increased by 2 compared with the first semiconductor integrated circuit device, but 2 or 3 of the basic cells are connected to form a 4-input AND / OR inverter circuit or a 6-input AND. It is possible to efficiently use the first and second bypass program switches PB1 and PB2 when configuring an OR inverter circuit or the like.

Further, according to the fourth semiconductor integrated circuit device of the present invention, as shown in FIG.
The third high-potential-side program switch PD3 between the source or drain extraction electrode SD3 and the first power supply line VDD.
Further, a third low potential side program switch PS3 is connected between the source or drain extraction electrode SD6 of the fourth transistor T4 and the second power supply line VSS. The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors T1 and T2, and the sources of the third and fourth transistors T3 and T4 or A second bypass program switch PB2 is connected between the drain extraction electrodes SD4 and SD6.

Therefore, the four transistors T1 to T4
And a total of 22 program switches PD1 to PD3, PS1
.About.PS3, P1 to P14, PB1 and PB2 form a minimum unit basic cell. For example, among the basic cells, first, third high potential side program switches PD1, PD3,
The first low potential side program switch PS1 and the third and twelfth
Of the program switch P3, P12, the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor are programmed to perform two-input N
It becomes possible to configure an AND circuit.

As a result, the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, but an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit. Etc. can be combined. Also, two basic cells are connected to form a 3-input NAND circuit and a 3-input NOR circuit.
It is possible to configure a circuit, a 4-input NAND circuit, a 4-input NOR circuit, a 4-input AND / OR inverter circuit, and a 6-input AND / OR inverter circuit by connecting three basic cells.

Further, according to the fifth semiconductor integrated circuit device of the present invention, as shown in FIG. 5, a plurality of first to fourth transistors T1 to T4 are connected to each other and a plurality of wirings are connected to each other. Various program switches PD1, PD2, PS1, PS2, P
1 to P14 are provided, the second high potential side spare wiring LP2 is connected to the first output wiring Lout1 via the fifteenth program switch P15, and the second low potential side spare wiring LN2 is provided.
Is connected to the second output wiring Lout2 through the 16th program switch P16.

Therefore, the four transistors T1 to T4
And a total of 20 program switches PD1, PD2, PS
1, PS2, and P1 to P16 form a minimum unit basic cell. In addition, the fifteenth and sixteenth program switches P15,
By performing selective conduction (program processing) of P16,
Second spare line LP2 for high potential side and first output line Lout1
And the second auxiliary wiring LN2 for the low potential side.
And the second output line Lout2 are connected to each other,
By deselecting the 5 and 16 program switches P15 and P16 (non-program processing), the first and second output wirings Lout1,
It is possible to give Lout1 a through wiring function.
The through wiring function is a wiring that passes the basic cell in the horizontal direction, and is effective in the case of communicating with the basic cells adjacent in the horizontal direction or when the shortest wiring distance is required.

As a result, the number of program switches is increased by two as compared with the first semiconductor integrated circuit device, but an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input circuit while applying the through wiring function. A NAND circuit, a two-input NOR circuit, etc. can be combined. It should be noted that 2 of the basic cells are connected and 3
Input NAND circuit, 3-input NOR circuit, 4-input NAND circuit
Circuit, 4-input NOR circuit, 4-input AND / OR inverter circuit, or 3-input AND
It becomes possible to configure an OR inverter circuit or the like.

Further, according to the sixth semiconductor integrated circuit device of the present invention, as shown in FIG. 6, the first to fourth transistors T1 to T4 are connected to each other and to a plurality of interconnections between them. Various program switches PD1, PD2, PS1, PS2, P1
To P14, the source or drain extraction electrode SD3 of the second transistor T2 is connected to the first power supply line VDD through the third high potential side program switch PD3, and the fourth transistor T4 is connected. The source or drain extraction electrode SD6 is connected to the second power supply line VSS through the third low potential side program switch PS3.

Therefore, the four transistors T1 to T4
And a total of 22 program switches PD1 to PD3, PS1
.About.PS3 and P1 to P16 form a minimum unit basic cell. In addition, like the fifth semiconductor integrated circuit device,
By the non-selection (non-program processing) of the 15 and 16 program switches P15 and P16, the first and second output wirings Lout1,
It is possible to give Lout1 a through wiring function.

As a result, the number of program switches is increased by 4 as compared with the first semiconductor integrated circuit device, but
Inverter circuit and inverter (power type) while applying the through wiring function, like the semiconductor integrated circuit device
Circuit, transmission gate circuit, two-input NAND
A circuit, a two-input NOR circuit, etc. can be combined. In addition, by connecting the two basic cells, a 3-input NAND circuit,
3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit
It is possible to configure a circuit, a 4-input AND / OR inverter circuit, and a 6-input AND / OR inverter circuit by connecting three basic cells.

Furthermore, according to the seventh semiconductor integrated circuit device of the present invention, as shown in FIG. 7, the first to fourth transistors T1 to T4 are connected to each other and to a plurality of interconnections between them. Various program switches PD1, PD2, PS1, PS2, P
1 to P14 are provided, and the first and second transistors T1,
The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of T2, and the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4. The second bypass program switch PB2 is connected.

Therefore, the four transistors T1 to T4
And a total of 22 program switches PD1, PD2, PS
1, PS2, P1 to P16, PB1 and PB2 form a minimum unit basic cell. Further, like the third semiconductor integrated circuit device, the first bypass program switch PB1 is used.
By this, the source or drain lead-out electrodes SD1 and SD3 of the first and second transistors T1 and T2 can be directly connected to each other without the second high-potential side spare wiring LP2.
Similarly, by the second bypass program switch PB2, the third low-potential side spare wiring LN2 is not provided between the source or drain extraction electrodes SD4, SD6 of the third and fourth transistors T3, T4. It is possible to connect directly.

As a result, the number of program switches is increased by 4 as compared with the first semiconductor integrated circuit device, but
Inverter circuit and inverter (power type) while applying the through wiring function, like the semiconductor integrated circuit device
Circuit, transmission gate circuit, two-input NAND
A circuit, a two-input NOR circuit, etc. can be combined. In addition, by connecting the two basic cells, a 3-input NAND circuit,
3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit
It is possible to configure a circuit, a 4-input AND / OR inverter circuit, and a 6-input AND / OR inverter circuit by connecting three basic cells.

Further, according to the eighth semiconductor integrated circuit device of the present invention, as shown in FIG. 8, a plurality of first to fourth transistors T1 to T4 and a plurality of interconnections between them and between wirings are connected. Various program switches PD1, PD2, PS1, PS2, P1
To P14, the third high potential side program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor T2 and the first power supply line VDD, and the fourth transistor A third low potential side program switch PS3 is connected between the source or drain extraction electrode SD6 of T4 and the second power supply line VSS. The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors T1 and T2, and the sources of the third and fourth transistors T3 and T4 or A second bypass program switch PB2 is connected between the drain extraction electrodes SD4 and SD6.

Therefore, the four transistors T1 to T4
And a total of 24 program switches PD1 to PD3, PS1
.About.PS3, P1 to P16, PB1 and PB2 form a minimum unit basic cell. Further, similar to the fourth semiconductor integrated circuit device, for example, among the basic cells, the first and third high potential side program switches PD1 and PD3, the first low potential side program switch PS1 and the third , By programming the fuse elements, antifuse elements, and p-type or n-type field effect transistors forming the twelfth program switches P3 and P12, a two-input NAND circuit can be formed.

As a result, the number of program switches is increased by 4 as compared with the first semiconductor integrated circuit device, but the fifth
Inverter circuit and inverter (power type) while applying the through wiring function, like the semiconductor integrated circuit device
Circuit, transmission gate circuit, two-input NAND
A circuit, a two-input NOR circuit, etc. can be combined. Also, two basic cells are connected to form a 3-input NAND circuit,
3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit
It is possible to configure a circuit, a 4-input AND / OR inverter circuit, and a 6-input AND / OR inverter circuit by connecting three basic cells.

While the first to eighth semiconductor integrated circuit devices of the present invention are suitable for forming a relatively small-scale logic gate circuit, the ninth to twelfth semiconductor integrated circuit devices are suitable. Suitable for forming a relatively large-scale logic gate circuit.

Further, according to the ninth semiconductor integrated circuit device of the present invention, as shown in FIG. 9, a plurality of first to eighth transistors T1 to T8 are connected to each other or to interconnects. Various program switches PD1 to PD4, PS1 to PS4, P1
To P22 are provided.

Therefore, the eight transistors T1 to T8
And a total of 30 program switches PD1 to PD4, PS1
.About.PS4 and P1 to P22 form a minimum unit basic cell. For example, among the basic cells, the first, second, fourth
High potential side program switches PD1, PD2, PD4, first and second low potential side program switches PS1, PS2, and fourth, eighth, tenth, seventeenth, and twenty-second program switches P
4, fuse elements forming P8, P10, P17, P22,
Program the antifuse element and p-type or n-type field effect transistor.

As a result, the source or drain extraction electrode SD1 of the first transistor T1 and the first power supply line VDD
Are connected via a first high potential side program switch PD1 and the source or drain extraction electrodes SD2 of the first and second transistors T1 and T2 and the first power supply line VDD are connected to the second high potential side. Is connected via the program switch PD2.

The source or drain extraction electrode SD3 of the second transistor T2 and the first output line Lout1 are connected via the fourth program switch P4, and the source or drain of the fourth transistor T4 is extracted. The electrode SD4 and the first output wiring Lout1 are connected via the eighth program switch P8. Further, the source or drain extraction electrodes SD5 of the third and fourth transistors T3 and T4 and the first power supply line VDD are connected via a fourth high potential side program switch PD4, and the fourth transistor T4 The source or drain extraction electrode SD6 and the first output line Lout1 are connected via the tenth program switch P10.

Furthermore, the source or drain extraction electrode SD7 of the fifth transistor T5 and the second power supply line VSS are connected via the first low potential side program switch PS1 and the fifth and sixth transistors T5 are connected. , T6 source or drain extraction electrode SD8 and second power supply line VSS
Is connected via the high potential side program switch PS2.

Further, the extraction electrode SD9 of the source or drain of the sixth transistor T6 and the seventh transistor T7
Is connected to the source / drain extraction electrode SD10 via the seventeenth program switch P17, and the source / drain extraction electrode SD12 of the eighth transistor T8 and the first output wiring Lout1 are connected to the twenty-second program switch P22.
Connected via.

As a result, a three-input NAND circuit is formed by the first to fourth transistors T1 to T4 made of p-type field effect transistors and the fifth to eighth transistors T5 to T8 made of n-type field effect transistors. It becomes possible to do. From this, a total of 30 program switches PD1 to PD4, PS1 to PS4, P1 to P22 are appropriately set.
Eight transistors T by programming
1 to T8, 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit, 3-input A
It is possible to configure a basic logic cell such as an ND / OR inverter circuit and a 4-input AND / OR inverter circuit.

Further, according to the tenth semiconductor integrated circuit device of the present invention, as shown in FIG. 10, a plurality of first to eighth transistors T1 to T8 and a plurality of interconnections between them and between wirings are connected. Various program switches PD1 to PD4, PS1 to PS4, P1
To P22, a fifth high potential side program switch PD5 is connected between the source or drain extraction electrode SD3 of the second transistor T2 and the first power supply line VDD, and a fourth A sixth high potential side program switch PD6 is connected between the source or drain extraction electrode SD6 of the transistor T4 and the first power supply line VDD, and further the source or drain extraction electrode SD9 of the sixth transistor T6 is connected. The fifth low-potential side program switch PS5 is connected between the second power supply line VSS and the second power supply line VSS, and the fifth power supply line VSS is connected between the source or drain extraction electrode SD12 of the eighth transistor T8 and the second power supply line VSS. The low potential side program switch PS6 of 6 is connected.

Therefore, the eight transistors T1 to T8
And a total of 34 program switches PD1 to PD6, PS1
.About.PS6 and P1 to P22 constitute a minimum unit basic cell. For example, among the basic cells, first, third, fifth and sixth high potential side program switches PD1, PD3,
PD5, PD6, first low potential side program switch PS1
And the third, ninth, seventeenth and twenty-second program switches P3,
A four-input NAND circuit can be constructed by programming the fuse element, antifuse element, and p-type or n-type field effect transistor forming P9, P17, and P22.

As a result, the number of program switches is increased by 4 as compared with the ninth semiconductor integrated circuit device, but a total of 34 program switches PD1 to PD4, PS1 to PS4,
8 by properly programming P1 to P22
With the transistors T1 to T8, a 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input N circuit
Basic logic cells such as an OR circuit, a 3-input AND / OR inverter circuit, and a 4-input AND / OR inverter circuit can be configured.

Further, according to the eleventh semiconductor integrated circuit device of the present invention, as shown in FIG. 11, the first to eighth transistors T1 to T8 are connected to each other and a plurality of interconnections are provided to connect them. Various program switches PD1 to PD4, PS1 to PS4, P
1 to P22, the first and second transistors T
1, T2 source or drain extraction electrodes SD1, SD3
The first and second bypass program switches PB1 and PB2 are respectively connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4, and the fifth and sixth transistors T5 and T5 are connected. Third and fourth bypass program switches PB3 and PB4 are connected between the source or drain extraction electrodes SD7 and SD9 of T6 and the source or drain extraction electrodes SD10 and SD12 of the seventh and eighth transistors T7 and T8, respectively. It

Therefore, the eight transistors T1 to T8
And a total of 34 program switches PD1 to PD4, PS1
.About.PS4, PB1 to PB4, P1 to P22 form a minimum unit basic cell. Further, the extraction electrodes S of the source or drain of the first and second transistors T1 and T2 are formed by the first and second bypass program switches PB1 and PB2.
It is possible to directly connect the D1 and SD3 and the lead-out electrodes SD4 and SD6 of the sources or drains of the third and fourth transistors T1 and T2 without the first output wiring Lout1.

Similarly, by the third and fourth bypass program switches PB3 and PB4, the extraction electrodes SD7 and S7 of the source or drain of the fifth and sixth transistors T5 and T6, respectively.
It is possible to directly connect between SD9 and between the lead-out electrodes SD10 and SD12 of the sources or drains of the seventh and eighth transistors T7 and T8 without the second output wiring Lout2.

As a result, the number of program switches is increased by 4 as compared with the ninth semiconductor integrated circuit device, but a total of 34 program switches PD1 to PD4, PS1 to PS4,
8 by properly programming P1 to P22
With the transistors T1 to T8, a 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input N circuit
Basic logic cells such as an OR circuit, a 3-input AND / OR inverter circuit, and a 4-input AND / OR inverter circuit can be configured.

Further, in the twelfth semiconductor integrated circuit device of the present invention, as shown in FIG.
T8 and a plurality of various program switches PD1 to PD4, PS1 to PS4, P1 to P22 for connecting between them and between wirings are provided, and the source or drain extraction electrode SD3 of the second transistor T2 and the first No. 5 between the power supply line VDD and
Is connected to the high potential side program switch PD5, and the sixth high potential side program switch PD6 is connected between the source or drain extraction electrode SD6 of the fourth transistor T4 and the first power supply line VDD. And the sixth
The fifth low-potential-side program switch PS5 is connected between the source or drain extraction electrode SD9 of the transistor T6 and the second power supply line VSS, and the eighth transistor T6
A sixth low potential side program switch PS6 is connected between the eighth source or drain extraction electrode SD12 and the second power supply line VSS.

In addition, the first and second transistors T1 and T
The first and second bypass program switches PB1 and PB2 are connected between the two source or drain extraction electrodes SD1 and SD3 and the source and drain extraction electrodes SD4 and SD6 of the third and fourth transistors T3 and T4, respectively. The extraction electrodes SD7, SD9 of the source or drain of the fifth and sixth transistors T5, T6 and the extraction electrode SD10 of the source or drain of the seventh and eighth transistors T7, T8.
, SD12, third and fourth bypass program switches PB3, PB4 are connected, respectively.

Therefore, the eight transistors T1 to T8
And a total of 38 program switches PD1 to PD6, PS1
.About.PS6, P1 to P22, PB1 to PB4 form a minimum unit basic cell. For example, the third of the basic cells
High potential side program switch PD3, second low potential side program switch PS2 and first, third, tenth, thirteenth,
18th program switch P1, P3, P10, P13, P
18, first and fourth bypass program switch PB1,
PB4 fuse element, anti-fuse element, p
By programming the n-type or n-type field effect transistor, a 4-input AND / OR inverter circuit can be configured.

As a result, the number of program switches is increased by 8 as compared with the ninth semiconductor integrated circuit device, but a total of 38 program switches PD1 to PD4, PS1 to PS4,
8 by properly programming P1 to P22
With the transistors T1 to T8, a 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input N circuit
Basic logic cells such as an OR circuit, a 3-input AND / OR inverter circuit, and a 4-input AND / OR inverter circuit can be configured.

Furthermore, according to the thirteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the first to fourth semiconductor integrated circuit devices are connected or various logic circuits in which the basic cells are combined. Is configured.

Therefore, by combining the basic logic cells according to the first to fourth semiconductor integrated circuit devices, for example, a D-type flip-flop circuit can be constituted by four transmission gate circuits and eight inverter circuits. It will be possible. In addition, the total number of transistors is 1 which constitutes four transmission gate circuits.
There are a total of 48 transistors, which is 6 transistors and 32 transistors forming 8 inverter circuits.

As a result, the D-type flip-flop circuit can be constructed with about half the number of transistors as compared with the conventional example. It should be noted that, as compared with a basic cell having a minimum unit of two types, that is, a transistor pair tile portion and a RAM logic tile portion as in the conventional example, a D-type is obtained by combining the basic cells of the first to eighth semiconductor integrated circuit devices. It becomes possible to easily configure the flip-flop. From this, it is expected that the usage efficiency will be improved.

Further, according to the fourteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the fifth to eighth semiconductor integrated circuit devices are connected or various logic circuits in which the basic cells are combined. Is configured.

Therefore, by combining the basic logic cells according to the fifth to eighth semiconductor integrated circuit devices, for example, the through wiring function is applied to apply the 3-input NAND circuit, 3
It is possible to configure an input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, a 4-input AND / OR inverter circuit, and a multi-input AND / OR inverter circuit by connecting a plurality of the semiconductor integrated circuit devices. Further, like the fourteenth semiconductor integrated circuit device, it becomes possible to configure a D-type flip-flop circuit by four transmission gate circuits and eight inverter circuits.

As a result, it becomes possible to provide an FPGA capable of programming a high-performance and high-performance semiconductor integrated circuit. Further, according to the fifteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the ninth to twelfth semiconductor integrated circuit devices are connected, or various logic circuits are formed by combining the basic cells. .

Therefore, by combining the basic logic cells according to the ninth to twelfth semiconductor integrated circuit devices, for example, by applying the through wiring function, the 3-input NAND circuit, 3
It is possible to configure an input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, a 4-input AND / OR inverter circuit, and a multi-input AND / OR inverter circuit by connecting a plurality of the semiconductor integrated circuit devices.

As a result, similar to the fourteenth semiconductor integrated circuit device, it is possible to provide an FPGA capable of programming a high-performance and highly-functional semiconductor integrated circuit. Further, according to the sixteenth semiconductor integrated circuit device of the present invention, two or more basic cells composed of the first to twelfth semiconductor integrated circuit devices are connected, or various logic circuits are formed by combining the basic cells. .

Therefore, the semiconductor integrated circuit device according to the first to eighth aspects of the present invention allows a relatively small-scale inverter circuit, inverter (power type) circuit, transmission gate circuit, two-input NAND circuit, two-input NOR circuit, etc. And a relatively large-scale three-input NAND circuit and three-input NOR circuit by the first to ninth semiconductor integrated circuit devices of the present invention.
By configuring the circuit, the 4-input NAND circuit, the 4-input NOR circuit, and the 4-input AND / OR inverter circuit, it becomes possible to configure a multifunctional composite logic circuit.

As a result, like the fifteenth semiconductor integrated circuit device, it is possible to provide an FPGA capable of programming a high-performance and high-performance semiconductor integrated circuit.

[0102]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 13 to 77 are views for explaining a semiconductor integrated circuit device according to an embodiment of the present invention.

(1) Description of First Embodiment FIG. 13 is a block diagram of the FPGA chip according to each embodiment of the present invention, and FIGS. 14 (a) and 14 (b) show each of the present invention. FIG. 16 is an explanatory diagram of a basic cell according to an example, and FIG.
(B) is the block diagram of the basic cell according to the first embodiment of the present invention.

For example, an FPGA (Field Programmable Gate Array) 100, which is an example of a semiconductor integrated circuit device, has a basic cell (basic cell) region 101 in FIG.
I / O (input / output circuit element) cell area 102 and wiring area 10
Composed of three. The FPGA can be provided to the user at an early stage, and can be mainly used when developing a new LSI or as a prototype of an electronic product. The FPGA is an ASIC that can be programmed by the user.

That is, the basic cells of the FPGA according to the first to eighth embodiments of the present invention are as shown in FIG.
A p-type field effect transistor TPi [i = 1, 2, 11, 12] as an example of the first and second transistors T1 and T2.
And an n-type field effect transistor Tni [i = 1, 2, 11, 1 as an example of the third and fourth transistors T3 and T4.
2], and source / drain extraction electrodes SDi [i = 1 to 6] and a gate G are provided therein.

The basic cells of the FPGA according to the ninth to twelfth embodiments of the present invention are the first to fourth transistors T1.
˜T4 as an example of p-type field effect transistor TPi
[I = 1 to 4] and fifth to eighth transistors T5 to T
8, an n-type field effect transistor Tni [i =
1 to 4], and source or drain extraction electrodes SDi [i = 1 to 12] and a gate G are provided therein.

FIG. 14B is a plan view of the wiring regions of the first to fourth transistors T1 to T4.
In FIG. 14B, the first to fourth transistors T1 to T1
Each gate G of T4 is a contact hole (bulk-AL1)
106 is fixedly connected to the input wiring Lin through the first,
The second output wirings Lout1 and Lout2 are through holes (AL1-
AL2) 106 is interposed to be fixedly connected to the first and second p-type spare wires LP1 and LP2, which are examples of the first and second high-potential side spare wires LP1 and LP2.

Further, the FPGA according to each embodiment of the present invention
Various program points are through holes (AL1- AL
2) First and second power supply lines VDD and VSS with 105 interposed
(Hereinafter, simply referred to as power supply line VDD or ground line GND) and first and second low potential side spare lines LN1 and LN2 which are examples of the first and second
It is programmed in the second spare wiring for n-type or the like. The details will be described later with reference to FIGS.

FIGS. 15A and 15B are block diagrams of the basic cell according to the first embodiment of the present invention, and FIG. 15A includes its transistors, wirings and various program points. FIG. 15B is a circuit diagram and shows a program symbol diagram in which the various program points are arranged.

In FIG. 15 (a), the first basic cell 1 of the present invention includes first to fourth transistors TP1, TP2, TN1,
TN4 and 18 various program switches PD1, PD2,
It consists of PS1, PS2 and P1 to P14.

For example, the first to fourth transistors TP1,
The gates G of TP2, TN1 and TN4 are connected to the input wiring Lin, and the first to fourth transistors TP1, TP2, TN1 and TN2 are connected.
Source or drain extraction electrodes SD1 to SD6 are
First and second p-type power source program switches, which are examples of the second high potential side program switches PD1 and PD2, and n-type, which is an example of the first and second low potential side program switches PS1 and PS2. Ground program switch and 1st-14th
Power supply line V via the program switches P1 to P14
DD, ground line GND, first and second output lines Lout1, Lout
2, the first and second p-type spare wirings LP1, LP2 or the first,
It is connected to the second n-type spare lines LN1 and LN2.

That is, FIG. 15 originally devised by the present inventor
In the program symbol diagram in which the transistor symbol is omitted as shown in (b), the extraction electrode SD1 of the source or drain of the first transistor TP1 is connected to the power line VDD through the first p-type power program switch PD1. When,
The second output wiring Lout2 with the first program switch P1 interposed, the first output wiring Lout1 with the second program switch P2 interposed, and the first p-type spare wiring L.
Connected to P1.

Further, the first and second transistors TP1 and T
The extraction electrode SD2 of the source or drain of P2 is the second p
Power source line V via the power source program switch PD2 for mold
The first program with the DD and the third program switch P3
Of the output wiring Lout1. The source or drain extraction electrode SD3 of the second transistor TP2 has a first output line L through a fourth program switch P4.
out1, the second output wiring Lout2 with the fifth program switch P5 interposed, and the sixth program switch P6.
Is connected to the first p-type spare wiring LP1.

Further, the extraction electrode SD4 of the source or drain of the third transistor TN1 is connected to the ground line GND through the first n-type ground program switch PS1 and the eighth electrode.
Connected to the first output line Lout1 via the program switch P8, the second output line Lout2 via the ninth program switch P9, and the first n-type spare line LN1. The source or drain extraction electrodes SD5 of the third and fourth transistors TN1 and TN4 are connected to the ground line GND via the second n-type ground program switch PS2.
Is connected to the second output wiring Lout2 through the tenth program switch P10.

Note that the source or drain extraction electrode SD6 of the fourth transistor TN4 has a first output switch Lout2 via the eleventh program switch P11 and a first output switch SD12 via the twelfth program switch P12. Output wiring L
out1 and the first output line Lout1 are connected to the first n-type spare line LN1 via the thirteenth program switch P13, and the first output line Lout1 is used for the second p-type line via the seventh program switch P7. The second output line L connected to the spare line LP2
out2 is the second via the 14th program switch P14
Connected to the n-type spare wiring LN2.

Further, various program points are formed by a fuse element, an anti-fuse element, a p-type or n-type field effect transistor, and the program (fusing or activating or ON operation, OFF operation (in the case of transistor)) processing is performed. As a result, it is electrically insulated or conductive. Here, in the program symbol diagram of FIG. 15 (b), when various anti-fuse elements are used for various program points indicated by white squares, and when they are selected, they are painted black. . Therefore, the non-selected portion is left with a white square symbol.

Regarding various program points,
When a fuse element is used and it is selected, the portion to be cut is represented by a white square symbol, and the portion painted in black is a non-selected portion. Regarding various program points, when a p-type or n-type field effect transistor is used and it is in an OFF state, that part is represented by a white square □ symbol, and when it is in an ON state. Will fill it black.

Thus, according to the basic cell of the first embodiment of the present invention, as shown in FIGS. 15 (a) and 15 (b), the first to fourth transistors TP1, TP2, TN1 are provided. , TN2
And a plurality of various program switches PD1, PD2, PS1, PS2, P1 to P14 for connecting between them and between wirings.

Therefore, the four transistors TP1 and TP
2, TN1, TN2, total 18 program switches PD
1, PD2, PS1, PS2, and P1 to P14 form a minimum unit basic cell. For example, in the first basic cell,
First and second p-type power source program switches PD1 and PD
2, first and second n-type ground program switch PS1,
A fuse element, an anti-fuse element, a p-type or an n-type which constitutes PS2 and the fourth and twelfth program switches P4 and P12.
Type field effect transistor is programmed.

As a result, the source or drain extraction electrode SD1 of the first transistor TP1 and the power supply line VDD are connected to each other through the first p-type power supply program switch PD1 and the first and second transistors TP1 and TP2 are connected. The source or drain extraction electrode SD2 and the power supply line VDD are connected via a second p-type power supply program switch PD2.

The source or drain extraction electrode SD3 of the second transistor TP2 and the first output line Lout1 are connected via the fourth program switch P4, and the source or drain of the third transistor TN1 is extracted. The electrode SD4 and the ground line GND are connected via the first n-type ground program switch PS1. The source or drain extraction electrode SD5 of the third and fourth transistors TN1 and TN4 and the ground line GND are connected to each other. P type power source program switch PS1
Connected via. Furthermore, the fourth transistor TN4
The source or drain extraction electrode SD6 and the first output wiring Lout1 are connected via the twelfth program switch P12.

As a result, an inverter circuit can be constituted by the second transistor TP2 which is a p-type field effect transistor and the fourth transistor TN4 which is an n-type field effect transistor. From this,
18 program switches PD1, PD2, PS1, P
By appropriately programming S2 and P1 to P14, four transistors TP1, TP2, TN1 and TN2
Inverter circuit, inverter (power type) circuit, transmission gate circuit, 2-input NAND circuit, 2
It becomes possible to configure a basic logic cell such as an input NOR circuit.

The seventh and fourteenth program switches P
It is possible to connect the first output wiring Lout1 and the second output wiring Lout2 to the basic cells in the vertical direction by performing the program processing of 7 and P14.

(2) Description of Second Embodiment FIGS. 16 (a) and 16 (b) are configuration diagrams of a basic cell according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the third p-type power source program switch PD3 and the third n-type ground program switch PS3 are connected.

That is, the second basic cell 2 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 18 various program switches PD1 to PD
3, PS1 to PS3, P1 to P14.

In the program symbol diagram of FIG. 16B, the third p-type power source program switch PD3 is the second one.
Is connected between the source or drain extraction electrode SD3 of the transistor TP2 and the power supply line VDD, and the third n-type ground program switch PS3 is connected to the source or drain extraction electrode SD6 of the fourth transistor TN2 and the ground line GND. Connected between and. The other structure is similar to that of the first embodiment, and the description thereof is omitted.

In this way, according to the basic cell of the second embodiment of the present invention, as shown in FIG.
A fourth transistor TP1, TP2, TN1, TN2 and 20 various program switches PD1 to PD3, PS1 to PS3, P1 to P14 for connecting between them and between wirings,
A third p-type power source program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power supply line VDD, and the source or drain extraction electrode SD6 of the fourth transistor TN2 is connected. And the ground line GND between the third ground program switch PS3 for n-type
Are connected.

Therefore, the four transistors TP1 and TP
2, TN1, TN2 and 20 program switches PD in total
1 to PD3, PS1 to PS3, and P1 to P14 form a minimum unit basic cell. For example, in the second basic cell,
First and third p-type power source program switches PD1 and PD
3, the first n-type ground program switch PS1 and the third,
By programming the fuse element, antifuse element, and p-type or n-type field effect transistor forming the twelfth program switches P3 and P12, a two-input NAND circuit can be formed.

As a result, the number of program switches is increased by 2 as compared with the first embodiment, but the inverter circuit,
An inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, etc. can be combined, and when the second basic cell 2 is combined, a third p-type power source program switch P
By applying D3 and the third n-type ground program switch PS3, it becomes possible to construct a 3-input, 4-input basic logic circuit.

(3) Description of Third Embodiment FIGS. 17 (a) and 17 (b) are block diagrams of a basic cell according to a third embodiment of the present invention, and FIGS. The block diagrams of the basic logic cells when the cells are programmed are shown respectively. The third embodiment differs from the first and second embodiments in that the first and second bypass program switches PB1 and PB2 are connected.

That is, the third basic cell 3 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 20 various program switches PD1, PD
2, PS1, PS2, P1 to P14 and PB1 and PB2.

In the program symbol diagram of FIG. 17B, the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2. The second bypass program switch PB2 is a source or drain extraction electrode SD4 of the third and fourth transistors TN1 and TN2,
Connected between SD6. The other structure is similar to that of the first embodiment, and the description thereof is omitted. Next, the program processing of the basic cell according to the third embodiment of the present invention will be described.

18 (a) and 18 (b) are configuration diagrams of an inverter circuit in the case where the basic cell according to the third embodiment of the present invention is programmed. In FIG. 18 (a), the inverter circuit is composed of first and second p-type power source program switches P.
D1, PD2, program processing of the fuse element, antifuse element, p-type or n-type field effect transistor constituting the first n-type ground program switch PS1 and the fourth and twelfth program switches P4, P12 .

As a result, as shown in FIG. 18B, the transistor TP connected between the power line VDD and the ground line GND is connected.
It is possible to configure an inverter circuit which is composed of 2 and TN1 and which inverts and amplifies the input signal A and outputs the output signal X from the first output wiring Lout1.

19 (a) and 19 (b) are configuration diagrams of an inverter (power type) circuit when a basic cell according to the third embodiment of the present invention is programmed. In FIG. 19 (a), the power type inverter circuit includes a second p-type power source program switch PD2, a second n-type ground program switch PS2, and first, fifth, ninth and eleventh program switches. Program processing of fuse elements, antifuse elements, and p-type or n-type field effect transistors constituting P1, P5, P9, and P11 is performed.

As a result, as shown in FIG. 19B, the transistor TP connected between the power supply line VDD and the ground line GND is connected.
An inverter (power type) circuit composed of 1, TN1, TP2, and TN2, which inverts and amplifies the input signal A and outputs the output signal X from the second output wiring Lout2, can be configured.

20 (a) and 20 (b) are block diagrams of a transmission gate circuit in the case of programming the basic cell according to the third embodiment of the present invention. In FIG. 20A, the transmission gate circuit includes first, third, fifth, eighth, tenth, and twelfth program switches P1 and P.
3, P5, P8, P10, P12 fuse elements,
Program the antifuse element and p-type or n-type field effect transistor.

As a result, as shown in FIG. 20 (b), the first output wiring Lout1 extends to the connection terminal T1, the second output wiring Lout2 extends to the connection terminal T2, and the second transistor It is possible to configure a transmission gate circuit in which the gate G of TP2 is connected to the control terminal S1 and the gate G of the third transistor TN1 is connected to the control terminal S2.

FIGS. 21 (a) and 21 (b) show a 2-input NA when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of an ND circuit. In FIG. 21 (a), the 2-input NAND circuit includes a second p-type power source program switch PD2, a first n-type ground program switch PS1 and second, fourth and twelfth program switches P2 and P4. , P
The fuse element, the antifuse element, and the p-type or n-type field effect transistor constituting 12 are programmed.

As a result, as shown in FIG. 21 (b), the first to fourth transistors TP1, TP2, TN1 and TN2 are provided, and the output signals X of the input signals A1 and A2 are logically amplified. 2-input NAN output from the first output line Lout1
A D circuit can be constructed.

22 (a) and 22 (b) are two-input NO when programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 22 (a), 2 inputs N
The OR circuit is the first p-type power source program switch PD
1, the second n-type ground program switch PS2 and the fifth,
Program processing is performed for the fuse element, antifuse element, and p-type or n-type field effect transistor forming the ninth and twelfth program switches P5, P9, and P11.

As a result, as shown in FIG. 22 (b), the first to fourth transistors TP1, TP2, TN1 and TN2 are provided, and the input signals A1 and A2 are logically amplified to output the output signal X thereof. 2-input NOR output from the second output wiring Lout2
A circuit can be constructed.

In this way, according to the basic cell of the third embodiment of the present invention, as shown in FIG.
~ Fourth transistor TP1, TP2, TN1, TN2 and 20 various program switches PD1, PD2, PS1, PS2, P1 to P14 and PB1, PB for connecting between them and between wirings
B2 is provided, and the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2.
A second bypass program switch PB2 is connected between the extraction electrodes SD4 and SD6 of the sources or drains of the fourth transistors TN1 and TN2.

Therefore, the four transistors TP1 and TP
2, TN1, TN2 and 20 program switches PD in total
1, PD2, PS1, PS2, P1 to P14, PB1 and PB2 form a minimum unit basic cell. Further, the first bypass program switch PB1 can be used to directly connect the extraction electrodes SD1 and SD3 of the sources or drains of the first and second transistors TP1 and TP2 without the first output wiring Lout1. Similarly, by the second bypass program switch PB2, the third and fourth transistors T
N1 and TN2 source or drain extraction electrodes SD4 and SD6
It is possible to directly connect the two without interposing the second output wiring Lout2.

As a result, the number of program switches is increased by 2 as compared with the first embodiment, but by connecting three third basic cells, a 4-input AND / OR inverter circuit or 6
It is possible to efficiently use the first and second bypass program switches PB1 and PB2 when configuring an input AND / OR inverter circuit or the like.

Further, by relating to the circuit configuration of the basic cell and not relying on many transistors as in the conventional example, the number of transistors and the number of program points are reduced as much as necessary, and the combination and program processing are performed. It is possible to configure 21 types of basic logic circuits.

Next, the case of programming a plurality of basic cells according to the third embodiment of the present invention will be described. 23 (a) and 23 (b) are 3-input NANDs in the case of programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of a circuit. In FIG. 23 (a), 3-input NA
The ND circuit first connects two basic cells 3 according to the third embodiment of the present invention. Here, the power supply line VDD and the ground line GN
D, the first and second p-type spare wirings LP1 and LP2, and the first and second
The second spare wirings LN1 and LN2 for n-type are connected. Also, 2
In one of the basic cells BC1 and BC2, a program point P6 is interposed between the first p-type spare wiring LP1 and a program point P7 is interposed between the second p-type spare wiring LP2 and the first output wiring Lout1. Then, the first n-type spare wiring LN1
A program point P13 is interposed therebetween, and a program point P14 is interposed between the second n-type spare wiring LN2 and the second output wiring Lout2.

Next, the first and second p-type power source program switches PD1 and PD2, and the first and second p-type power source program switches of the one basic cell BC1.
N type power source program switches PS1, PS2, fuse elements, antifuse elements, p type or n elements constituting the fourth, seventh and thirteenth program switches P4, P7, P13.
The second p-type power source program switch PD2, the second, the fourth and the twelfth program switches P2 of the other basic cell BC2.
A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming P4 and P12 are programmed.

As a result, as shown in FIG. 23B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3 and output the output signal X from the first output wiring. 3-input NAN output from Lout1
A D circuit can be constructed.

24 (a) and 24 (b) are three-input NO in the case where the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of an R circuit. In Fig. 24 (a), 3 inputs N
The OR circuit connects two basic cells 3 according to the third embodiment of the present invention.

Further, the first and second p-type power source program switches PD1 and PD2 of the one basic cell BC1 and the first and second
N type power source program switches PS1, PS2, fourth, sixth, eleventh and fourteenth program switches P4, P6, P
The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting 11, P14 are programmed, and the first and second n-type power source program switches PS1, PS2 of the other basic cell BC2 are programmed. Program processing is performed for the fuse element, antifuse element, and p-type or n-type field effect transistor forming the fifth, ninth, and eleventh program switches P5, P9, and P11.

As a result, as shown in FIG. 24 (b), the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3 and output the output signal X from the first output wiring. 3-input NAN output from Lout1
A D circuit can be constructed.

FIGS. 25A and 25B are four-input NA when programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of an ND circuit. In FIG. 25A, the 4-input NAND circuit first connects two basic cells 3 according to the third embodiment of the present invention.

Next, the second p-type power source program switch PD2 of the one basic cell BC1, the first n-type power source program switch PS1, the second, fourth, seventh and thirteenth program switches P2. , P4, P7, P13, fuse elements, antifuse elements, p-type or n-type field effect transistors are programmed, and the other basic cell B is programmed.
C2 second p-type power source program switch PD2, second,
Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming the fourth and twelfth program switches P2, P4, P12 is performed.

As a result, as shown in FIG. 25 (b), the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3, A4 and output the output signal X from the first signal. A 4-input NAND circuit that outputs from the output wiring Lout1 can be configured.

26 (a) and 26 (b) are four-input NO in the case of programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 26 (a), 4 inputs N
The OR circuit connects two basic cells 3 according to the third embodiment of the present invention.

Also, the first p-type power source program switch PD1 of the one basic cell BC1, the second n-type power source program switch PS2, the sixth, ninth, eleventh, and fourteenth program switches P6. The fuse element, the antifuse element, and the p-type or n-type field effect transistor forming P9, P11, and P14 are programmed, and the other basic cell B is processed.
C2 second n-type power source program switch PS2, fifth,
Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor which constitute the ninth and eleventh program switches P5, P9, and P11 is performed.

As a result, as shown in FIG. 26B, the first to fourth transistors TP11 and TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3, A4 and output the output signal X of the second signal. It is possible to configure a 4-input NAND circuit that outputs from the output wiring Lout2.

FIGS. 27 (a) and 27 (b) show a 3-input AN in the case of programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 27A, a 3-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

The first and second p-type power source program switches PD1 and PD2 of the one basic cell BC1 and the first and second p-type power source program switches
N type power source program switches PS1, PS2, fourth, seventh, eleventh and fourteenth program switches P4, P7, P
The anti-fuse element or the fuse element constituting P11, P14 is programmed, and the first n-type power source program switch PS1, first, third, fifth of the other basic cell BC2 is programmed.
, 11th program switches P1, P3, P5, P11
The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting the above are programmed.

As a result, as shown in FIG. 27B, the first to fourth transistors TP11, TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, two-input logical amplification of the input signals A1 and A2 is performed first, and the resultant signal and the input signal B are combined. Perform logical amplification and output signal X
3-input AND · O for outputting from the second output wiring Lout2
An R inverter circuit can be configured.

FIGS. 28 (a) and 28 (b) show a 4-input AN in the case of programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 28A, the 4-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Further, the second p-type power source program switch PD2, the second, fourth, seventh, ninth, thirteenth, and fourteenth program switches P2, P4, P of one of the basic cells BC1.
7, P9, P13, P14 fuse elements, anti-fuse elements, p-type or n-type field effect transistors are programmed, and the first p-type power source program switch PD1 of the other basic cell BC2, The n-type power source program switch PS2, the third, fifth, and eleventh program switches P3, P5, and P11, which are fuse elements, antifuse elements, and p-type or n-type field effect transistors, are programmed. To do.

As a result, as shown in FIG. 28 (b), the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, three-input logical amplification is performed first with the input signals A1, A2, A3, and the resulting signal and the input signal B 4-input AN that performs logical amplification with and outputs the output signal X from the second output wiring Lout2
A D / OR inverter circuit can be constructed.

FIGS. 29 (a) and 29 (b) show a 4-input AN in the case of programming the basic cell according to the third embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 29 (a), a 4-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Also, the second p-type power source program switch PD2 of the one basic cell BC1, the first n-type power source program switch PS1, the second, fourth, seventh, ninth and fourteenth programs. Fuse element, antifuse element, p-type or n-type switch P2, P4, P7, P9, P14
Type field effect transistor is programmed, and the first n-type power source program switch PS1, the first, third, fifth and eleventh program switches P1, P3, P5 and P11 of the other basic cell BC2 are programmed. The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting the above are programmed.

As a result, as shown in FIG. 29B, the first to fourth transistors TP11 and TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which first perform two-input logical amplification of the input signals A1 and A2, and also two input signals A3 and A4. It is possible to configure a 4-input AND / OR inverter circuit which performs input logical amplification, logically amplifies the result signals of both, and outputs the output signal X from the second output wiring Lout2.

FIGS. 30 (a) and 30 (b) show a 4-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 30A, a 4-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Further, the second n-type power source program switch PS2 of one of the basic cells BC1, the first, fourth, seventh, ninth, eleventh and fourteenth program switches P1, P4, P.
7, P9, P11, P14, fuse elements, anti-fuse elements, p-type or n-type field effect transistors are programmed, and the second p-type power source program switch PD2 of the other basic cell BC2, Program processing of a fuse element, an anti-fuse element, a p-type or n-type field effect transistor which configures one n-type power source program switch PS1, second, fourth and tenth program switches P2, P4 and P10. To do.

As a result, as shown in FIG. 30B, the first to fourth transistors TP11 and TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1 and A2 are first two-input logically amplified, and the resultant signal and the input signals B1 and B2 are obtained. And a three-input logic amplification with the output signal X is output from the second output wiring Lout2 4
An input AND / OR inverter circuit can be constructed.

FIGS. 31, 32 (a) and 32 (b) are block diagrams of a 6-input AND / OR inverter circuit in the case of programming the basic cell according to the third embodiment of the present invention. In FIG. 31, a 6-input AND / OR inverter circuit connects three basic cells 3 according to the third embodiment of the present invention.

For example, the first n-type power source program switch PS1 of the first basic cell BC1, the first, third, fifth, seventh, eleventh and fourteenth program switches P1, P3, P.
5, P7, P11, P14, fuse elements, antifuse elements, p-type or n-type field effect transistors are programmed, and the first n-type power source program switch PS1 of the second basic cell BC2 is programmed. A fuse element, an anti-fuse element, a p-type or n-type field effect transistor forming the first bypass program switch PB1, the third, sixth, eleventh and fourteenth program switches P3, P6, P11, P14. Program processing of. Furthermore, the third
Second p-type power source program switch PD2 of the basic cell BC3, first n-type power source program switch PS1, second, fourth and eleventh program switches P2, P4, P
The fuse element, the antifuse element, and the p-type or n-type field-effect transistor constituting 11 are programmed.

As a result, as shown in FIGS. 32A and 32B, the first to fourth transistors TP11 of the basic cell BC1 are formed.
, TP12, TN11, TN12, the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2 and the first to fourth transistors TP31, TP32 of the basic cell BC3.
, TN31, TN32, and the input signals A1, A2
, Two-input logic amplification of the input signals B1 and B2, further two-input logic amplification of the input signals C1 and C2, and three-input logic amplification of the result signals of the three parties. A 6-input AND / OR inverter circuit which outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 33 (a) and 33 (b) show a 4-input AN when the basic cell according to the third embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 33 (a), a 4-input AND / OR inverter circuit connects two basic cells 3 according to the third embodiment of the present invention.

Further, the first p-type power source program switch PD1 of the one basic cell BC1, the second bypass program point PB2, the fourth, seventh, eighth, tenth, thirteenth, thirteenth
14 program switches P4, P7, P8, P10, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting the P13 and P14 are programmed and the first p-type power source program switch PD1 of the other basic cell BC2 and the second n-type are programmed. Power source program switch PS2, fuse elements constituting the third, fifth, eighth and eleventh program switches P3, P5, P8, P11,
Program the antifuse element and p-type or n-type field effect transistor.

As a result, as shown in FIG. 33B, the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, the input signals A1 and A2 are first two-input logically amplified, and the resulting signal and the input signal B are combined. A 4-input AN that performs 2-input logic amplification, performs 2-input logic amplification of the resultant signal and the input signal C, and outputs the output signal X from the second output wiring Lout2.
A D / OR inverter circuit can be constructed.

(4) Description of Fourth Embodiment FIGS. 34 (a) and 34 (b) are configuration diagrams of a basic cell according to a fourth embodiment of the present invention, and FIGS. The block diagrams of the basic logic cells when the cells are programmed are shown respectively. The fourth embodiment is different from the first to third embodiments.
In this embodiment, the third p-type power source program switch P
D3, the third n-type ground program switch PS3 and the first,
The second bypass program switches PB1 and PB2 are connected.

That is, the fourth basic cell 4 is shown in FIG.
, The first to fourth transistors TP1, TP2, TN
1, TN2 and 20 various program switches PD1 to PD
3, PS1 to PS3, P1 to P14 and PB1 and PB2.

Further, in the program symbol diagram of FIG. 34B, the third p-type power source program switch PD3 is the second one.
Is connected between the source or drain extraction electrode SD3 of the transistor TP2 and the power supply line VDD, and the third n-type ground program switch PS3 is connected to the source or drain extraction electrode SD6 of the fourth transistor TN2 and the ground line GND. Connected between and.

Further, the first bypass program switch PB1 is connected between the extraction electrodes SD1 and SD3 of the sources or drains of the first and second transistors TP1 and TP2,
The second bypass program switch PB2 is the third, fourth
Of the transistors TN1 and TN2 are connected between the extraction electrodes SD4 and SD6 of the source or drain. The other structure is similar to that of the first embodiment, and the description thereof is omitted. Next, the program processing of the basic cell according to the fourth embodiment of the present invention will be described.

FIGS. 35 (a) and 35 (b) are configuration diagrams of an inverter circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 35 (a), the inverter circuit includes the first and second p-type power source program switches PD1 and PD2, the first n-type ground program switch PS1 and the fourth and fourth inverters, as in the third embodiment. Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming the twelfth program switches P4 and P12 is performed.

As a result, as shown in FIG. 35 (b), the transistor TP connected between the power supply line VDD and the ground line GND is connected.
It is possible to configure an inverter circuit which is composed of 2 and TN1 and which inverts and amplifies the input signal A and outputs the output signal X from the first output wiring Lout1.

FIGS. 36 (a) and 36 (b) are configuration diagrams of an inverter (power type) circuit when a basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 36 (a), the power type inverter circuit has a second p-type power source program switch PD2, similar to the third embodiment.
The second n-type ground program switch PS2 and the first, fifth, ninth and eleventh program switches P1, P5, P
9. A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming P11 are programmed.

As a result, as shown in FIG. 36B, the transistor TP connected between the power supply line VDD and the ground line GND is connected.
An inverter (power type) circuit composed of 1, TN1, TP2, and TN2, which inverts and amplifies the input signal A and outputs the output signal X from the second output wiring Lout2, can be configured.

FIGS. 37 (a) and 37 (b) are block diagrams of the transmission gate circuit when the basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 37 (a), the transmission gate circuit is similar to the third embodiment in that the first, third, fifth, eighth, tenth and twelfth program switches P1, P3, P5, P8, A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming P10 and P12 are programmed.

As a result, as shown in FIG. 37 (b), the first output wiring Lout1 extends to the connection terminal T1, the second output wiring Lout2 extends to the connection terminal T2, and the second transistor It is possible to configure a transmission gate circuit in which the gate G of TP2 is connected to the control terminal S1 and the gate G of the third transistor TN1 is connected to the control terminal S2.

FIGS. 38 (a) and 38 (b) show a 2-input NA when programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of an ND circuit. In FIG. 38 (a), the 2-input NAND circuit includes the first and third p-type power source program switches PD1 and PD3, the first n-type ground program switch PS1 and the third and twelfth program switches P3. , P12
The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting the above are programmed.

As a result, as shown in FIG. 38 (b), the first to fourth transistors TP1, TP2, TN1 and TN2 are provided, and the output signals X of the input signals A1 and A2 are logically amplified. 2-input NAN output from the first output line Lout1
A D circuit can be constructed.

FIGS. 39 (a) and 39 (b) are two-input NO when programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 39 (a), 2 inputs N
The OR circuit is the third p-type power source program switch PD
3, first and third n-type ground program switch PS1,
PS3 and each of the first, fifth and tenth program switches P1,
A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming P5 and P10 are programmed.

As a result, as shown in FIG. 39 (b), the first to fourth transistors TP1, TP2, TN1 and TN2 are provided, and the output signals X of the input signals A1 and A2 are logically amplified. 2-input NOR output from the second output wiring Lout2
A circuit can be constructed.

As described above, according to the basic cell of the fourth embodiment of the present invention, as shown in FIG.
The third p-type power source program switch PD3 is connected between the source or drain extraction electrode SD3 of the transistor TP2 and the power source line VDD, and the fourth transistor T
N2 source or drain extraction electrode SD6 and ground line GND
A third n-type ground program switch PS3 is connected between and. In addition, the first and second transistors TP1 and TP2
The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the second transistor and the second between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TN1 and TN2. The bypass program switch PB2 is connected.

Therefore, the four transistors TP1 and TP
2, TN1, TN2, total 22 program switches PD
1 to PD3, PS1 to PS3, P1 to P14, PB1 and PB2 form a minimum unit basic cell. This makes the first
Although the number of program switches is increased by four as compared with the embodiment described above, an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit and the like can be combined.

Next, the case of programming a plurality of basic cells according to the fourth embodiment of the present invention will be described. 40 (a) and 40 (b) are three-input NAND in the case of programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of a circuit. In Figure 40 (a), 3-input NA
The ND circuit first connects two basic cells 4 according to the fourth embodiment of the present invention. Here, the power supply line VDD and the ground line GN
D, the first and second p-type spare wirings LP1 and LP2, and the first and second
The second spare wirings LN1 and LN2 for n-type are connected. Also, 2
In one of the basic cells BC1 and BC2, a program point P6 is interposed between the first p-type spare wiring LP1 and a program point P7 is interposed between the second p-type spare wiring LP2 and the first output wiring Lout1. Then, the first n-type spare wiring LN1
A program point P13 is interposed therebetween, and a program point P14 is interposed between the second n-type spare wiring LN2 and the second output wiring Lout2.

Next, the first and second p-type power source program switches PD1 and PD2, and the first and second p-type power source program switches of the one basic cell BC1.
N type power source program switches PS1, PS2, fuse elements, antifuse elements, p type or n elements constituting the fourth, seventh and thirteenth program switches P4, P7, P13.
Type field effect transistor is programmed, and fuse elements constituting the first, third p-type power source program switches PD1, PD3, third and twelfth program switches P3, P12 of the other basic cell BC2 , Antifuse elements, p-type or n-type field effect transistors are programmed.

As a result, as shown in FIG. 40 (b), the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3 and output the output signal X from the first output wiring. 3-input NAN output from Lout1
A D circuit can be constructed.

41 (a) and 41 (b) are three-input NO when programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of an R circuit. 41 (a), 3 inputs N
The OR circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Further, the first and second p-type power source program switches PD1 and PD2 of the one basic cell BC1 and the first and second p-type power source program switches
N type power source program switches PS1, PS2, fourth, sixth, eleventh and fourteenth program switches P4, P6, P
The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting 11 and P14 are programmed, and the first and third n-type power source program switches PS1 and PS3 of the other basic cell BC2 are programmed. Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor which form each of the fifth and tenth program switches P5 and P10 is performed.

As a result, as shown in FIG. 41B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3 and output the output signal X from the second output wiring. 3-input NAN output from Lout2
A D circuit can be constructed.

42 (a) and 42 (b) are four-input NA when programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of an ND circuit. In FIG. 42A, the 4-input NAND circuit first connects two basic cells 4 according to the fourth embodiment of the present invention.

Next, the first and third p-type power source program switches PD1, PD3 of the one basic cell BC1, the first n-type power source program switch PS1, the third, seventh and thirteenth programs The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor forming the switches P3, P7, and P13 are programmed, and the other basic cell B is processed.
C2 first and third p-type power source program switch PD1,
Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor which compose PD3 and the third and twelfth program switches P3 and P12 is performed.

As a result, as shown in FIG. 42B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3, A4 and output the output signal X from the first signal. A 4-input NAND circuit that outputs from the output wiring Lout1 can be configured.

43 (a) and 43 (b) are four-input NO in the case where the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of an R circuit. In FIG. 43 (a), 4 inputs N
The OR circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

The first p-type power source program switch PD1, the second and third n-type power source program switches PS1, PS3, the sixth, the tenth, and the fourteenth program switches of one of the basic cells BC1. The fuse element, the antifuse element, and the p-type or n-type field effect transistor forming P6, P10, and P14 are programmed and the other basic cell B
C2 first and third n-type power source program switch PS1,
Program processing of a fuse element, an anti-fuse element, and a p-type or n-type field effect transistor which form PS3, each of the fifth and tenth program switches P5, P10 is performed.

As a result, as shown in FIG. 43 (b), the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which logically amplify the input signals A1, A2, A3, A4 and output the output signal X of the second signal. It is possible to configure a 4-input NAND circuit that outputs from the output wiring Lout2.

FIGS. 44 (a) and 44 (b) show a 3-input AN in the case of programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 44 (a), a 3-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

The first and second p-type power source program switches PD1 and PD2 of the one basic cell BC1 and the first and second p-type power source program switches
N type power source program switches PS1, PS2, fourth, seventh, eleventh and fourteenth program switches P4, P7, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor which constitute 11, P14 are programmed, and the first n-type power source program switch PS1, first, third of the other basic cell BC2 is programmed. , Fuse elements, antifuse elements, and p-type or n-type field effect transistors forming the fifth and eleventh program switches P1, P3, P5, and P11 are programmed.

As a result, as shown in FIG. 44B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, two-input logical amplification of the input signals A1 and A2 is performed first, and the resultant signal and the input signal B are combined. Perform logical amplification and output signal X
3-input AND · O for outputting from the second output wiring Lout2
An R inverter circuit can be configured.

FIGS. 45 (a) and 45 (b) show a 4-input AN in the case of programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 45 (a), a 4-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Also, the first, third p-type power source program switches PD1, PD3, third, seventh, ninth, thirteenth, fourteenth program switches P3, P of one of the basic cells BC1.
7, P9, P13, P14 fuse elements, anti-fuse elements, p-type or n-type field effect transistors are programmed, and the first p-type power source program switch PD1 of the other basic cell BC2, The program processing of the fuse element, antifuse element, p-type or n-type field effect transistor constituting the n-type power source program switch PS2, the third, fifth and eleventh program switches P3, P5 and P11 To do.

As a result, as shown in FIG. 45 (b), the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, three-input logical amplification is performed first with the input signals A1, A2, A3, and the resulting signal and the input signal B 4-input AN that performs logical amplification with and outputs the output signal X from the second output wiring Lout2
A D / OR inverter circuit can be constructed.

FIGS. 46 (a) and 46 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 46 (a), a 4-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Further, the first and third p-type power source program switches PD1 and PD3 of the one basic cell BC1, the first n-type power source program switch PS1, the third, the seventh, the eleventh and the tenth, respectively.
A fuse element, an anti-fuse element, a p-type or n-type constituting each of 14 program switches P3, P7, P11, P14
Type field effect transistor is programmed, and the first n-type power source program switch PS1, the first, third, fifth and eleventh program switches P1, P3, P5, P11 of the other basic cell BC2. The fuse element, the anti-fuse element, and the p-type or n-type field-effect transistor constituting the above are programmed.

As a result, as shown in FIG. 46 (b), the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, which first perform two-input logical amplification of the input signals A1 and A2, and also two input signals A3 and A4. It is possible to configure a 4-input AND / OR inverter circuit which performs input logical amplification, logically amplifies the result signals of both, and outputs the output signal X from the second output wiring Lout2.

FIGS. 47 (a) and 47 (b) show a 4-input AN when the basic cell according to the fourth embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 47 (a), a 4-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

The first, third n-type power source program switches PS1, PS3, the first, fourth, seventh, tenth, and fourteenth program switches P1, P of one of the basic cells BC1 are also provided.
4, P7, P10, P14, fuse elements, anti-fuse elements, p-type or n-type field-effect transistors are programmed, and the other first and third basic cells BC2 are programmed.
P-type power source program switch PD1, PD3, third n
The power source program switch PS3 for mold, the fuse element, the anti-fuse element, and the p-type or n-type field effect transistor which form each of the third and tenth program switches P3 and P10 are programmed.

As a result, as shown in FIG. 47 (b), the first to fourth transistors TP11, TP12 of the basic cell BC1.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2. The input signals A1 and A2 are first two-input logically amplified, and the resultant signal and the input signals B1 and B2 are obtained. And a three-input logic amplification with the output signal X is output from the second output wiring Lout2 4
An input AND / OR inverter circuit can be constructed.

FIGS. 48, 49 (a) and 49 (b) are block diagrams of a 6-input AND / OR inverter circuit when the basic cell according to the fourth embodiment of the present invention is programmed. In FIG. 48, a 6-input AND / OR inverter circuit connects three basic cells 4 according to the fourth embodiment of the present invention.

For example, the first n-type power source program switch PS1 of the first basic cell BC1, the first, third, fifth, seventh, eleventh, and fourteenth program switches P1, P3, P.
5, P7, P11, P14, fuse elements, antifuse elements, p-type or n-type field effect transistors are programmed, and the first n-type power source program switch PS1 of the second basic cell BC2 is programmed. A fuse element, an anti-fuse element, a p-type or n-type field effect transistor forming the first bypass program switch PB1, the third, sixth, eleventh and fourteenth program switches P3, P6, P11, P14. Program processing of. Furthermore, the third
Second p-type power source program switch PD2 of the basic cell BC3, first n-type power source program switch PS1, second, fourth and eleventh program switches P2, P4, P
The fuse element, the antifuse element, and the p-type or n-type field-effect transistor constituting 11 are programmed.

As a result, as shown in FIGS. 49A and 49B, the first to fourth transistors TP11 of the basic cell BC1 are formed.
, TP12, TN11, TN12, the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2 and the first to fourth transistors TP31, TP32 of the basic cell BC3.
, TN31, TN32, and the input signals A1, A2
, Two-input logic amplification of the input signals B1 and B2, further two-input logic amplification of the input signals C1 and C2, and three-input logic amplification of the result signals of the three parties. A 6-input AND / OR inverter circuit which outputs the output signal X from the second output wiring Lout2 can be configured.

FIGS. 50 (a) and 50 (b) show a 4-input AN in the case of programming the basic cell according to the fourth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 50 (a), a 4-input AND / OR inverter circuit connects two basic cells 4 according to the fourth embodiment of the present invention.

Also, the third p-type power source program switch PD3 of the one basic cell BC1, the second n-type power source program switch PS2, the first, third, seventh, ninth, thirteenth, and thirteenth
14 program switches P1, P3, P7, P9, P
A fuse element, an antifuse element, and a p-type or n-type field-effect transistor constituting the P13 and P14 are programmed, and the first p-type power source program switch PD1 and the second bypass of the other basic cell BC2 are programmed. Program point PB2, 4th and 10th program switches P4, P
A fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor constituting 10 are programmed.

As a result, as shown in FIG. 50B, the first to fourth transistors TP11 and TP12 of the basic cell BC1 are provided.
, TN11, TN12 and the first to fourth transistors TP21, TP22, TN21, TN22 of the basic cell BC2, the input signals A1 and A2 are first two-input logically amplified, and the resulting signal and the input signal B are combined. A 4-input AN that performs 2-input logic amplification, performs 2-input logic amplification of the resultant signal and the input signal C, and outputs the output signal X from the second output wiring Lout2.
A D / OR inverter circuit can be constructed.

51 (a) to 51 (c) are configuration diagrams (part 1) of a logic circuit programmable from the basic cell according to the fourth embodiment of the present invention. FIG. 51 (a) shows a 3-input OR / AND inverter circuit.
It is a symmetrical type logic circuit of an OR inverter circuit. Further, FIG. 51B shows a 4-input OR / AND inverter circuit, which is a symmetrical type logic circuit of the 4-input AND / OR inverter circuit. Furthermore, FIG. 51 (c) shows a 4-input OR
It is an AND inverter circuit, which is a symmetrical type logic circuit of a 4-input AND / OR inverter circuit. For this reason,
The program processing of each program point of the basic cell can be easily realized by connecting symmetrically.

Further, FIGS. 52A to 52C are block diagrams (part 2) of the logic circuit programmable by the basic cell according to the fourth embodiment of the present invention. FIG. 52A shows a 4-input OR / AND inverter circuit,
It is a symmetrical type logic circuit of an OR inverter circuit. Figure
52 (b) is a 6-input OR / AND inverter circuit,
It is a symmetrical type logic circuit of a 6-input AND / OR inverter circuit. Furthermore, FIG. 52 (c) shows a 4-input OR / AND
It is an inverter circuit and is a symmetrical type logic circuit of a 4-input AND / OR inverter circuit. Therefore, the program processing at each program point of the basic cell can be easily realized by connecting symmetrically.

As a result, 21 basic logic cells can be assembled by programming the two basic cells according to the fourth embodiment. In addition, Figure 53
(A), (b) has shown the explanatory view of the D-type flip-flop circuit which combined the basic cell which concerns on the 4th Example of this invention. In FIG. 53 (a), a D-type flip-flop circuit DFF is an application circuit in which 12 basic cells according to the first to eighth embodiments of the present invention are combined.

For example, eight inverter circuits IN1 to IN8 based on the basic cells of the first to third or fourth embodiments and 4
The individual transmission gate circuits TG1 to TG4 are connected. As a result, the D-type flip-flop circuit DFF can be constructed. In addition, the total number of transistors formed is 16 transistors forming four transmission gate circuits TG1 to TG4 and 32 transistors forming eight inverter circuits IN1 to IN8, for a total of 48 transistors.

As a result, the D-type flip-flop circuit can be configured with about half the number of transistors as compared with the conventional example. It should be noted that, as compared with the basic cell having the minimum unit of two types, that is, the transistor pair tile portion and the RAM logic tile portion as in the conventional example, the D-type flip-flops are combined by the combination of the basic cells according to the first to eighth embodiments. Since the flop can be easily configured, it is possible to improve the usage efficiency.

(5) Description of Fifth Embodiment FIG. 54 (a) is a block diagram of a basic cell according to a fifth embodiment of the present invention. The fifth embodiment differs from the first to fourth embodiments in the fifteenth and sixteenth program switches P1.
5, P16 are added, and each transistor TP1, TP2, TN
1, TN2 source or drain extraction electrodes SD1 to SD6
First to fifth program switches P1 to P connected to
The fifth and eighth to twelfth program switches P8 to P12 are not directly connected to the first and second output wirings Lout1 and Lout2.

That is, the fifth basic cell 5 is shown in FIG.
In the program symbol diagram, the first to fourth transistors TP1, TP2, TN1 and TN2 and 20 various program switches PD1, PD2, PS1, PS2, P1 to P16 are provided.

Further, the first to fourth transistors TP1 and T4
The gates G of P2, TN1 and TN2 are connected to the input wiring Lin,
The source or drain extraction electrodes SD1 to SD6 of the transistors TP1, TP2, TN1 and TN2 are the first and second p-type power source program switches PD1 and PD2, and the first and second n-type ground program switches PS1 and Power line VDD, ground line GND, first and second output lines Lout1 and Lout2, first and second p-type spare lines LP1, with PS2 and first to sixteenth program switches P1 to P16 interposed. LP2 or the first and second n-type spare lines LN1 and LN2.

That is, the source or drain extraction electrode SD1 of the first transistor TP1 is connected to the power supply line VDD via the first p-type power supply program switch PD1 and the first program switch P1 via the first power supply line VDD. The second p-type preliminary wiring LP2, the second p-type preliminary wiring LP2 and the first p-type preliminary wiring LP1 are connected via the second program switch P2.

The first and second transistors TP1, T
The extraction electrode SD2 of the source or drain of P2 is the second p
Power source line V via the power source program switch PD2 for mold
The second with the DD and the third program switch P3 interposed
Is connected to the p-type spare wiring LP2. The source / drain extraction electrode SD3 of the second transistor TP2 has a second n-type interposition of the fourth program switch P4 and a second p-type spare wiring LP2 and a fifth program switch P5. It is connected to the die preliminary wiring LN2 and the first p-type preliminary wiring LP1 via the sixth program switch P6.

Further, the source or drain extraction electrode SD4 of the third transistor TN1 is connected to the ground line GND via the first n-type ground program switch PS1 and the eighth line.
Second p-type spare wiring LP2 via the program switch P8, second n-type spare wiring LN2 through the ninth program switch P9, and first n-type spare wiring LN1. Connected to. Third and fourth transistors TN
The source or drain extraction electrode SD5 of TN2 is connected to the ground line GND through the second n-type ground program switch PS2 and the second p-type preliminary wiring through the tenth program switch P10. It is connected to LP2.

The source or drain extraction electrode SD6 of the fourth transistor TN2 is connected to the second n-type spare wiring LN2 via the eleventh program switch P11.
It is connected to the second p-type spare wiring LP2 with twelve program switches P12 interposed and to the first n-type spare wiring LN1 with a thirteenth program switch P13 interposed.

The second p-type spare wiring LP2 is connected to the seventh program switch P7, and the second n-type spare wiring LN2 is connected to the fourteenth program switch P14. The second p-type spare line LP2 is connected to the first output line Lout1 via the fifteenth program switch P15, and the second n-type spare line LN2 includes the sixteenth program switch P16. Then, it is connected to the second output wiring Lout2. The other structure is similar to that of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell of the fifth embodiment of the present invention, as shown in FIG.
~ Fourth transistor TP1, TP2, TN1, TN2 and 20 various program switches PD1, PD2, PS1, PS2, P1 to P16 for connecting between them and between wirings are provided,
The second p-type spare wiring LP2 is connected to the first output wiring Lout1 through the fifteenth program switch P15, and the second n-type spare wiring LN2 is connected to the sixteenth program switch P15.
It is connected to the second output wiring Lout2 with 16 interposed.

Therefore, the four transistors TP1 and TP
2, TN1, TN2 and 20 program switches PD in total
1, PD2, PS1, PS2, and P1 to P16 form a basic cell of the minimum unit. Further, by selectively conducting (programming) the fifteenth and sixteenth program switches P15 and P16, the second p-type spare wiring LP2 and the first output wiring Lout1 are connected to each other, and the second Of the n-type spare wiring LN2 and the second output wiring Lout2,
By the non-selection (non-program processing) of the 15th and 16th program switches P15 and P16, the first and second output wirings Lout
1 and Lout1 can be provided with a through wiring function.

The through wiring function is a wiring that passes the fifth basic cell 5 in the horizontal direction. When the basic cells adjacent in the horizontal direction are directly connected to each other or when the shortest wiring distance is required. It is valid.

As a result, the number of program switches is increased by 2 compared to the first embodiment, but an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NA are applied while applying the through wiring function.
An ND circuit, a two-input NOR circuit, etc. can be combined. It should be noted that by connecting two first basic cells, a 3-input NAN
D circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit, 4-input AND / OR inverter circuit,
It becomes possible to configure a 6-input AND / OR inverter circuit or the like by connecting three fifth basic cells 5.

(6) Description of Sixth Embodiment FIG. 54 (b) is a block diagram of a basic cell according to the sixth embodiment of the present invention. The sixth embodiment differs from the fifth embodiment in that the third p-type power source program switch PD3 is used.
And a third n-type ground program switch PS3 for connection to the ground line GND.

That is, the sixth basic cell 6 is shown in FIG.
In the program symbol diagram, the first to fourth transistors TP1, TP2, TN1 and TN2 and 20 various program switches PD1, PD2, PS1, PS2, P1 to P16 are provided.

The third p-type power program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power line VDD, and the third n-type ground program switch PS3 is The fourth transistor TN2 is connected between the source or drain extraction electrode SD6 and the ground line GND. The rest of the configuration is similar to that of the fifth embodiment, so its explanation is omitted.

As described above, according to the basic cell of the sixth embodiment of the present invention, as shown in FIG.
~ Fourth transistor TP1, TP2, TN1, TN2 and 22 various program switches PD1, PD2, PS1, PS2, P1 to P16 for connecting between them and between wirings are provided,
The source or drain extraction electrode SD3 of the second transistor TP2 is connected to the third p-type power source program switch PD3.
Is connected to the power supply line VDD with the third electrode interposed therebetween, and the source or drain extraction electrode SD6 of the fourth transistor TN2 is connected to the third
Is connected to the ground line GND through the n-type ground program switch PS3.

Therefore, the four transistors TP1 and TP
2, TN1, TN2, total 22 program switches PD
1 to PD3, PS1 to PS3, and P1 to P16 form a minimum unit basic cell. Further, like the fifth basic cell 5, the first and second output lines L are formed by non-selection (non-program processing) of the fifteenth and sixteenth program switches P15 and P16.
It is possible to give out1 and Lout1 a through wiring function.

As a result, the number of program switches is increased by 4 compared with the first embodiment, but like the fifth embodiment, the inverter circuit, while applying the through wiring function,
An inverter (power type) circuit, a transmission gate circuit, a 2-input NAND circuit, a 2-input NOR circuit, etc. can be combined. In addition, by connecting two sixth basic cells, a 3-input NAND circuit, a 3-input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, and a 4-input ANDO
It is possible to configure a 6-input AND / OR inverter circuit or the like by connecting three R inverter circuits and the sixth basic cell 6.

(7) Description of Seventh Embodiment FIG. 55 (a) is a block diagram of a basic cell according to a seventh embodiment of the present invention. The seventh embodiment differs from the fifth embodiment in that the first and second bypass program switches PB1 and PB2 are connected.

That is, the seventh basic cell 7 is shown in FIG.
In the program symbol diagram of FIG. 1, first to fourth transistors TP1, TP2, TN1 and TN2 and 22 various program switches PD1, PD2, PS2, PS1, PS2, P1 to P16 and PB are provided.
1, consisting of PB2.

The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2, and the second bypass program switch PB2 is the third. , Of the fourth transistors TN1 and TN2 are connected between the extraction electrodes SD4 and SD6 of the source or drain. The rest of the configuration is similar to that of the fifth embodiment, so its explanation is omitted.

In this way, according to the basic cell of the seventh embodiment of the present invention, as shown in FIG.
~ Fourth transistor TP1, TP2, TN1, TN2 and 22 various program switches PD1, PD2, PS1, PS2, P1 to P16 and PB1, PB for connecting between them and between wirings
B2 is provided, and the first and second transistors TP1 and TP2 have a first electrode between the source or drain extraction electrodes SD1 and SD3.
The bypass program switch PB1 is connected, and the second bypass program switch PB2 is connected between the source or drain extraction electrodes SD4, SD4 of the third and fourth transistors TN1, TN2.

Therefore, the four transistors TP1 and TP
2, TN1, TN2, total 22 program switches PD
1, PD2, PS1, PS2, P1 to P16, PB1 and PB2 form a minimum unit basic cell. Further, similar to the third embodiment, the first bypass program switch PB1
By this, the source or drain lead-out electrodes SD1 and SD3 of the first and second transistors TP1 and TP2 can be directly connected without the second p-type preliminary wiring LP2, and similarly, the second bypass With the program switch PB2 for
The second n-type spare wiring L is provided between the lead-out electrodes SD4 and SD6 of the sources or drains of the third and fourth transistors TN1 and TN2.
It is possible to connect directly without going through N2.

As a result, the number of program switches is increased by four as compared with the first embodiment, but like the fifth embodiment, the inverter circuit, while applying the through wiring function,
An inverter (power type) circuit, a transmission gate circuit, a 2-input NAND circuit, a 2-input NOR circuit, etc. can be combined. In addition, the seventh basic cell 7
3 input NAND circuit, 3 input NOR circuit, 4 connected individually
Input NAND circuit, 4-input NOR circuit, 4-input AND circuit
It becomes possible to construct a 6-input AND / OR inverter circuit by connecting three OR basic circuits or seven seventh basic cells.

(8) Description of Eighth Embodiment FIG. 55 (b) is a block diagram of a basic cell according to an eighth embodiment of the present invention. The eighth embodiment differs from the first embodiment in that the third p-type power source program switch PD3 is used in the eighth embodiment.
And a third n-type ground program switch PS3, and first and second bypass program switches PB1 and PB2 are connected.

That is, the eighth basic cell 8 is shown in FIG. 55 (b).
In the program symbol diagram of FIG. 1, first to fourth transistors TP1, TP2, TN1 and TN2 and 24 various program switches PD1, PD2, PS1, PS2, P1 to P16 and PB are provided.
1, consisting of PB2.

The third p-type power source program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power source line VDD, and the third
The n-type ground program switch PS3 is connected between the source or drain extraction electrode SD6 of the fourth transistor TN2 and the ground line GND.

Further, the first bypass program switch PB1 is connected between the extraction electrodes SD1 and SD3 of the sources or drains of the first and second transistors TP1 and TP2,
The second bypass program switch PB2 is the third, fourth
Of the transistors TN1 and TN2 are connected between the extraction electrodes SD4 and SD6 of the source or drain. Other configurations are fifth
Since it is the same as the embodiment described above, the description thereof will be omitted.

As described above, according to the basic cell of the eighth embodiment of the present invention, as shown in FIG.
~ Fourth transistor TP1, TP2, TN1, TN2, and 24 various program switches PD1, PD2, PS1, PS2, P1 to P14 for connecting between them and between wirings are provided,
A third p-type power source program switch PD3 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power supply line VDD, and the source or drain extraction electrode SD6 of the fourth transistor TN2 is connected. And the ground line GND between the third ground program switch PS3 for n-type
Are connected. In addition, the first and second transistors TP1,
The first bypass program switch PB1 is connected between the source or drain extraction electrodes SD1 and SD3 of TP2, and the first bypass program switch PB1 is connected between the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TN1 and TN2. The second bypass program switch PB2 is connected.

Therefore, the four transistors TP1 and TP
2, TN1, TN2 and 24 program switches PD in total
1 to PD3, PS1 to PS3, P1 to P16, PB1 and PB2 form a minimum unit basic cell. Further, similar to the fourth embodiment, for example, in the eighth basic cell 8, the first and third p-type power source program switches PD1, PD3, the first n-type ground program switch PS1 and the A three-input program switch P3, P12, a fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor are programmed to perform a 2-input NAND.
It becomes possible to configure a circuit.

As a result, the number of program switches is increased by 6 as compared with the first embodiment, but like the fifth embodiment, the inverter circuit, while applying the through wiring function,
An inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit, etc. can be combined. Also, by connecting two first basic cells, a 3-input NAND circuit, a 3-input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, and a 4-input AND / O
Connect the R inverter circuit and three first basic cells to
It becomes possible to configure an input AND / OR inverter circuit or the like.

The basic cells of the first to eighth embodiments of the present invention are suitable for forming a relatively small-scale logic gate circuit, whereas the basic cells of the ninth to twelfth embodiments described below are suitable. The basic cell according to the embodiment is suitable for forming a relatively large-scale logic gate circuit.

(9) Description of Ninth Embodiment FIG. 56 is a block diagram of a basic cell according to a ninth embodiment of the present invention. The ninth embodiment is different from the first to eighth embodiments in that eight transistors TP1 to TP4 and TN1 to TN4 are used.
To form a basic cell.

That is, the ninth basic cell 9 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 30 program switches PD1 to PD4 and PS1 to P for connecting between them and between wirings
It consists of S4, P1 to P22.

For example, the first to eighth transistors TP1 to
The gates G of TP4 and TN1 to TN4 are connected to the input wiring Lin, and the first to eighth transistors TP1 to TP4 and TN1 to TN4 are connected.
Source or drain extraction electrodes SD1 to SD12 are first
~ Fourth p-type power source program switches PD1 to PD4, first to fourth n-type grounding program switches PS1 to PS4 and first to twenty-second program switches P1 to P22 are interposed, and power source line VDD and ground Line GND, first and second output wiring Lou
Connected to t1 and Lout2.

That is, the extraction electrode SD1 of the source or drain of the first transistor TP1 is connected to the power line VDD via the first p-type power program switch PD1 and the first program switch P1 via the first power switch VDD. The second output wiring Lout2 is connected to the first output wiring Lout1 via the second program switch P2.

Further, the first and second transistors TP1, T
The extraction electrode SD2 of the source or drain of P2 is the second p
Power source line V via the power source program switch PD2 for mold
The first program with the DD and the third program switch P3
Of the second transistor T connected to the output wiring Lout1 of
The source or drain extraction electrode SD3 of P2 is connected to the first output line Lou via the fourth program switch P4.
t1 and the second program switch P5
Of the third transistor TP3) and the output electrode Lout2 of the third transistor TP3) via the sixth program switch P6.

Further, the source or drain extraction electrode SD4 of the third transistor TP3 is connected to the power line VDD through the third p-type power program switch PD3 and the seventh
Of the third and fourth transistors TP3 and TP4 or the second output wiring Lout2 via the program switch P7 and the first output wiring Lout1 via the eighth program switch P8. The drain extraction electrode SD5 is connected to the power supply line VDD and the ninth program switch P9 via the fourth p-type power supply program switch PD4.
Is connected to the first output line Lout1.

The source or drain lead-out electrode SD6 of the fourth transistor TP4 has a first output line Lout1 with a tenth program switch P10 interposed and a second electrode with an eleventh program switch P11 interposed therebetween. Output wiring L
Connected to out2.

The source or drain extraction electrode SD7 of the fifth transistor TN1 is connected to the ground line GND through the first n-type ground program switch PS1 and the thirteenth program switch P12. 1 output wiring L
out1 and the second output wiring Lout2 through the fourteenth program switch P13. The source or drain extraction electrodes SD8 of the fifth and sixth transistors TN1 and TN2 are connected to the ground line GND through the second n-type ground program switch PS2 and the fourteenth program switch P14.
Is connected to the second output wiring Lout2.

The source or drain extraction electrode SD9 of the sixth transistor TN2 has a first output line Lout2 with a fifteenth program switch P15 interposed therebetween and a first sixteenth program switch P16 interposed therebetween. Output wiring L
out1 and the seventeenth program switch P17 are interposed to be connected to the extraction electrode SD10 of the source or drain of the seventh transistor TP3). The source or drain extraction electrode SD10 of the seventh transistor TN3 is connected to the ground line GND through the third n-type ground program switch PS3.
Is connected to the first output line Lout1 via the eighteenth program switch P18 and to the second output line Lout2 via the nineteenth program switch P19.

Furthermore, the seventh and eighth transistors TN3,
The source or drain extraction electrode SD11 of TN4 is
Is connected to the ground line GND through the n-type ground program switch PS4 and the second output wiring Lout2 through the twentieth program switch P20. The extraction electrode SD12 of the source or drain of the eighth transistor TN4 is
It is connected to the second output wiring Lout2 via the 21st program switch P21 and to the first output wiring Lout1 via the 22nd program switch P22. The other structure is similar to that of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell of the ninth embodiment of the present invention, as shown in FIG.
Of the transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 for connecting between them and between wirings.
.About.PD4, PS1 to PS4, P1 to P22.

Therefore, eight transistors TP1 to TP
4, TN1 to TN4 and a total of 30 program switches PD
1 to PD4, PS1 to PS4, P1 to P22 form a minimum unit basic cell. For example, among the ninth basic cell 9, the first, second, and fourth p-type power source program switches PD1, PD2, and PD4, the first and second n-type grounding program switches PS1 and PS2, and the fourth , 8th, 10th, 17th, 22nd program switches P4, P8, P10, P17, P22, fuse elements, antifuse elements, p-type or n-type.
Type field effect transistor is programmed.

As a result, the source or drain extraction electrode SD1 of the first transistor TP1 and the power supply line VDD are connected via the first p-type power supply program switch PD1 and the first and second transistors TP1 and TP2 are connected. The source or drain extraction electrode SD2 and the power supply line VDD are connected via a second p-type power supply program switch PD2.

The source or drain lead-out electrode SD3 of the second transistor TP2 and the first output line Lout1 are connected via the fourth program switch P4, and the source or drain of the fourth transistor TP4 is led out. The electrode SD4 and the first output wiring Lout1 are connected via the eighth program switch P8. Further, the source or drain extraction electrodes SD5 of the third and fourth transistors TP3 and TP4 are connected to the power supply line VDD via a fourth p-type power supply program switch PD4, and the fourth transistor TP4 is connected.
The source or drain extraction electrode SD6 and the first output line Lout1 are connected via the tenth program switch P10.

Further, the source or drain extraction electrode SD7 of the fifth transistor TN1 and the ground line GND are connected via the first n-type ground program switch PS1.
The source or drain lead-out electrodes SD8 of the fifth and sixth transistors TN1 and TN2 are connected to the ground line GND through the second p-type power source program switch PS2.

Further, the extraction electrode SD9 of the source or drain of the sixth transistor TN2 and the seventh transistor TN3
Is connected to the source / drain extraction electrode SD10 via the seventeenth program switch P17, and the source / drain extraction electrode SD12 and the first output wiring Lout1 of the eighth transistor TN4 are connected to the twenty-second program switch P22.
Connected via. .

As a result, a three-input NAND circuit is formed by the first to fourth transistors TP1 to TP4 made of p-type field effect transistors and the fifth to eighth transistors TN1 to TN4 made of n-type field effect transistors. It becomes possible to do. From this, a total of 30 program switches PD1 to PD4, PS1 to PS4, P1 to P22 are appropriately set.
Eight transistors T by programming
P1 to TP4, TN1 to TN4, 3-input NAND circuit, 3
Input NOR circuit, 4-input NAND circuit, 4-input NOR circuit, 3-input AND / OR inverter circuit, 4-input AND circuit
It becomes possible to configure a basic logic cell such as an OR inverter circuit.

(10) Description of Tenth Embodiment FIG. 57 is a block diagram of a basic cell according to a tenth embodiment of the present invention. The tenth embodiment differs from the ninth embodiment in that the fifth and sixth p-type power source program switches PD are
5, PD6 and the fifth and sixth n-type ground program switches PS5, PS6 are connected.

That is, the tenth basic cell 10 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
To TP4, TN1 to TN4 and 34 various program switches PD1 to PD6, PS1 to P for connecting between them and between wirings
It consists of S6, P1 to P22.

For example, the fifth p-type power source program switch PD5 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power source line VDD, and the sixth p-type power source program switch PD6. Is connected between the source or drain extraction electrode SD6 of the fourth transistor TP4 and the power supply line VDD. The fifth n-type ground program switch PS5 is connected between the source or drain extraction electrode SD9 of the sixth transistor TN2 and the ground line GND, and the sixth n-type ground program switch PS6.
Is connected between the extraction electrode SD12 of the source or drain of the eighth transistor TN4 and the ground line GND. The rest of the configuration is the same as that of the ninth embodiment, so its explanation is omitted.

As described above, according to the basic cell of the tenth embodiment of the present invention, as shown in FIG.
Of the transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 for connecting between them and between wirings.
To PD4, PS1 to PS4, P1 to P22, the extraction electrode S of the source or drain of the second transistor TP2.
A fifth p-type power source program switch PD5 is connected between D3 and the power source line VDD, and a fourth transistor TP4 is provided.
The sixth p-type power source program switch PD6 is connected between the source or drain extraction electrode SD6 and the power supply line VDD, and the source or drain extraction electrode SD9 of the sixth transistor TN2 and the ground line GND are connected. Between the fifth n
Type ground program switch PS5 is connected to the source or drain extraction electrode SD1 of the eighth transistor TN4.
A sixth n-type ground program switch PS6 is connected between 2 and the ground line GND.

Therefore, eight transistors TP1 to TP
4, TN1 to TN4, total 34 program switches PD
1 to PD6, PS1 to PS6, and P1 to P22 form a minimum unit basic cell. For example, among the tenth basic cell 10, the first, third, fifth and sixth p-type power source program switches PD1, PD3, PD5, PD6, the first n-type grounding program switch PS1 and the third , A 9-th, 17-th, and 22-th program switch P3, P9, P17, P22, a fuse element, an anti-fuse element, and a p-type or n-type field-effect transistor are programmed to perform a 4-input NAND circuit. Can be configured.

As a result, the number of program switches is increased by 4 as compared with the ninth embodiment, but a total of 34 program switches PD1 to PD4, PS1 to PS4, P1 to P22 are appropriately programmed. By means of eight transistors TP1 to TP4 and TN1 to TN4, a 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input N circuit
Basic logic cells such as an OR circuit, a 3-input AND / OR inverter circuit, and a 4-input AND / OR inverter circuit can be configured.

(11) Description of Eleventh Embodiment FIG. 58 is a block diagram of a basic cell according to an eleventh embodiment of the present invention, and FIGS. 59 to 67 show respective cases when the basic cell is programmed. The respective configuration diagrams of the basic logic cells are shown. The difference from the ninth embodiment is that in the eleventh embodiment, the first
~ Third bypass program switches PB1 to PB4 are connected.

That is, the eleventh basic cell 11 is the same as the first to eighth transistors TP1 in the program symbol diagram of FIG.
~ TP4, TN1 ~ TN4 and 34 various program switches PD1 ~ PD4, PS1 ~ P for connecting between them and between wirings
It consists of S4, PB1 to PB4, P1 to P22.

For example, the first bypass program switch PB1 is connected between the extraction electrodes SD1 and SD3 of the sources or drains of the first and second transistors TP1 and TP2,
Further, the second bypass program switch PB2 is connected between the extraction electrodes SD4, SD6 of the sources or drains of the third and fourth transistors TP3, TP4.

Further, the third bypass program switch PB3 is connected between the extraction electrodes SD7 and SD9 of the sources or drains of the fifth and sixth transistors TN1 and TN2,
The fourth bypass program switch PB4 is connected between the extraction electrodes SD10 and SD12 of the sources or drains of the seventh and eighth transistors TN3 and TN4. The other structure is similar to that of the first embodiment, and the description thereof is omitted.

As described above, according to the basic cell of the eleventh embodiment of the present invention, as shown in FIG.
Of the transistors TP1 to TP4, TN1 to TN4, and a plurality of various program switches PD1 for connecting between them and between wirings.
To PD4, PS1 to PS4, P1 to P22, the first,
Source or drain extraction electrodes SD1 and SD3 of the second transistors TP1 and TP2 and third and fourth transistors T
Source or drain extraction electrodes SD4, SD6 of P3, TP4
Between the first and second bypass program switches PB1,
PB2 is connected to each of the fifth and sixth transistors T
N1 and TN2 source or drain extraction electrodes SD7 and SD9
The third and fourth bypass program switches PB3 and PB4 are connected between the source or drain extraction electrodes SD10 and SD12 of the seventh and eighth transistors TN3 and TN4, respectively.

Therefore, eight transistors TP1 to TP
4, TN1 to TN4, total 34 program switches PD
1 to PD4, PS1 to PS4, PB1 to PB4, and P1 to P22 form a minimum unit basic cell. Also, the first and second
Of the bypass program switches PB1 and PB2 between the source and drain extraction electrodes SD1 and SD3 of the first and second transistors TP1 and TP2, and the source or drain extraction electrodes SD4 and SD4 of the third and fourth transistors TP1 and TP2.
The SD6 can be directly connected without the first output wiring Lout1.

Similarly, the third and fourth bypass program switches PB3 and PB4 are used to extract the source or drain electrodes of the fifth and sixth transistors TN1 and TN2.
It is possible to directly connect the SD9 and the lead-out electrodes SD10 and SD12 of the sources or drains of the seventh and eighth transistors TN3 and TN4 without the second output wiring Lout2.

As a result, the number of program switches is increased by 4 as compared with the ninth embodiment, but a total of 34 program switches PD1 to PD4, PS1 to PS4, P1 to P22 are appropriately programmed. Therefore, as shown in FIGS. 59 to 67, by using eight transistors TP1 to TP4 and TN1 to TN4, a 3-input NAND circuit, a 3-input NOR circuit, a 4-input NAND circuit, a 4-input NOR circuit, and a 3-input AND / OR circuit are provided.
It becomes possible to configure a basic logic cell such as an inverter circuit and a 4-input AND / OR inverter circuit.

Next, the program processing of the basic cell according to the eleventh embodiment of the present invention will be described. Fig. 59
(A), (b) is a block diagram of a 3 input NAND circuit at the time of programming the basic cell which concerns on the 11th Example of this invention. In FIG. 59 (a), the 3-input NAND circuit is
First, second, and fourth p-type power source program switch PD
1, PD2, PD4, 1st, 2nd n-type power source program switches PS1, PS2, 4th, 8th, 10th, 17th, 22nd program switches P4, P8, P10, P17, P22 Constituting fuse element, anti-fuse element, p-type or n
Type field effect transistor is programmed.

As a result, as shown in FIG. 59 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 3-input NAND circuit which logically amplifies 3 and outputs the output signal X from the first output wiring Lout1.

FIGS. 60 (a) and 60 (b) are three-input NO when programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 60 (a), 3 inputs N
The OR circuit includes first, second p-type power source program switches PD1, PD2, first, second, and fourth n-type power source program switches PS1, PS2, PS4, fourth, sixth, eleventh, First
5, 19th, 21st program switches P4, P6, P1
Program processing of fuse elements, antifuse elements, and p-type or n-type field effect transistors constituting 1, P15, P19, and P21.

As a result, as shown in FIG. 60 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 3-input NAND circuit which logically amplifies 3 and outputs the output signal X from the second output line Lout2.

FIGS. 61 (a) and 61 (b) are four-input NA when programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of an ND circuit. In FIG. 61 (a), the 4-input NAND circuit includes second, fourth p-type power source program switches PD2, PD4, a first n-type power source program switch PS1, second, fourth, eighth, and fourth. A fuse element, an anti-fuse element, and a p-type or n-type field effect transistor forming the tenth, seventeenth and twenty-second program switches P2, P4, P8, P10, P17 and P22 are programmed.

As a result, as shown in FIG. 61 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 4-input NAND circuit that logically amplifies A3 and A4 and outputs the output signal X from the first output wiring Lout1.

62 (a) and 62 (b) are four-input NO in the case of programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 62 (a), 4 inputs N
The OR circuit is the first p-type power source program switch PD
1, 2nd and 4th n type power source program switch PS2,
Ps4, sixth, eleventh, thirteenth, fifteenth, nineteenth, and twenty-first program switches P6, P11, P13, P15, P19, P21, fuse elements, antifuse elements, p-type or n-type.
Type field effect transistor is programmed.

As a result, as shown in FIG. 62B, the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 4-input NAND circuit which logically amplifies A3 and A4 and outputs the output signal X from the second output wiring Lout2.

63 (a) and 63 (b) are 3-input ANs in the case of programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 63 (a), the 3-input AND / OR inverter circuit is
Second p-type power source program switches PD1, PD2, first, second and third n-type power source program switches PS1,
PS2, PS3, 4th, 7th, 9th, 11th, 15th, 21st program switches P4, P7, P9, P11, P15, P
The fuse element, the antifuse element, and the p-type or n-type field-effect transistor that form the element 21 are programmed.

As a result, as shown in FIG. 63 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are provided, and two input signals A1 and A2 are input first. It logically amplifies the result signal and the input signal B, and outputs the output signal X to the second output wiring Lou.
A 3-input AND / OR inverter circuit that outputs from t2 can be configured.

FIGS. 64 (a) and 64 (b) show a 4-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 64 (a), the 4-input AND / OR inverter circuit is
Third p-type power source program switch PD2, PD3, fourth
N-type power source program switch PS4, second, fourth, ninth, eleventh, thirteenth, seventeenth, and twenty-first program switches Ps
Program processing of the fuse element, antifuse element, and p-type or n-type field effect transistor constituting 2, P4, P9, P11, P13, P17, and P21.

As a result, as shown in FIG. 64 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
A three-input AND / OR inverter circuit for logically amplifying the resulting signal and the input signal B and outputting the output signal X from the second output line Lout2 is constructed. be able to.

FIGS. 65 (a) and 65 (b) show a 4-input AN when the basic cell according to the eleventh embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 65 (a), the 4-input AND / OR inverter circuit includes a second p-type power source program switch PD2, a first first n-type power source program switch PS1, PS1, a second, a fourth, and a fourth. 7, 9th, 11th, 15th, 21st program switches P
The fuse element, the antifuse element, and the p-type or n-type field-effect transistor which form 2, P4, P7, P9, P11, P15, and P21 are programmed.

As a result, as shown in FIG. 65 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are formed.
Is subjected to two-input logic amplification, and two-input logic amplification of the input signals A3 and A4 is performed, and both result signals are subjected to logic amplification.
The output signal X is output from the second output wiring Lout2 4
An input AND / OR inverter circuit can be constructed.

66 (a) and 66 (b) are four-input AN in the case of programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 66 (a), the 4-input AND / OR inverter circuit includes a fourth p-type power source program switch PD4, second and third n-type power source program switches PS2, PS3, first, fourth, and fourth. 8, 10th, 13th, 15th, 20th program switches P
Program processing of fuse elements, antifuse elements, and p-type or n-type field effect transistors constituting P1, P4, P8, P10, P13, P15, and P20.

As a result, as shown in FIG. 66 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are provided, and the input signals A1 and A2 are provided first.
Is logically amplified by two inputs, and the resulting signal and the input signal B1,
It is possible to configure a 4-input AND / OR inverter circuit that performs 3-input logical amplification with B2 and outputs the output signal X from the second output wiring Lout2.

67 (a) and 67 (b) are four-input ANs in the case of programming the basic cell according to the eleventh embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 67 (a), the 4-input AND / OR inverter circuit is
Third p-type power source program switch PD1, PD3, fourth
N type power source program switch PS4, third bypass program point PB3, fourth, ninth, eleventh, twelfth,
14th, 17th, 18th, 21st program switches P4
Program processing of fuse elements, antifuse elements, p-type or n-type field effect transistors constituting P9, P11, P12, P14, P17, P18 and P21 is performed.

As a result, as shown in FIG. 67 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are formed.
Is subjected to two-input logic amplification, the result signal and the input signal B are subjected to two-input logic amplification, the result signal and the input signal C are subjected to two-input logic amplification, and the output signal X is output to the second output It is possible to configure a 4-input AND / OR inverter circuit which outputs from the wiring Lout2.

(12) Description of the twelfth embodiment FIG. 68 is a block diagram of a basic cell according to the twelfth embodiment of the present invention, and FIGS. 69 to 77 show respective cases when the basic cell is programmed. The respective configuration diagrams of the basic logic cells are shown. The twelfth embodiment differs from the ninth embodiment in the fifth and sixth p-type power source program switches PD5 and PD6 and the fifth and sixth n-type ground program switches PS5 and PS6.
, And the first to fourth bypass program switches PB1 to PB4 are respectively connected.

That is, the twelfth basic cell 12 corresponds to the first to eighth transistors TP1 in the program symbol diagram of FIG.
~ TP4, TN1 to TN4 and 38 various program switches PD1 to PD6, PS1 to P for connecting between them and between wirings
It consists of S6, PB1 to PB4, and P1 to P22.

For example, the fifth p-type power source program switch PD5 is connected between the source or drain extraction electrode SD3 of the second transistor TP2 and the power source line VDD, and the sixth p-type power source program switch PD6. Is connected between the source or drain extraction electrode SD6 of the fourth transistor TP4 and the power supply line VDD.

The fifth n-type ground program switch PS5 is connected between the extraction electrode SD9 of the source or drain of the sixth transistor TN2 and the ground line GND, and the sixth
The n-type ground program switch PS6 is connected between the source or drain extraction electrode SD12 of the eighth transistor TN4 and the ground line GND. Further, the first bypass program switch PB1 is connected to the extraction electrodes SD1 and S of the source or drain of the first and second transistors TP1 and TP2.
The second bypass program switch PB2 is connected between D3 and the source or drain extraction electrodes SD4, SD6 of the third and fourth transistors TP3, TP4.

Further, the third bypass program switch PB3 is connected between the extraction electrodes SD7 and SD9 of the sources or drains of the fifth and sixth transistors TN1 and TN2,
The fourth bypass program switch PB4 is connected between the extraction electrodes SD10 and SD12 of the sources or drains of the seventh and eighth transistors TN3 and TN4. The rest of the configuration is the same as that of the ninth embodiment, so its explanation is omitted.

Thus, according to the basic cell of the twelfth embodiment of the present invention, as shown in FIG.
Transistors TP1 to TP4, TN1 to TN4, and 38 various program switches P for connecting between them and between wirings.
D1 to PD4, PS1 to PS4, P1 to P22 are provided, and the second
The fifth p-type power source program switch PD5 is connected between the source or drain extraction electrode SD3 of the transistor TP2 and the power source line VDD, and the fourth transistor T4.
Source or drain electrode P6 of P4 and power supply line VDD
And a sixth p-type power source program switch PD6 is connected between the fifth and n-type ground program switches, and a fifth n-type ground program switch between the source or drain extraction electrode SD9 of the sixth transistor TN2 and the ground line GND. PS5 is connected to the source or drain extraction electrode S of the eighth transistor TN4.
A sixth n-type ground program switch PS6 is connected between D12 and the ground line GND.

Also, the first and second transistors TP1, T
The first and second bypass program switches PB1 and PB2 are connected between the source or drain extraction electrodes SD1 and SD3 of P2 and the source or drain extraction electrodes SD4 and SD6 of the third and fourth transistors TP3 and TP4, respectively. The source or drain extraction electrodes SD7 and SD9 of the fifth and sixth transistors TN1 and TN2 and the source or drain extraction electrodes SD10 of the seventh and eighth transistors TN3 and TN4.
, SD12, third and fourth bypass program switches PB3, PB4 are connected, respectively.

Therefore, the eight transistors TP1 to TP
4, TN1 to TN4 and a total of 38 program switches PD
1 to PD6, PS1 to PS6, P1 to P22, PB1 to PB4 form a basic cell of the minimum unit. For example, in the 12th basic cell, the third p-type power source program switch PD
3, the second n-type ground program switch PS2 and the first,
Third, tenth, thirteenth, eighteenth program switches P1, P
3, P10, P13, P18, and 4 inputs by programming the fuse elements, antifuse elements, and p-type or n-type field effect transistors that form the first and fourth bypass program switches PB1 and PB4. AND O
It becomes possible to configure the R inverter circuit.

As a result, the number of program switches is increased by 8 as compared with the ninth embodiment, but a total of 38 program switches PD1 to PD4, PS1 to PS4, P1 to P22 are appropriately programmed. Therefore, as shown in FIGS. 69 to 77, eight transistors TP1 to TP4 and TN1 to TN4 are provided.
, 3-input NAND circuit, 3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit, 3-input AND / O
It is possible to configure a basic logic cell such as an R inverter circuit and a 4-input AND / OR inverter circuit.

Next, the program processing of the basic cell according to the twelfth embodiment of the present invention will be described. Fig. 69
(A), (b) is a block diagram of a 3 input NAND circuit at the time of programming the basic cell which concerns on the 12th Example of this invention. In FIG. 69 (a), the 3-input NAND circuit is
First to third and sixth p-type power source program switches PD1
To PD3, PD6, fuse elements forming the first and second n-type power source program switches PS1, PS2, the fourth, ninth, seventeenth and twenty-second program switches P4, P9, P17, P22, and anti Program the fuse element and the p-type or n-type field effect transistor.

As a result, as shown in FIG. 69 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 3-input NAND circuit which logically amplifies 3 and outputs the output signal X from the first output wiring Lout1.

70 (a) and 70 (b) are three-input NO when programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 70 (a), 3 inputs N
The OR circuit includes first, second p-type power source program switches PD1, PD2, first to third and sixth n-type power source program switches PS1 to PS3, PS6, fourth, sixth, eleventh, First
5, 20th program switches P4, P6, P11, P1
5. Program the fuse element, antifuse element, and p-type or n-type field effect transistor that form P20.

As a result, as shown in FIG. 70 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 3-input NAND circuit which logically amplifies 3 and outputs the output signal X from the second output line Lout2.

71 (a) and 71 (b) are four-input NA when programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of an ND circuit. In FIG. 71 (a), the 4-input NAND circuit includes the first, third, fifth and sixth p-type power source program switches PD1, PD3, PD5, PD6 and the first n-type.
Mold power source program switch PS1, 3rd, 9th, 17th,
The fuse element, the antifuse element, and the p-type or n-type field effect transistor forming the 22nd program switches P3, P9, P17, and P22 are programmed.

As a result, as shown in FIG. 71 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 4-input NAND circuit that logically amplifies A3 and A4 and outputs the output signal X from the first output wiring Lout1.

72 (a) and 72 (b) are four-input NO when programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of an R circuit. In FIG. 72 (a), 4 inputs N
The OR circuit is the first p-type power source program switch PD
1st, 1st, 3rd, 5th, 6th n-type power source program switches PS1, PS3, PS5, PS6, 6th, 11th, 14th, 14th
Fuse elements, antifuse elements, p-type or n-type elements constituting each of the 20 program switches P6, P11, P14, P20
Type field effect transistor is programmed.

As a result, as shown in FIG. 72B, the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
It is possible to configure a 4-input NAND circuit which logically amplifies A3 and A4 and outputs the output signal X from the second output wiring Lout2.

73 (a) and 73 (b) are 3-input ANs in the case of programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 73 (a), the 3-input AND / OR inverter circuit is
Second p-type power source program switch PD1, PD2, first
˜Fuses forming third n-type power source program switches PS1 to PS3, fourth, seventh, ninth, eleventh, fifteenth, and twenty-first program switches P4, P7, P11, P14, P15, P21 The element, antifuse element, p-type or n-type field effect transistor is programmed.

As a result, as shown in FIG. 73 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are provided, and the input signals A1 and A2 are input first. It logically amplifies the result signal and the input signal B, and outputs the output signal X to the second output wiring Lou.
A 3-input AND / OR inverter circuit that outputs from t2 can be configured.

FIGS. 74 (a) and 74 (b) are 4-input ANs in the case of programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 74 (a), the 4-input AND / OR inverter circuit is
Third and fifth p-type power source program switches PD1 and PD
3, PD5, fourth n-type power source program switch PS4,
Fuse element, anti-fuse element, p-type or n-type field effect forming the third, ninth, eleventh, thirteenth, seventeenth, and twenty-first program switches P3, P9, P11, P13, P17, P21 Program the transistor.

As a result, as shown in FIG. 74 (b), the input signals A1, A2, A are composed of the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4.
A three-input AND / OR inverter circuit for logically amplifying the resulting signal and the input signal B and outputting the output signal X from the second output line Lout2 is constructed. be able to.

FIGS. 75 (a) and 75 (b) are 4-input ANs when the basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 75 (a), the 4-input AND / OR inverter circuit is
Fifth p-type power source program switches PD1 and PD5, first and third n-type power source program switches PS1 and PS3,
Fuse element, anti-fuse element, p-type or n-type field effect constituting the third, seventh, ninth, eleventh, fifteenth, and twenty-first program switches P3, P7, P9, P11, P15, P21 Program the transistor.

As a result, as shown in FIG. 75 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are provided.
Is subjected to two-input logic amplification, and two-input logic amplification of the input signals A3 and A4 is performed, and both result signals are subjected to logic amplification.
The output signal X is output from the second output wiring Lout2 4
An input AND / OR inverter circuit can be constructed.

FIGS. 76 (a) and 76 (b) show a 4-input AN when the basic cell according to the twelfth embodiment of the present invention is programmed.
It is a block diagram of a D / OR inverter circuit. In FIG. 76 (a), the 4-input AND / OR inverter circuit is
Sixth n-type power source program switches PS3, PS6, first, fifth and sixth n-type power source program switches PS1,
Ps5, Ps6, first, fourth, ninth, fourteenth, twentieth program switches P1, P4, P9, P14, P20 fuse elements, antifuse elements, p-type or n-type field effect transistors Program processing of.

As a result, as shown in FIG. 76 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are formed.
Is logically amplified by two inputs, and the resulting signal and the input signal B1,
It is possible to configure a 4-input AND / OR inverter circuit that performs 3-input logical amplification with B2 and outputs the output signal X from the second output wiring Lout2.

77 (a) and 77 (b) are four-input ANs in the case of programming the basic cell according to the twelfth embodiment of the present invention.
It is a block diagram of a D / OR inverter circuit. In FIG. 77 (a), the 4-input AND / OR inverter circuit is
Fifth p-type power source program switch PD3, PD5, second
N type power source program switch PS2, fourth bypass program point PB4, first, third, tenth, thirteenth,
The 17th and 20th program switches P1, P3, P10,
Program processing of fuse elements, antifuse elements, and p-type or n-type field effect transistors constituting P13, P17, and P20.

As a result, as shown in FIG. 77 (b), the first to fourth transistors TP1 to TP4 and the fifth to eighth transistors TN1 to TN4 are formed.
Is subjected to two-input logic amplification, the result signal and the input signal B are subjected to two-input logic amplification, the result signal and the input signal C are subjected to two-input logic amplification, and the output signal X is output to the second output It is possible to configure a 4-input AND / OR inverter circuit which outputs from the wiring Lout2.

As described above, by connecting two or more basic cells according to the first to twelfth embodiments of the present invention or combining the basic logic cells to form various logic circuits, high performance, It is possible to provide an FPGA capable of programming a high-performance semiconductor integrated circuit.

Table 1 summarizes the number of program switches and the minimum unit (the number of BCs) of the basic cells according to the first to twelfth embodiments.

[0338]

[Table 1]

The minimum unit (the number of BCs) shows the case where four transistors are used as a reference, and the number of program switches is converted per the number of basic cells (BCs).

According to this, in the combination of the basic cells of the first embodiment, the number of program switches is 1 which is the smallest.
It can be eight. Also, 3 input AND / OR inverter circuit, 4 input AND / OR inverter circuit, 4
Input OR / AND inverter circuit, 6-input AND / OR
Although it is not possible to build an inverter circuit, it is possible to build other 16 types of basic logic cells.

In the combination of the basic cells of the second embodiment, the 4-input AND / OR inverter circuit and the 4-input O are used.
Although it is not possible to assemble an R / AND inverter circuit and a 6-input AND / OR inverter circuit, it is possible to assemble other 18 kinds of basic logic cells.

Furthermore, in the fifth to eighth embodiments, the first and second output wirings Lout1 and Lout2 can be used as through wirings, and in the ninth to twelfth embodiments, the minimum unit is two basic cells. It is possible to reduce the number of program switches to 15 with one set as a set.

[0343]

As described above, according to the first semiconductor integrated circuit device of the present invention, the first and second transistors which are p-type field effect transistors and the first and second transistors which are n-type field effect transistors. The third and fourth transistors are provided with a plurality of various program switches that connect between them and between the wirings.

Therefore, four transistors and a total of 18
A minimum unit basic cell is configured by the program switches. In addition, by programming a plurality of various program switches of the basic cell, an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input N circuit.
It is possible to configure a basic logic cell such as an OR circuit.

Further, according to the second semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, a third high / low potential side program switch is provided. .

Therefore, four transistors and a total of 20
A minimum unit basic cell is configured by the program switches. Also, by combining the basic cells, it becomes possible to form a 4-input AND / OR inverter circuit or the like.

Furthermore, according to the third semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and a plurality of various program switches for connecting between them and between wirings, And a second bypass program switch.

Therefore, four transistors and a total of 20
A minimum unit basic cell is configured by the program switches. Further, the number of program switches is increased by 2 as compared with the first semiconductor integrated circuit device, but 2 or 3 of the basic cells are connected and the first and second bypass program switches are used to increase It is possible to efficiently configure an input AND / OR inverter circuit, a 6-input AND / OR inverter circuit, and the like.

According to the fourth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the third high / low potential side program switch and the first and first program switches are also provided. And 2 bypass program switches.

Therefore, four transistors and a total of 22
A minimum unit basic cell is configured by the program switches. Further, the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, but as with the third semiconductor integrated circuit device, two or three of the basic cells are connected to each other and the third high-level switch is connected.・ Using the low potential side program switch and the first and second bypass program switches, 4
Input AND / OR inverter circuit and 6-input AND / OR
It is possible to efficiently configure the inverter circuit and the like.

Further, according to the fifth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the high potential side spare wiring and the first output wiring are connected. A fifteenth program switch and a sixteenth program switch for connecting the low potential side spare wiring and the second output wiring are provided.

Therefore, four transistors and a total of 20
A minimum unit basic cell is configured by the program switches. Further, although the number of program switches is increased by two as compared with the first semiconductor integrated circuit device, by performing the program processing of the fifteenth and sixteenth program switches, a through wiring function is provided for the first and second output wirings. It becomes possible to have. It is possible to configure basic logic cells such as an inverter circuit, an inverter (power type) circuit, a transmission gate circuit, a two-input NAND circuit, a two-input NOR circuit.

According to the sixth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches and the third high / low potentials are provided. And a side program switch.

Therefore, four transistors and a total of 22
A minimum unit basic cell is configured by the program switches. Further, the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, but like the fifth semiconductor integrated circuit device, the first and the first program switches are performed by the non-selection processing of the fifteenth and sixteenth program switches. The second output wiring can have a through wiring function.

Furthermore, according to the seventh semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches and the first and second bypass switches are provided. And a program switch for use.

Therefore, four transistors and a total of 22
A minimum unit basic cell is configured by the program switches. Although the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, like the fifth semiconductor integrated circuit device, the through wiring function is applied to the first and second bypass program programs. Various basic cells can be constructed by applying switches.

According to the eighth semiconductor integrated circuit device of the present invention, in addition to the first to fourth transistors and various program switches, the fifteenth and sixteenth program switches,
The third high / low potential side program switch and the first and second
A bypass program switch is provided.

Therefore, four transistors and a total of 24
A minimum unit basic cell is configured by the program switches. Further, the number of program switches is increased by four as compared with the first semiconductor integrated circuit device, but like the fifth semiconductor integrated circuit device, a program switch for high / low potential side and Various basic logic cells can be configured by applying the first and second bypass program switches.

Further, according to the ninth semiconductor integrated circuit device of the present invention, the first semiconductor integrated circuit device including the p-type field effect transistor is used.
˜Fifth to eighth transistors consisting of a fourth transistor and an n-type field effect transistor, and a plurality of various program switches for connecting between them and between wirings.

Therefore, eight transistors and a total of 30
A minimum unit basic cell is configured by the program switches. In addition, by appropriately programming a total of 30 program switches of the basic cell, a 3-input NAND circuit,
3-input NOR circuit, 4-input NAND circuit, 4-input NOR circuit
Circuit, 3-input AND / OR inverter circuit, 4-input AN
A basic logic cell such as a D / OR inverter circuit can be efficiently constructed.

According to the tenth semiconductor integrated circuit device of the present invention, in addition to the first to eighth transistors and various program switches, the fifth and sixth high / low potential side program switches are provided. Be equipped.

Therefore, 8 transistors and a total of 34
A minimum unit basic cell is configured by the program switches. Further, although the number of program switches is increased by four as compared with the ninth semiconductor integrated circuit device, various basic logic cells are configured by eight transistors by appropriately performing a program process for a total of 34 program switches. It becomes possible to do.

Further, according to the eleventh semiconductor integrated circuit device of the present invention, in addition to the first to eighth transistors and various program switches, first to fourth bypass program switches are provided.

Therefore, 8 transistors and a total of 34
A minimum unit basic cell is configured by the program switches. Although the number of program switches is increased by 4 as compared with the ninth semiconductor integrated circuit device, a total of 34 program switches are appropriately programmed to form a basic logic cell with 8 transistors. Is possible.

In addition to the first to eighth transistors and various program switches in the twelfth semiconductor integrated circuit device of the present invention, the fifth and sixth high / low potential side program switches and the first to fourth program switches are also provided. And a bypass program switch.

Therefore, eight transistors and a total of 38
A minimum unit basic cell is configured by the program switches. Further, although the number of program switches is increased by 8 as compared with the ninth semiconductor integrated circuit device, various basic logic cells are configured by 8 transistors by appropriately performing a program processing of 38 program switches in total. It becomes possible to do.

It should be noted that two or more basic cells composed of the first to eighth semiconductor integrated circuit devices of the present invention are connected, or various logic circuits are formed by combining the basic cells. Therefore, by combining the basic logic cells according to the first to eighth semiconductor integrated circuit devices, it becomes possible to configure a D-type flip-flop circuit with a smaller number of transistors than in the conventional example. It should be noted that, compared to a basic cell in which the minimum unit is two types, a transistor pair tile portion and a RAM logic tile portion, as in the conventional example, a D-type flip
The flop can be easily configured.

Further, two or more basic cells composed of the ninth to twelfth semiconductor integrated circuit devices of the present invention are connected, or various logic circuits are formed by combining the basic cells. Therefore, by combining the basic logic cells according to the ninth to twelfth semiconductor integrated circuit devices, it becomes possible to easily configure a multi-input AND / OR inverter circuit or the like.

This largely contributes to the provision of an FPGA capable of programming a high-performance and high-performance semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a principle diagram (2) of a semiconductor integrated circuit device according to the present invention.

FIG. 3 is a principle diagram (No. 3) of the semiconductor integrated circuit device according to the present invention.

FIG. 4 is a principle diagram (4) of a semiconductor integrated circuit device according to the present invention.

FIG. 5 is a principle diagram (5) of a semiconductor integrated circuit device according to the present invention.

FIG. 6 is a principle diagram (6) of a semiconductor integrated circuit device according to the present invention.

FIG. 7 is a principle diagram (No. 7) of the semiconductor integrated circuit device according to the present invention.

FIG. 8 is a principle view (No. 8) of the semiconductor integrated circuit device according to the present invention.

FIG. 9 is a principle diagram (9) of a semiconductor integrated circuit device according to the present invention.

FIG. 10 is a principle diagram (10) of the semiconductor integrated circuit device according to the present invention.

FIG. 11 is a principle diagram (11) of a semiconductor integrated circuit device according to the present invention.

FIG. 12 is a principle diagram (part 12) of the semiconductor integrated circuit device according to the present invention.

FIG. 13 is a configuration diagram of a chip plane of an FPGA according to each embodiment of the present invention.

FIG. 14 is an explanatory diagram of a basic cell according to each embodiment of the present invention.

FIG. 15 is a configuration diagram of a basic cell according to the first embodiment of the present invention.

FIG. 16 is a configuration diagram of a basic cell according to a second embodiment of the present invention.

FIG. 17 is a configuration diagram of a basic cell according to a third embodiment of the present invention.

FIG. 18 is a configuration diagram of an inverter circuit that programs a basic cell according to a third embodiment of the present invention.

FIG. 19 is a configuration diagram of an inverter (power type) circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 20 is a configuration diagram of a transmission gate circuit that programs a basic cell according to a third embodiment of the present invention.

FIG. 21 is a configuration diagram of a two-input NAND circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 22 is a configuration diagram of a 2-input NOR circuit in which a basic cell is programmed according to the third embodiment of the present invention.

FIG. 23 is a configuration diagram of a 3-input NAND circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 24 is a configuration diagram of a 3-input NOR circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 25 is a configuration diagram of a 4-input NAND circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 26 is a configuration diagram of a 4-input NOR circuit in which a basic cell is programmed according to a third embodiment of the present invention.

FIG. 27 is a configuration diagram of a 3-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 28 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 29 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 30 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 31 is a configuration diagram of a 6-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 32 is a supplementary diagram of a 6-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 33 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a third embodiment of the present invention is programmed.

FIG. 34 is a configuration diagram of a basic cell according to a fourth embodiment of the present invention.

FIG. 35 is a configuration diagram of an inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 36 is a configuration diagram of an inverter (power type) circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 37 is a configuration diagram of a transmission gate circuit that programs a basic cell according to a fourth embodiment of the present invention.

FIG. 38 is a configuration diagram of a 2-input NAND circuit in which a basic cell according to the fourth embodiment of the present invention is programmed.

FIG. 39 is a configuration diagram of a 2-input NOR circuit in which a basic cell is programmed according to the fourth embodiment of the present invention.

FIG. 40 is a configuration diagram of a 3-input NAND circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 41 is a configuration diagram of a 3-input NOR circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 42 is a configuration diagram of a 4-input NAND circuit in which a basic cell is programmed according to the fourth embodiment of the present invention.

FIG. 43 is a configuration diagram of a 4-input NOR circuit in which a basic cell is programmed according to a fourth embodiment of the present invention.

FIG. 44 is a configuration diagram of a 3-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 45 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 46 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to the fourth embodiment of the present invention is programmed.

FIG. 47 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 48 is a configuration diagram of a 6-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 49 is a supplementary diagram of a 6-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 50 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a fourth embodiment of the present invention is programmed.

FIG. 51 is a circuit configuration diagram (part 1) programmable by the basic cell according to the fourth embodiment of the present invention.

FIG. 52 is a circuit configuration diagram (part 2) programmable by the basic cell according to the fourth example of the present invention.

FIG. 53 is an explanatory diagram of a D-type flip-flop circuit in which basic cells according to a fourth example of the present invention are combined.

FIG. 54 is a configuration diagram of a basic cell according to fifth and sixth embodiments of the present invention.

[Fig. 55] Fig. 55 is a configuration diagram of a basic cell according to a seventh embodiment of the present invention.

[Fig. 56] Fig. 56 is a configuration diagram of a basic cell according to a ninth embodiment of the present invention.

[Fig. 57] Fig. 57 is a configuration diagram of a basic cell according to a tenth embodiment of the present invention.

FIG. 58 is a configuration diagram of a basic cell according to an eleventh embodiment of the present invention.

FIG. 59 is a configuration diagram of a 3-input NAND circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 60 is a configuration diagram of a 3-input NOR circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 61 is a configuration diagram of a 4-input NAND circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 62 is a configuration diagram of a 4-input NOR circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 63 is a configuration diagram of a 3-input AND / OR inverter circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 64 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 65 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 66 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell is programmed according to an eleventh embodiment of the present invention.

FIG. 67 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to an eleventh embodiment of the present invention is programmed.

FIG. 68 is a configuration diagram of a basic cell according to a twelfth embodiment of the present invention.

FIG. 69 is a configuration diagram of a 3-input NAND circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 70 is a configuration diagram of a 3-input NOR circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 71 is a configuration diagram of a 4-input NAND circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 72 is a configuration diagram of a 4-input NOR circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 73 is a configuration diagram of a 3-input AND / OR inverter circuit in which a basic cell is programmed according to a twelfth embodiment of the present invention.

FIG. 74 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 75 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 76 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 77 is a configuration diagram of a 4-input AND / OR inverter circuit in which a basic cell according to a twelfth embodiment of the present invention is programmed.

FIG. 78 is a configuration diagram of a logic circuit included in a basic cell of an FPGA according to a conventional example.

[Explanation of symbols]

T1 to T4 ... First to fourth transistors, T5 to T8 ... Fifth to eighth transistors, P1 to P22 ... First to 22nd program points, SD1 to SD12 ... Source or drain extraction electrode, PD1 to PD6 ... First to sixth high potential side program switches, PS1 to PS6 ... First to sixth low potential side program switches, PB1 to PB4 ... First to fourth bypass program switches Lout1, Lout2 ... first and second output wirings, LP1, LP2 ... first and second high-potential side preliminary wirings, LN1, LN2 ... first and second low-potential side preliminary wirings, Lin ... input wiring, VDD , VSS ... First and second power supply lines.

Claims (25)

[Claims] 1. First to fourth transistors (T1 to T)
4) and the first to fourth transistors (T1 to T4)
And a plurality of various program switches (PD1, PD2, PS1, PS2, P1 to P14) for connecting the lines and wirings, and each gate (G) of the first to fourth transistors (T1 to T4) The extraction electrodes (SD1 to SD6) of the sources or drains of the first to fourth transistors (T1 to T4) connected to the input wiring (Lin) are connected to the first and second high potential side program switches (PD1, PD2), the first and second low potential side program switches (PS1, PS2) and the first to fourteenth
For the first and second power supply lines (VDD, VSS), the first and second output lines (Lout1, Lout2), and the first and second high potential sides with the program switches (P1 to P14) interposed. A semiconductor integrated circuit device characterized by being connected to spare wirings (LP1, LP2) or first and second spare wirings for low potential side (LN1, LN2). 2. The semiconductor integrated circuit device according to claim 1, wherein the source or drain extraction electrode (SD1) of the first transistor (T1) interposes a first high potential side program switch (PD1). Let the first power line (V
DD), the second output wiring (Lout2) with the first program switch (P1) interposed, and the first output wiring (Lout1) with the second program switch (P2) interposed.
And a first high-potential-side spare line (LP1), and the source or drain extraction electrodes (SD2) of the first and second transistors (T1, T2) are connected to the second high-potential side. Is connected to the first power supply line (VDD) through the program switch (PD2) and the first output line (Lout1) through the third program switch (P3), and the second transistor The source or drain extraction electrode (SD3) of (T2) has a fourth program switch (P4) interposed therebetween and a first output wiring (Lout1) and a fifth program switch (P5) interposed therethrough. 2 output wiring (Lout2) and the sixth program switch (P
6) is connected to the first spare line for high potential side (LP1), and the extraction electrode (SD4) of the source or drain of the third transistor (T3) is for the first low potential side. Second power supply line (VSS) with a program switch (PS1) interposed
A first output wiring (Lout1) with an eighth program switch (P8) interposed, and a second output wiring (Lout2) with a ninth program switch (P9) interposed. The lead-out electrode (SD5) of the source or drain of the third and fourth transistors (T3, T4) is connected to the potential side spare wiring (LN1), and the second low potential side program switch (PS2) Is connected to the second power supply line (VSS) and the tenth program switch (P10) via the second output wiring (Lout2), and the source of the fourth transistor (T4) or The drain extraction electrode (SD6) is connected to the second output wiring (Lout2) through the eleventh program switch (P11),
The 12th program switch (P12) is interposed and the 1st output wiring (Lout1) and the 13th program switch (P1)
3) is connected to the first low potential side spare wiring (LN1), and the first output wiring (Lout1) is connected to the second low potential side through the seventh program switch (P7). The second output wiring (Lout2) is connected to the side auxiliary wiring (LP2), and is connected to the second low-potential side auxiliary wiring (LN2) through the fourteenth program switch (P14). A semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a third high potential side program switch (PD3). Is connected to the first power supply line (VDD), and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes a third low potential side program switch (PS3). A semiconductor integrated circuit device characterized by being connected to a second power supply line (VSS). 4. The semiconductor integrated circuit device according to claim 1, wherein the first and second transistors (T1, T2) are provided.
2) Source or drain extraction electrodes (SD1, SD3)
A first bypass program switch (PB1) is connected between the third and fourth transistors (T3, T4).
A semiconductor integrated circuit device, wherein a second bypass program switch (PB2) is connected between the source or drain extraction electrodes (SD4, SD6). 5. The semiconductor integrated circuit device according to claim 1, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a third high potential side program switch (PD3). Is connected to the first power supply line (VDD), and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes a third low potential side program switch (PS3). Connected to the second power supply line (Vss), and the first bypass program switch (S1) between the source or drain extraction electrodes (SD1, SD3) of the first and second transistors (T1, T2). PB1) is connected, and the second bypass program switch (PB2) is connected between the source or drain extraction electrodes (SD4, SD6) of the third and fourth transistors (T3, T4). The semiconductor integrated circuit device, characterized in that. 6. The semiconductor integrated circuit device according to claim 1, wherein the first and second transistors (T1, T2) are provided.
2) A p-type field effect transistor, and the third and fourth transistors (T3, T4) are n-type field effect transistors. 7. The semiconductor integrated circuit device according to claim 1, wherein the various program switches (PD1 to PD3,
A semiconductor integrated circuit device, wherein PS1 to PS3, P1 to P14, PB1 and PB2) are composed of a fuse element, an antifuse element and a p-type or n-type field effect transistor. 8. First to fourth transistors (T1 to T)
4) and the first to fourth transistors (T1 to T4)
And a plurality of various program switches (PD1, PD2, PS1, PS2, P1 to P16) for connecting the lines and wirings, and the gates (G) of the first to fourth transistors (T1 to T4) are input. Connected to a wiring (Lin), the first to fourth
Source / drain extraction electrodes (SD1 to SD6) of the transistors (T1 to T4) are first and second high potential side program switches (PD1 and PD2), and first and second low potential side program switches. (PS1, PS2) and first to sixteenth program switches (P1 to P16) are interposed to
Second power supply lines (VDD, VSS), first and second output wirings (Lout1, Lout2), first and second high potential side spare wirings (LP1, LP2) or first and second low wirings. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is connected to spare wirings (LN1, LN2) for the potential side. 9. The semiconductor integrated circuit device according to claim 8, wherein the source or drain extraction electrode (SD1) of the first transistor (T1) interposes a first high potential side program switch (PD1). Let the first power line (V
DD), the second high potential side spare wiring (LP2) with the first program switch (P1) interposed, and the second high potential side spare wiring with the second program switch (P2) interposed. Wiring (LP2) and first high-potential side spare wiring (LP1)
And a source or drain extraction electrode (SD2) of the first and second transistors (T1, T2) connected to a first power supply via a second high potential side program switch (PD2). The line (VDD) and the second high voltage side spare line (LP2) through the third program switch (P3), and the source or drain extraction electrode of the second transistor (T2). (SD3) is connected to the second high potential side spare wiring (LP) through the fourth program switch (P4).
2), the second low potential side spare wiring (LN2) with the fifth program switch (P5) interposed, and the first high potential side spare wiring with the sixth program switch (P6) interposed. A second power supply line connected to the wiring (LP1), and the source or drain extraction electrode (SD4) of the third transistor (T3) with the first low potential side program switch (PS1) interposed. (VSS)
A second high-potential side spare wiring (LP2) with an eighth program switch (P8) interposed, and a second low-potential side spare wiring (LP9) with a ninth program switch (P9) interposed. LN2) and the first low potential side spare wiring (LN1), and the extraction electrodes (SD5) of the source or drain of the third and fourth transistors (T3, T4) are connected to the second low potential side. It is connected to the second power supply line (VSS) via the potential side program switch (PS2) and to the second high potential side spare wiring (LP2) via the tenth program switch (P10). , The source or drain extraction electrode (SD6) of the fourth transistor (T4) is provided with a second low-potential side spare line (LN) with an eleventh program switch (P11) interposed.
2), the second high potential side spare wiring (LP2) with the twelfth program switch (P12) interposed, and the first low potential side spare wiring with the thirteenth program switch (P13) interposed. To the wiring (LN1), the second high potential side spare wiring (LP2) is connected to a seventh program switch (P7), and the second low potential side spare wiring (LN2) is connected to 14 program switches (P1
4), and the second spare wiring for high potential side (LP2) is connected to the first output wiring (L) through the fifteenth program switch (P15).
out1) and is connected to the second low-potential side spare wiring (L
N2) is connected to the second output wiring (Lout2) through the 16th program switch (P16). 10. The semiconductor integrated circuit device according to claim 8, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a third high potential side program switch (PD3). Is connected to the first power supply line (VDD), and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes a third low potential side program switch (PS3). A semiconductor integrated circuit device characterized by being connected to a second power supply line (VSS). 11. The semiconductor integrated circuit device according to claim 8, wherein the first and second transistors (T1, T2) are provided.
2) Source or drain extraction electrodes (SD1, SD3)
A first bypass program switch (PB1) is connected between the two, and the third and fourth transistors (T3, T
4) Source or drain extraction electrodes (SD1, SD3)
A semiconductor integrated circuit device, wherein a second bypass program switch (PB2) is connected between the two. 12. The semiconductor integrated circuit device according to claim 8, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a third high potential side program switch (PD3). Is connected to the first power supply line (VDD), and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes a third low potential side program switch (PS3). And the first bypass program between the lead-out electrodes (SD1, SD3) of the source or drain of the first and second transistors (T1, T2) connected to the second power supply line (VSS). The switch (PB1) is connected, and the second bypass program switch (PB2) is connected between the extraction electrodes (SD4, SD6) of the sources or drains of the third and fourth transistors (T3, T4). The semiconductor integrated circuit device characterized in that it is. 13. The semiconductor integrated circuit device according to claim 8, wherein the first and second transistors (T1, T1) are provided.
2) A p-type field effect transistor, and the third and fourth transistors (T3, T4) are n-type field effect transistors. 14. The semiconductor integrated circuit device according to claim 8, wherein the various program switches (PD1 to PD3,
A semiconductor integrated circuit device, wherein PS1 to PS3, P1 to P16, PB1 and PB2) are composed of a fuse element, an antifuse element, and a p-type or n-type field effect transistor. 15. First to eighth transistors (T1 to T)
8) and the first to eighth transistors (T1 to T8)
And a plurality of various program switches (PD1 to PD4, PS1 to PS4, P1 to P22) for connecting the wirings and wirings, and each gate (G) of the first to eighth transistors (T1 to T8) The extraction electrodes (SD1 to SD12) of the sources or drains of the first to eighth transistors (T1 to T8) connected to the input wiring (Lin) have the first to fourth high potential side program switches (PD1 to). PD4), the first to fourth low potential side program switches (PS1 to PS4) and the first to first
Semiconductors characterized by being connected to first and second power supply lines (VDD, VSS) and first and second output lines (Lout1, Lout2) through 22 program switches (P1 to P22) Integrated circuit device. 16. The semiconductor integrated circuit device according to claim 15, wherein the source or drain extraction electrode (SD1) of the first transistor (T1) interposes a first high potential side program switch (PD1). Let the first power line (V
DD), the second output wiring (Lout2) through the first program switch (P1), and the first output wiring (Lout1) through the second program switch (P2). , The source or drain extraction electrodes (SD2) of the first and second transistors (T1, T2) are provided with a first power source line (VDD) through a second high potential side program switch (PD2). Is connected to the first output line (Lout1) through the third program switch (P3), and the source or drain extraction electrode (SD3) of the second transistor (T2) is connected to the fourth The first output wiring (Lout1) with the program switch (P4) interposed, the second output wiring (Lout2) with the fifth program switch (P5) interposed, and the sixth program switch (Pout).
6) is connected to the source / drain lead-out electrode (SD4) of the third transistor (T3), and the source or drain lead-out electrode (SD4) of the third transistor (T3) is First power supply line (VDD) with a high potential side program switch (PD3) interposed
And a second output wiring (Lout2) through a seventh program switch (P7) and a first output wiring (Lout1) through an eighth program switch (P8). The source or drain extraction electrodes (SD5) of the third and fourth transistors (T3, T4) and the first power supply line (VDD) with the fourth high potential side program switch (PD4) interposed. The ninth program switch (P9) is interposed and connected to the first output line (Lout1), and the source or drain extraction electrode (SD6) of the fourth transistor (T4) is connected to the tenth program switch (Pout). The first output wiring (Lout1) and the first output wiring (Lout1)
11 program switch (P11) is interposed and it is connected to the second output wiring (Lout2), and the source or drain extraction electrode (SD7) of the fifth transistor (T5) is connected to the first low potential side. Second power supply line (VSS) through the program switch (PS1) for
And a first output wiring (Lout1) through a thirteenth program switch (P12) and a second output wiring (Lout2) through a fourteenth program switch (P13). Source or drain extraction electrodes (SD8) of the fifth and sixth transistors (T5, T6) and a second power supply line (VSS) with a second low potential side program switch (PS2) interposed. It is connected to the second output wiring (Lout2) through a fourteenth program switch (P14), and the source or drain extraction electrode (SD9) of the sixth transistor (T6) is a fifteenth program switch. (P15) is interposed and the second output wiring (Lout2)
The 16th program switch (P16) is interposed, and the 1st output wiring (Lout1) and the 17th program switch (P1)
7) is connected to the source / drain lead-out electrode (SD10) of the seventh transistor (T3), and the source or drain lead-out electrode (SD10) of the seventh transistor (T7) is Second power supply line (VSS) with a low potential side program switch (PS3) interposed
A first output wiring (Lout1) through an eighteenth program switch (P18) and a second output wiring (Lout2) through a nineteenth program switch (P19), The source or drain extraction electrodes (SD11) of the seventh and eighth transistors (T7, T8) and the second power supply line (VSS) with the fourth low potential side program switch (PS4) interposed. It is connected to the second output wiring (Lout2) through the twentieth program switch (P20), and the source or drain extraction electrode (SD12) of the eighth transistor (T8) is the twenty-first program switch. (P21) is interposed and the second output wiring (Lout2)
A semiconductor integrated circuit device, characterized in that it is connected to the first output wiring (Lout1) through 22 program switches (P22). 17. The semiconductor integrated circuit device according to claim 15, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a fifth high potential side program switch (PD5). Is connected to the first power supply line (VDD) via the intervening line, and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes the sixth high potential side program switch (PD6). Connected to the first power supply line (VDD), and the source or drain extraction electrode (SD9) of the sixth transistor (T6) has a fifth low potential side program switch (PS5) interposed. The extraction electrode (SD12) of the source or drain of the eighth transistor (T8) is connected to the second power supply line (Vss) and the second low potential side program switch (PS6) is interposed between of Source line (VSS)
A semiconductor integrated circuit device characterized by being connected to a. 18. The semiconductor integrated circuit device according to claim 15, wherein the first and second transistors (T1, T) are provided.
2) Source or drain extraction electrodes (SD1, SD3)
And the first and second bypass program switches (PB1, PB2) are connected between the source or drain extraction electrodes (SD4, SD6) of the third and fourth transistors (T3, T4), respectively. , The sixth transistor (T
5, T6) source or drain extraction electrode (SD7,
SD9) and the third or fourth bypass program switch (PB3, P) between the source or drain extraction electrodes (SD10, SD12) of the seventh and eighth transistors (T7, T8).
B4) are respectively connected to the semiconductor integrated circuit device. 19. The semiconductor integrated circuit device according to claim 15, wherein the source or drain extraction electrode (SD3) of the second transistor (T2) is a fifth high potential side program switch (PD5). Is connected to the first power supply line (VDD) via the intervening line, and the source or drain extraction electrode (SD6) of the fourth transistor (T4) interposes the sixth high potential side program switch (PD6). Connected to the first power supply line (VDD), and the source or drain extraction electrode (SD9) of the sixth transistor (T6) has a fifth low potential side program switch (PS5) interposed. The extraction electrode (SD12) of the source or drain of the eighth transistor (T8) is connected to the second power supply line (Vss) and the second low potential side program switch (PS6) is interposed between of Source line (VSS)
Connected to the first and second transistors (T1, T
2) Source or drain extraction electrodes (SD1, SD3)
And the first and second bypass program switches (PB1, PB2) are connected between the source or drain extraction electrodes (SD4, SD6) of the third and fourth transistors (T3, T4), respectively. , The sixth transistor (T
5, T6) source or drain extraction electrode (SD7,
SD9) and the third or fourth bypass program switch (PB3, P) between the source or drain extraction electrodes (SD10, SD12) of the seventh and eighth transistors (T7, T8).
B4) are respectively connected to the semiconductor integrated circuit device. 20. The semiconductor integrated circuit device according to claim 15, wherein the first to fourth transistors (T1 to T) are provided.
4) is a p-type field effect transistor,
~ A semiconductor integrated circuit device, wherein the eighth transistor (T5 to T8) is an n-type field effect transistor. 21. The semiconductor integrated circuit device according to claim 15, wherein the various program switches (PD1 to PD6,
PS1 to PS6, P1 to P22, PB1 to PB4) are fuse elements, antifuse elements, and p-type or n-type field effect transistors. 22. A semiconductor integrated circuit device, comprising: connecting two or more basic cells comprising the semiconductor integrated circuit device according to claim 1; or combining the basic cells to form various logic circuits. 23. A semiconductor integrated circuit device, comprising: connecting two or more basic cells comprising the semiconductor integrated circuit device according to claim 8 or combining the basic cells to form various logic circuits. 24. A semiconductor integrated circuit device, comprising: connecting two or more basic cells comprising the semiconductor integrated circuit device according to any one of claims 15 to 21 or combining the basic cells to form various logic circuits. 25. A semiconductor integrated circuit comprising: connecting two or more basic cells comprising the semiconductor integrated circuit device according to claim 22, 23, or 24, or combining the basic cells to form various logic circuits. apparatus.