JPH06111580A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce an occupancy area and a driving load and to make an opareation at a high speed by controlling the load circuit of a differencial amplifying circuit for responding to respective bit line pairs and having an output signal line pair and a load circuit as common units with a circuit arranged for controlling the switching of the operations for a write-in and a read-out. CONSTITUTION:Bit lines (BL)1 to (n) arranged at every column of a memory array 6 are connected to transfer gate circuits (DTR) 1 to (n) via the differencial amplifying circuits (BLSA) 1 to (n). The output signal line pir (RB) 1 and the load circuit (LD) 1 are common units for each BLSA, each DTR transmits a write-in data to BL. Then, the switching of the operation of write-in/read-out is performed by a control circuit WR and also decode circuits for BL selection (BLD) 1 to (n) are controlled by the same WR via a decode circuit BD and the differencial amplifying circuit BSA. Selective signals SS 1 to (n) are generated in each BLD and BLSA and DTR are selected and then LD1 is controlled by each BLD. Thus, the ooccupancy area and the driving load are reduced, and the operation of the circuit is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit for a semiconductor memory device. The present invention relates to a semiconductor memory device capable of reducing the occupied area of a decode circuit for selecting a bit line pair and accelerating the circuit operation.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIGS. FIG. 1 is a block diagram showing the overall configuration of a general semiconductor memory device. A conventional semiconductor memory device includes a chip enable control circuit 1, a switching control circuit 2 for controlling switching between write and read operations, an input / output circuit 3 for inputting / outputting data, a column decoder 4, and a data input / output. I / O control circuit 5 for controlling the
And Rhoda Da 7. FIG. 4 shows a structure of an input / output circuit connected to a bit line pair of a conventional semiconductor memory device and a decoding circuit for selecting them. In the figure, BL1, BL2, BLn are bit line pairs, BLSA
1, BLSA2, BLSAn are bit line pairs BL1, BL
2, a differential amplifier circuit provided in common for each BLn and sharing a load circuit with the output signal line pair, LD1 is a load circuit common to the differential amplifier circuits BLSA1, BLSA2, BLSAn, and RB1 is a differential amplifier circuit. Circuit BLSA1, BL
Output signal line pair common to SA2 and BLSAn, SR1 and S
R2 and SRn are differential amplifier circuits BLSA1 and BLSA, respectively.
SA2, BLSAn selection signal lines, DTR1, DTR
2, DTRn are provided corresponding to the bit line pairs BL1, BL2, BLn respectively, and transfer gate circuits for transmitting write data to the corresponding bit line pairs BL1, BL2, BLn, WB1 are write data line pairs,
LD2 is a load circuit that precharges the power supply voltage when the write data line pair WB1 is not selected, SW1, SW2, S
Wn are transgate circuits DTR1 and DTR, respectively.
2, DTRn selection signal lines, BLD1, BLD2, BL
Dn is a bit line pair selection decoding circuit provided corresponding to each of the bit line pairs BL1, BL2, BLn,
GWB is a global write data line pair, BTR is a transfer gate circuit connecting the write data line pair WB1 and GWB, BSA is a differential amplifier circuit, SBW is a bit line pair selection decoding circuit BLD1, BLD2, BLD.
n and the selection signal line of the transfer gate circuit BTR,
SBR is a selection signal line of the differential amplifier circuit BSA, WES is an output signal line of a circuit that controls switching of writing and reading operations of the semiconductor memory device, and BD is divided into a plurality of parts including all the circuits described above in the semiconductor memory device. And a decoding circuit for selecting a selected memory cell block.

Next, the operation of the conventional example device thus configured will be described.

A decode circuit BD for selecting a memory cell block receives a decode signal of an address signal input to a semiconductor memory device and a decode circuit BL for selecting a bit line pair.
From the output signal line WES of the circuit which generates the selection signal on the selection signal line SBW of D1, BLD2, BLDn and the transfer gate circuit BTR, and which controls the decoding signal of the address signal and the switching of the writing and reading operations of the semiconductor memory device. The logic of the signal is taken to generate a selection signal on the selection signal line SBR. In addition, bit line pair selection decoding circuits BLD1 and BLD provided corresponding to the bit line pairs BL1, BL2, and BLn, respectively.
2, BLDn receive the decode signal of the address signal input to the semiconductor memory device and the selection signal SBW, and are provided corresponding to each of the bit line pairs BL1, BL2, BLn, respectively, and transfer gate circuits DTR1, for transmitting write data, Selection signal line SW to DTR2 and DTRn
1, SW2, and SWn generate selection signals, and output signals from decode signals of address signals, selection signals from the selection signal line SBW, output signal lines WES of circuits that control switching of writing and reading operations of the semiconductor memory device. Taking the logic of the signal, the bit line pair BL1, BL2, B
Differential amplifier circuits BLSA1 and BLSA provided corresponding to each Ln and sharing the output signal line pair and the load circuit
Selection signal lines SR1, SR2, S to SA2, BLSAn
A selection signal is generated in Rn.

Here, when the semiconductor memory device including the circuit shown in FIG. 4 is in the write operation state, the decoding circuit BD causes the memory cell block and the bit line pair BL included in the memory cell block.
When the bit line pair BL1 which is one of 1, BL2 and BLn is selected, the selection signal lines SBW and SW1 are set to “High”.
It becomes the "h" potential and the transfer gate circuits BTR and D
TR1 becomes "ON" and write data line pair GW
B, write data line pair WB1, and bit line pair BL
1 is electrically connected, and the write data input to the semiconductor memory device is transmitted to the write data line pair WB1 through the write data line pair GWB, which is the bit line pair B.
It is transmitted to L1. Further, since the semiconductor memory device is in the writing state, the output signal line WES becomes the “High” potential, the selection signal lines SBR and SR1 become the “Low” potential, and the differential amplifier circuits BLSA1 and BSA are not selected, and the power consumption is reduced. .

[0006]

The input / output circuits connected to the bit line pairs of the conventional semiconductor memory device and the decode circuit for selecting them are provided corresponding to each bit line pair. A signal line for selecting a differential amplifier circuit having a common output signal line pair and a load circuit and a transfer gate circuit provided corresponding to each bit line pair and transmitting write data to the corresponding bit line pair is shown. 4, SR1, SR2, SRn and SW
1, SW2, and SWn are separated, and the power consumption is reduced by deselecting the differential amplifier circuit during the write operation. Therefore, the bit line pair selection corresponding to each bit line pair is selected. Decoder circuits BLD1 and B
LD2 and BLDn have select signal lines SW1 and S
A decode circuit for generating a selection signal on W2 and SWn,
It is necessary to have two circuits of a decoding circuit for generating a selection signal on the selection signal lines SR1, SR2, SRn. Therefore, the occupied area in the semiconductor memory device of the bit line pair selection decoding circuit provided corresponding to each bit line pair increases, and the drive load of the output signal line of the circuit controlling the switching between the write and read operations is increased. There was a growing problem. The present invention solves such a problem, and provides a device which can reduce the occupied area of a decoding circuit for selecting a bit line pair, reduce the driving load of an output signal line, and speed up the circuit operation. The purpose is to do.

[0007]

DISCLOSURE OF THE INVENTION The present invention provides a cell array including a plurality of memory cells arranged in a matrix of m rows and n columns, and correspondingly provided for each column of the memory cells. A pair of bit lines respectively connected to the memory cells of the columns, a differential amplifier circuit provided corresponding to each pair of the bit lines and having a common output signal line pair and a load circuit, and each of the pair of bit lines. In a semiconductor memory device including a transfer gate circuit provided corresponding to each of the bit lines for transmitting write data to the corresponding bit line pair, and a control circuit for controlling switching of write and read operations, the load circuit is controlled by the control circuit. A circuit controlling means and a means for generating a common selection signal for selecting the differential amplifier circuit and the transfer gate circuit. It is characterized in.

[0008]

Operation: An output signal of a circuit which is provided corresponding to each bit line pair and which controls switching of read and write operations of a common load circuit of a differential amplifier circuit in which the output signal line pair and the load circuit are common Control is performed by a line and a signal which is a logic of the decode signal of the address signal input to the semiconductor memory device.

As a result, the occupied area of the bit line pair selection decoding circuit provided corresponding to each bit line pair can be reduced, and the output signal line of the circuit for controlling the switching between the write and read operations can be reduced. The driving load can be reduced to speed up the circuit operation.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment and a conventional example of the present invention.

In the embodiment of the present invention, a chip enable control circuit 1, a switching control circuit 2 for controlling switching between writing and reading operations, an input / output circuit 3 for inputting / outputting data, a column decoder 4, and a data decoder. An input / output control circuit 5 for controlling input / output, a cell array 6, and a row decoder 7 are included in the overall configuration.

(First Embodiment) FIG. 2 is a diagram showing the configurations of an input / output circuit and a decoding circuit in the first embodiment of the present invention.

The first embodiment of the present invention is provided with a cell array 6 including a plurality of memory cells arranged in a matrix of m rows and n columns, and provided corresponding to each column of the memory cells. The bit line pairs BL1 to BLn connected to the memory cells in the column and the bit line pairs BL1 to BL1
Bit line pairs BL1 to BLn, and differential amplifier circuits BLSA1 to BLSAn provided corresponding to each BLn and sharing the output signal line pair RB1 and the load circuit LD1.
Transfer gate circuits DTR1 to DTRn for transmitting write data to the corresponding bit line pairs BL1 to BLn, and a control circuit WR for controlling switching between write and read operations. A feature of the present invention is that a decoding circuit BD, a differential amplifier circuit BSA, and a differential amplifier circuit BLSA1 that constitute a means for controlling the load circuit LD1 by the control circuit WR.
~ BLSAn and transfer gate circuit DTR1 ~
Bit line pair selection decoding circuits BLD1 to BLD for generating common selection signals SS1 to SSn for selecting DTRn
n and.

In the figure, BL1, BL2, BLn are provided corresponding to each bit line pair, and BLSA1, BLSA2, BLSAn are provided corresponding to each bit line pair BL1, BL2, BLn, and the output signal line pair and the load circuit are made common. This is a differential amplifier circuit, and LD1 is the differential amplifier circuit BLSA1, BL
A load circuit common to SA2 and BLSAn is composed of a P-channel type insulated gate field effect transistor. Also, R
B1 is a differential amplifier circuit BLSA1, BLSA2, BLSA
n common output signal line pair, DTR1, DTR2, DTR
n is provided corresponding to each bit line pair BL1, BL2, BLn, and the corresponding bit line pair BL1, BL
2, a transfer gate circuit for transmitting a write decoder to BLn, WB1 is a write decoder line pair, L
D2 is a load circuit for precharging to the power supply voltage when the write data line pair WB1 is not selected, SS1, S
S2 and SSn are the differential amplifier circuits BLSA1 and BLSA1, respectively.
BLSA2, BLSAn and select signal lines for transfer gate circuits DTR1, DTR2, DTRn, BLD
1, BLD2, BLDn are bit line pairs BL1, BL2,
A bit line pair selection decoding circuit provided corresponding to each BLn, GWB is a global write data line pair, BTR is a write data line pair WB1 and GW.
BSA is a transfer gate circuit, BSA is a differential amplifier circuit, SBW is a bit line pair selection decoding circuit BLD1, BLD2, BLDn and a selection signal line of the transfer gate circuit BTR, and SBR is a differential amplifier circuit BS.
A selection signal line of A, WES is a write / read switching signal line of a circuit that controls switching of writing and reading operations of the semiconductor memory device from the control circuit WR, and BD is a plurality including all circuits described above in the semiconductor memory device. A decode circuit for selecting the divided memory cell blocks, and WR is a control circuit.

Next, the operation of the first embodiment of the present invention thus constructed will be described.

The decode circuit BD for selecting the memory cell block receives the decode signal of the address signal input to the semiconductor memory device and selects the bit line pair select decode circuits BLD1, BLD2, BLDn and the select signal of the transfer gate circuit BTR. The selection signal to the line SBW is generated, and the logic of the decode signal of the address signal and the output signal from the output signal line WES of the circuit for controlling the switching of the writing and reading operations of the semiconductor memory device is taken to the selection signal line SBR. Generate a selection signal of.

The bit line pair selection decode circuits BLD1, BLD2, BLDn provided corresponding to each bit line pair BL1, BL2, BLn are the decode signal of the address signal input to the semiconductor memory device and the selection signal line. Upon receiving the selection signal from the SBW, the bit line pair BL1,
Transfer gate circuits DTR1 and DTR provided corresponding to each of BL2 and BLn and transmitting write data to the corresponding bit line pairs BL1, BL2 and BLn.
2, DTRn, and bit line pair BL1, BL2, BL
Differential amplifier circuits BLSA1 and BLSA, which are provided corresponding to each n and share the output signal line pair and the load circuit in common.
SA2, BLSAn selection signal lines SS1, SS2, SS
Generate a select signal on n.

Here, when the semiconductor memory device including the circuit shown in FIG. 2 is in the write operation state, the decoding circuit BD causes the memory cell block and the bit line pair BL included therein.
When BL1 of 1, BL2, and BLn is selected, the selection signal lines SBW and SS1 are set to “High” potential, and the transfer gate circuits BTR and DTR1 are set to “O”.
N "state and write data line pair GWB and WB
1 and the bit line pair BL1 are electrically connected, and the write data input to the semiconductor memory device is transmitted to the write data line pair WB1 through the write data line pair GWB,
It is transmitted to the bit line pair BL1.

Further, since the semiconductor memory device is in the write state, the write / read switching signal line WES has a "High" potential, the selection signal line SBR has a "Low" potential, and the differential amplifier circuit BSA is not selected and consumed. Power is reduced.
In addition, the signal line SBRB that is provided corresponding to each of the bit line pairs BL1, BL2, and BLn and controls the common load circuit LD1 of the differential amplifier circuit that shares the output signal line pair with the load circuit is "High". "Becomes potential and load circuit L
D1 is turned off, and bit line pair BL1, BL
2. A differential amplifier circuit BLSA is provided corresponding to each of BLn and BLn and has a common output signal line pair and load circuit.
1, BLSA2, and BLSAn are deselected to reduce power consumption.

(Second Embodiment) FIG. 3 is a circuit diagram of an input / output circuit connected to a bit line pair of a semiconductor memory device of the second embodiment of the present invention and a decode circuit for selecting them. In the figure, BL1, BL2, BLn are bit pair lines, BLS
A1, BLSA2, and BLSAn are provided corresponding to each bit line pair, and a differential amplifier circuit in which the output signal line pair and the load circuit are common, and LD1 is a differential amplifier circuit BLSA.
A load circuit common to 1, BLSA2, and BLSAn is composed of an N-channel insulated gate field effect transistor.
The difference between the second embodiment and the first embodiment is that the insulated gate field effect transistor forming the load circuit LD1 is changed from a P channel type insulated gate field effect transistor to an N channel type insulated gate field effect transistor, and its control signal is changed. There is a change from SBRB to SBR having the opposite phase, and the operation and effect of each circuit and signal line are similar to those of the first embodiment.

[0021]

As described above, according to the present invention, the occupied area of the bit line pair selecting decode circuit provided corresponding to each bit line pair is reduced, and
There is an effect that the driving load of the output signal line of the circuit for controlling the switching between the writing operation and the reading operation can be reduced to speed up the circuit operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to an embodiment of the present invention and a conventional example.

FIG. 2 is a diagram showing the configurations of an input / output circuit and a decoding circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing configurations of an input / output circuit and a decoding circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an input / output circuit and a decoding circuit in a conventional example.

[Explanation of symbols]

1 chip enable control circuit 2 switching control circuit 3 input / output circuit 4 column decoder 5 input / output control circuit 6 cell array 7 row decoder BL1, BL2, BLn bit line pair BLSA1, BLSA2, BLSAn, BSA differential amplifier circuit LD1, LD2 load circuit RB1 output signal line pair DTR1, DTR2, DTRn, BTR transfer gate circuit WB1 write data line pair SS1, SS2, SSn, SBR, BSA, SR1, S
R2, SRn, SW1, SW2, SWn selection signal line BLD1, BLD2, BLDn bit line pair selection decoding circuit GWB write data line pair WES write / read switching signal line BD decoding circuit SBRB control signal line WR control circuit

Claims (2)

[Claims] 1. A cell array (6) including a plurality of memory cells arranged in a matrix of m rows and n columns, and a memory cell of a corresponding column provided corresponding to each column of the memory cells. A pair of bit lines (BL1 to BLn) connected to each of the bit line pairs, and a differential amplifier circuit (corresponding to each of the bit line pairs and provided with the output signal line pair (RB1) and the load circuit (LD1) in common) BLSA1 to BLSAn), transfer gate circuits (DTR1 to DTRn) provided corresponding to each of the bit line pairs and transmitting write data to the corresponding bit line pairs, and control for controlling switching between write and read operations. In a semiconductor memory device including a circuit (WR), means for controlling the load circuit (LD1) by the control circuit (WR) ( D, BSA) and means (BLD1 to BLDn) for generating common selection signals (SS1 to SSn) for selecting the differential amplifier circuits (BLSA1 to BLSAn) and the transfer gate circuits (DTR1 to DTRn). A semiconductor memory device characterized by the above. 2. The semiconductor memory device according to claim 1, wherein the load circuit is a P-channel type insulated gate field effect transistor or an N-channel type insulated gate field effect transistor.