JPH06105457A - Battery protection circuit - Google Patents

Abstract

PURPOSE:To extend the operation life of a battery by providing a power down means and setting the power down mode depending on the balanced condition between over-discharge and over-charging conditions of each battery. CONSTITUTION:If either the battery A or battery B is in the switch over- discharge condition, a discharge switch of a charge/discharge switch means 6 is turned off with control of a discharge system control logic means 9. Under this condition, the power down mode starts when both batteries A and B enter the over-discharge condition. When the battery voltage detecting means 7 detects the battery A or B enters the over-charge condition, the charge switch of the charge/discharge switch 6 is turned off and simultaneously an over-flow circuit causes the battery in the over-charge condition to discharge. In the power down mode, a current to the circuits except for the required minimum number of circuits among the battery protection circuits under the over-discharge condition is cut off and thereby a sustaining period owing to the remaining capacitance can be set very longer, preventing the deterioration of characteristic of the battery.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called battery protection circuit for preventing overcharge and overdischarge of a secondary battery.

[0002]

2. Description of the Related Art In a battery pack in which a plurality of batteries are connected in series, a charger which detects overcharge or overdischarge based on the total voltage connected in series and a load side are turned on / off. Was preventing battery consumption.

Further, the battery protection function is provided not on the battery side but on the charger or load side, and when abnormal overcharging or excessive current occurs on the charger or load side,
Turns on / off the power supply by detecting the temperature of the battery or the thermostat in the battery pack.
Off.

However, in the above method, particularly in a battery composed of a plurality of batteries, if the characteristics of each battery are not uniform, there is a possibility that only a specific battery is overcharged or overdischarged. It cannot be practically used for a battery whose performance is greatly deteriorated by over-discharge and over-charge.

Therefore, a prior invention (Japanese Patent Application No. 3-213019) by the same application was proposed. In the invention of this prior application, even if the capacity balance of the batteries is lost due to individual differences in the batteries constituting each battery in the process of repeating charging and discharging the secondary batteries connected in series, it has a function of restoring the balance. In this method, a battery capacity balance circuit is provided in a charge / discharge circuit to prevent overcharge and overdischarge.

This battery capacity balance circuit is basically composed of a circuit for protecting the battery, which includes overcharge detection, charge current off, overflow detection, overdischarge detection, discharge current off, This is a method of protecting the battery by being composed of a circuit group for detection of hysteresis and overcurrent.

[0007]

However, in the above-mentioned prior invention, even if over-discharge or over-charge of the battery is detected, the current flows in the circuit group after the over-discharge is detected, and the current consumption is always constant. There is a problem that is occurring.

Therefore, it is necessary to protect the battery by protecting the battery by suppressing the discharge as much as possible by reducing the current flowing in the circuit after detecting the overdischarge together with the circuit group for detecting the overdischarge and overcharge of the battery. Has issues that must be addressed.

[0009]

As a concrete means for solving the above-mentioned problems, the present invention detects a secondary battery and the voltage of the battery, and compares the detected voltage with a reference voltage to obtain the secondary battery. State detection means for detecting an overdischarged state or an overcharged state of the battery, first and second switch means for cutting off the discharge current or the charging current, and the first based on the detection result of the state detection means And a control means for controlling conduction and non-conduction of the second switch means, in a battery protection circuit, at least a power down switch means for cutting off the power supplied to the state detecting means, and the state detecting means. There is also provided a battery protection circuit comprising: a power down means for bringing the power down switch means into a non-conducting state when an overdischarge state is detected. It is.

The power-down switch means is provided for returning the power-down switch means from the non-conducting state to the conducting state when charging is restarted from the over-discharged state; a plurality of the secondary batteries are connected in series. In the battery protection circuit, the power down means sets the power down switch means to a non-conducting state when one or all of the secondary batteries are detected to be over-discharged by the status detection means; When any one of the secondary batteries is overcharged, a power down inhibiting means is provided to prevent the power down switch means from being in a non-conducting state; when a large current is momentarily supplied, To prevent the power down switch means from becoming non-conductive,
A voltage drop prevention means for preventing the detection terminal voltage of the battery voltage from becoming equal to or lower than the overdischarge detection voltage is provided; further, a means for balancing the batteries for overcharging / discharging the plurality of secondary batteries is provided. The present invention provides a battery protection circuit characterized by the above.

[0011]

In the battery protection circuit according to the present invention, the power-down mode is set at the time of over-discharging, so that the current consumed by the circuit is extremely reduced, the power-down mode can be restored, and the battery protection circuit is connected in series. In the case of a secondary battery, by setting the power down mode by detecting the over discharge of one or all secondary batteries, the balance of each battery can be properly adjusted on the overcharge side or the overdischarge side, and the power down In the mode, even if the secondary battery is 0V, it can be charged.

[0012]

EXAMPLE A battery protection circuit according to the present invention,
Detailed description will be made with reference to the drawings. FIG. 1 is a block diagram showing an outline of a battery protection circuit of a first embodiment according to the present invention. In the block diagram, 1 is a battery protection circuit, and the battery protection circuit 1 includes a detection unit 2 and a control unit. The charge / discharge control is performed on the batteries Abat and Bbat, which are a plurality of batteries, and are configured by a unit 3, a return unit 4, a power-down SW unit 5, and a charge / discharge switch unit 6.

The detection unit 2 is composed of a battery voltage detection unit 7 and an overcurrent detection unit 8, and the battery voltage detection unit 7 is a battery Aba.
The overcharge (A, B) and overdischarge (A, B) states are detected from the respective voltages of t and Bbat, and the overcurrent detection unit 8 detects the overcurrent state.

The control unit 3 includes a discharge system control logic unit 9, a discharge SW control unit 10, a GND level shift unit 11, and
It is composed of a charging system control logic unit 12 and a charging SW control unit 13.

The discharge system control logic unit 9 and the discharge SW control unit 10 of the control unit 3 are charged / discharged states of the batteries Abat and Bbat detected by the battery voltage detection unit 7 of the detection unit 2 and the overcurrent detected by the overcurrent detection unit 8. From the state of the current signal, the battery voltage detection unit 7
To the charging / discharging switch section 6, which will be described later, and a power down signal to the restoring section 4.

Further, the discharge system control logic unit 9 and the discharge SW
The ground signal from the control unit 10 is input to the charging system control logic unit 12 and the charging SW control unit 13 via the GND level shift unit 11.

The GND level shift unit 11 of the control unit 3 has
Since the discharge switches of the discharge system control logic unit 9 and the discharge SW control unit 10 and the charge switches of the charge system control logic unit 12 and the charge SW control unit 13 have different grounds (GND), each ground potential is set as a constant reference. It is determined.

The charge system control logic unit 12 and the charge SW control unit 13 of the control unit 3 control the charge / discharge switch unit 6 from the battery state, charge detection (starting circuit), etc. Is output. The power down cancellation signal exits from the so-called power down mode when the battery voltage becomes equal to or higher than a predetermined voltage value.

The recovery unit 4 is composed of a power down control unit 14 and a start circuit charge detection unit 15, and the power down control unit 14 outputs power down signals from the discharge system control logic unit 9 and the charge system control logic unit 12. To the power-down SW section 5, which will be described later, and the activation circuit charge detection section 15 starts charging automatically or manually.

The power-down SW section 5 sends the power-down signal from the power-down control section 14 to the detection section 2 and the control section 3 to turn off the power source to enter the power-down mode.

The charging / discharging switch section 6 is a discharge S of the control section 3.
The charging and discharging of the batteries Abat and Bbat are controlled based on the control from the W control unit 10 and the charging SW control unit 13.

Next, the general operation during discharging and charging will be described based on the block diagram of FIG. [1] During discharge In a battery composed of a plurality of batteries Abat and Bbat, the battery voltage detection unit 7 of the detection unit 2 constantly monitors the discharge state of the battery Abat and the battery Bbat, and the battery Abat or the battery Bbat When any one of Bbat is in an overdischarge state, an overdischarge (A) signal or an overdischarge (B) signal is sent to the discharge system control logic unit 9 of the control unit 3, and the discharge SW control is performed by the control of the discharge system control logic unit 9. The unit 10 turns off the discharge switch of the charge / discharge switch unit 6.

By turning off the discharge switch of the charging / discharging switch section 6, the batteries other than over-discharge are controlled to overflow discharge. In this state, for example, the battery Ab.
In the case of a battery composed of at and Bbat, if both the batteries Abat and Bbat are in an overdischarged state, the power down mode is entered.

The power-down mode may be set when either of the batteries Abat and Bbat is in the over-discharged state. That is, if the battery is composed of the batteries Abat and Bbat, the battery Abat or the battery B
The power-down mode is entered when any of the bats is over-discharged.

Further, at the time of discharging, it is detected that an overcurrent having a predetermined value has flowed for a predetermined period of time.
When it is detected by, the discharge SW control unit 10 of the control unit 3 turns off the discharge switch of the charge / discharge switch unit 6. It should be noted that the power-down mode does not occur if the state of over-discharge or over-current is within a predetermined time due to a momentary large current.

[2] During charging When the battery voltage detecting unit 7 of the detecting unit 2 detects that the battery Abat or the battery Bbat is in the overcharged state in the battery composed of the battery Abat or the battery Bbat, The charge (A) signal or the overcharge (B) signal is sent to the charge system control logic unit 12 of the control unit 3, and the charge switch of the charge / discharge switch unit 6 is turned off. At the same time, although not shown, the overcharged battery is discharged by the overflow circuit.

Here, in the case of charging from the power-down mode, the charge SW control unit 13 of the control unit 3 is based on the charge detection signal from the starting circuit charge detection unit 15 of the restoration unit 4.
If the battery voltage detection unit 2 detects that the total battery voltage has risen to the predetermined voltage value or more by forcibly performing the charging operation under the control of, and forcibly canceling the power down mode, the power down is released. A signal is sent to the power-down control unit 14 of the recovery unit 4 to get out of the power-down mode, that is, to get out of the over-discharged state, and become the normal charged state.
Even if one of the battery Abat and the battery Bbat is in the overdischarged state, if the other is in the overcharged state, the power down mode is not entered and the overcharged state has the highest priority.

Next, the discharge characteristics and the power down mode of the battery composed of the batteries Abat and Bbat will be described. That is, the discharge characteristics of the battery are shown in FIG.
As shown in FIG. 5, the battery voltage continues to drop while drawing the discharge curve 16 with the elapse of the discharge time, and the state where the battery voltage becomes equal to or lower than the overdischarge voltage value 17 which is set to a predetermined voltage value is the overdischarge state.

When the detecting section 2 shown in FIG. 1 detects this over-discharged state, the discharge switch of the charging / discharging switch section 6 is turned off to eliminate the discharge to the load, and the battery voltage is held in the over-discharge region 18. The remaining capacity 19 can be calculated in advance.

However, even if the discharge to the load disappears, some current continues to flow in the battery protection circuit 1 shown in FIG. Therefore, since the discharge continues to proceed, the discharge curve of the remaining capacity 19 is 20
Becomes

Therefore, what has been devised is a power-down mode, which is a method of cutting off the current to the circuits of the battery protection circuit in the over-discharged state except for the minimum necessary circuit.

By providing this power-down mode, the discharge curve becomes the discharge direction 21, and during the period for maintaining the voltage by the remaining capacity 19 in the overdischarge state,
Compared with the case where the power down mode is not provided, there is a very large difference. For example, the remaining capacity 19 in the over-discharged state is 30 mAh, the circuit consumption current for operating in the over-discharge region 18 is 20 μA, and the circuit consumption for operating in the over-discharge region 18 when the power down mode is provided. If the current is set to 1 μA, as shown in Table 1 below, the time required for the battery voltage to reach 0 V from the overdischarge region 18 can be significantly improved.

[0033]

[Table 1]

As can be seen from this table, the time required for the battery voltage to reach 0 V can be greatly improved from 1500 hours to 30,000 hours, and in reality, the current consumption decreases to some extent as the battery voltage decreases. Therefore, it can be maintained for a longer period of time, and the performance deterioration caused by the battery being over-discharged can be prevented in advance.

Next, a battery protection circuit of the first embodiment according to the present invention will be described with reference to the drawings. FIG. 3 shows the configuration of the battery protection circuit 1, which is mainly composed of five comparators, a plurality of switching elements, and a plurality of gates, and the connection state of these is as follows. .

That is, the battery assembly incorporating the battery protection circuit 1 is connected to the positive side of the battery Abat via the fuse 23 connected to the positive connection terminal (Eb +) connected to the positive side of the charger or the load. The negative side of the battery Abat is connected to the positive side of the battery Bbat, which is a so-called series connection.

The negative side of the battery Bbat is connected to the negative side terminal (Eb) of the charger or the load via the discharging power NMOS transistor QD and the charging power NMOS transistor QC.
-) Is connected.

The battery protection circuit 1 is connected to the terminal VDD via the plus terminal (Eb +) and the protection resistor R10, and the terminal CPU is connected to the drain terminal of the NMOS transistor Q14 via the resistor R11.

Negative side of battery Abat and battery Bbat
The connection point with the positive side of is connected to the terminal VC, and the battery B
The terminal CPD on the negative side of bat is connected to the drain terminal of the PMOS transistor Q15 via the resistor R12, and is connected to the terminal VSS via the protection resistor R13.

A smoothing capacitor CA is interposed between the terminals VDD and VC, and a smoothing capacitor CB is interposed between the terminals VC and VSS.

Power N-channel MOS transistor Q
D (hereinafter referred to as power NMOS transistor QD)
Is the source, gate and drain terminals and the parasitic diode D
1, a source terminal of which is connected to the negative side of the battery Bbat and a gate terminal of which is terminal D
The drain terminal is connected to O and the drain terminal is connected to the drain terminal of the power NMOS transistor QC.

Power N-channel MOS transistor Q
C (hereinafter referred to as power NMOS transistor QC)
Is the source, gate and drain terminals and the parasitic diode D
2 is a transistor having a source terminal connected to a negative side terminal (Eb-) and a gate terminal connected to a terminal O.
The drain terminal is connected to V and the drain terminal is connected to the drain terminal of the power NMOS transistor QD. The negative terminal (Eb-) is connected to the terminal VM via the protection resistor R22. A terminal (Ec-) for distinguishing between charging and discharging may be connected from an intermediate position between the drain terminal of the power NMOS transistor QD and the source terminal of the power NMOS transistor QC.

The power-down switch PDSW1 is a switch that opens and closes in response to a power-down signal. One terminal of the power-down switch PDSW1 is connected to the terminal VDD, and the other terminal, the connection point a, has comparators COMP1, 2, 3, 4, 4. 5 is connected to the power input terminal.

The power-down switch PDSW2 is a switch that opens and closes in response to a power-down signal. One terminal of the power-down switch PDSW2 is connected to the terminal VC, and the other terminal is a resistor R.
It is connected to the other end of 11.

The power-down switch PDSW3 is a switch that opens and closes in response to a power-down signal. One terminal of the power-down switch PDSW3 is connected to the terminal VSS, and the other terminal is connected to the other end of the resistor R19.

The comparator COMP1 is composed of two input terminals and one output terminal, and one inverting input terminal (hereinafter referred to as a minus side input terminal) has a resistor R14.
Is connected to the connection point between the other end of R1 and one end of the resistor R15, the other non-inverting input terminal (hereinafter referred to as the positive side input terminal) is connected to the positive side of the reference voltage E1 (+1.5 V), and the output terminal is It is connected to one input terminal of the NOR gate G2. In addition, one end of the resistor R14 is connected to the terminal VDD and the resistor R15 is
The other end of the resistor R11 and the comparator COMP2
Connected to the positive side input terminal of the
The minus side of 1 is connected to the terminal VC.

The comparator COMP2 is composed of two input terminals and one output terminal, one minus side input terminal is connected to the plus side of the reference voltage E1 (+1.5 V), and the other plus side. The side input terminal is connected to the connection point between the other end of the resistor R15 and one end of the resistor R11, and the output terminal is connected to the input terminal of the NOR gate G8 and the gate terminal of the NMOS transistor Q14. The hysteresis switch input terminal of the comparator COMP2 is connected to the output terminal of the AND gate G1.

The comparator COMP3 is composed of two input terminals and one output terminal, and one minus side input terminal is connected to a connection point between the other end of the resistor R17 and one end of the resistor R18. The other plus side input terminal is connected to the plus side of the reference voltage E2 (+1.5 V), and the output terminal is connected to the input terminal of the NOR gate G2. still,
One end of the resistor R17 is connected to the terminal VC, and the other end of the resistor R18 is connected to one end of the resistor R19 and the plus side input terminal of the comparator COMP4.

The comparator COMP4 is composed of two input terminals and one output terminal, one minus side input terminal is connected to the plus side of the reference voltage E2 (+1.5 V), and the other plus side. The side input terminal is connected to the connection point between the other end of the resistor R18 and one end of the resistor R19, and the output terminal is connected to the input terminal of the NOR gate G8 and the gate terminal of the PMOS transistor Q15. The hysteresis switch input terminal of the comparator COMP4 is connected to the output terminal of the AND gate G1.

The comparator COMP5 is composed of two input terminals and one output terminal, one minus side input terminal is connected to the plus side of the reference voltage E3 (+ 0.4V), and the other plus side. The side input terminal is connected to the terminal VM, and the output terminal is connected to the other end of the resistor R4 forming the time constant CR and the input terminal of the AND gate G1.
Note that one end of the resistor R4 is connected to the input terminal of the NOR gate G9 and one end of the capacitor C2, and the other end of the capacitor C2 is connected to the terminal VDD.

The AND gate G1 has two input terminals and one
A gate composed of a plurality of output terminals, one input terminal connected to the output terminal of the comparator COMP5, the other input terminal connected to the output terminal of the NOR gate G2,
The output terminal is connected to the hysteresis switch input terminals of the comparators COMP2 and COMP4.

The NOR gate G2 is a gate consisting of two input terminals and one output terminal. One input terminal is the output terminal of the comparator COMP1 and the other input terminal is the output terminal of the comparator COMP3. The output terminal is connected to the input terminal of the AND gate G1, the input terminal of the knot gate G3, and the NMOS transistor Q13.
Is connected to the gate terminal of.

The input terminal of the NOT gate G3 is connected to the output terminal of the NOR gate G2, and the output terminal is connected to the input terminal of the NAND gate G4 and the input terminal of the NOR gate G9.

The NAND gate G4 has two input terminals and one
A gate having one output terminal, one input terminal connected to the output terminal of the NOT gate G3, the other input terminal connected to the output terminal of the NOR gate G8, and the output terminal of the NAND gate of the power down latch circuit. It is connected to the input terminal of G6.

The NAND gate G5 has two input terminals and one
A gate composed of a plurality of output terminals, the NAND gate G
6 forms a power down latch circuit with one input terminal connected to the other end of the resistor R1 and the other input terminal connected to the output terminal of the NAND gate G6,
The output terminal is connected to one end of the resistor R0, and a power down signal is generated from this output terminal. The other end of the resistor R0 is grounded, and one end of the resistor R1 is connected to the terminal VDD.

The NAND gate G6 has two input terminals and one
A gate composed of a plurality of output terminals, the NAND gate G
5 forms a power down latch circuit together with one input terminal connected to the output terminal of the NAND gate G5, the other input terminal connected to the output terminal of the NAND gate G4, and the output terminal connected to the input terminal of the NAND gate G5. It is connected.

The knot gate G7 is an element of the charging logic, and its input terminal is connected to the terminal VD via the resistor R1.
The output terminal is connected to the input terminal of the NAND gate G10.

The NOR gate G8 is a gate having two input terminals and one output terminal. One input terminal is connected to the output terminal of the comparator COMP2 and the other input terminal is the output of the comparator COMP4. The output terminal is connected to the input terminal of the NAND gate G4 and the input section of the GND level shift section forming the charging logic.

The NOR gate G9 is a gate having two input terminals and one output terminal, one input terminal is connected to the output terminal of the knot gate G3, and the other input terminal is connected to one end of the resistor R4 and It is connected to one end of the capacitor C2, and the output terminal is connected to the gate terminal of the power NMOS transistor QD via the terminal DO.

The AND gate G10 is a gate having two input terminals and one output terminal, one input terminal is connected to the output terminal of the knot gate G7, and the other input terminal is a GND level shift unit. 27, and the output terminal is connected to the gate terminals of the PMOS transistors Q9 and Q10.

The P-channel MOS transistor Q9 (hereinafter referred to as the PMOS transistor Q9) is a source,
A transistor consisting of a gate and a drain terminal,
The source terminal is connected to the terminal VDD, the gate terminal is connected to the output terminal of the NAND gate G10, and the drain terminal is N.
Drain terminal and terminal OV of MOS transistor Q10
Is connected to the gate terminal of the power NMOS transistor QC via.

N-channel MOS transistor Q10
(Hereinafter, referred to as NMOS transistor Q10) is a transistor including a source, a gate, and a drain terminal, and the source terminal is the terminal VM and the GND of the charging logic.
, The gate terminal is connected to the output terminal of the NAND gate G10, and the drain terminal is connected to the PMOS transistor Q.
It is connected to the gate terminal of the power NMOS transistor QC through the drain terminal of 9 and the terminal OV.

N-channel MOS transistor Q13
(Hereinafter, referred to as NMOS transistor Q13) is a transistor having a source, a gate and a drain terminal, the source terminal is connected to the terminal VSS, the gate terminal is connected to the output terminal of the NOR gate G2, and the drain terminal is the resistor R5. Is connected to one end of. The other end of the resistor R5 is connected to the terminal VM.

N-channel MOS transistor Q14
(Hereinafter, referred to as NMOS transistor Q14) is a transistor having a source, a gate, and a drain terminal. The source terminal is connected to the terminal VC, the gate terminal is connected to the output terminal of the comparator COMP2, and the drain terminal is a resistor. It is connected to the terminal CPU via R11.

P-channel MOS transistor Q15
(Hereinafter, referred to as PMOS transistor Q15) is a transistor having a source, a gate and a drain terminal, the source terminal is connected to the terminal VC, the gate terminal is connected to the output terminal of the comparator COMP4, and the drain terminal is a resistor. It is connected to the terminal CPD via R12.

The GND level shift section 27 has its input section connected to the output terminal of the NOR gate G8, and its output terminal connected to the input terminal of the AND gate G10.

The starting portion 28 is connected to the terminal VM at the input portion, and the output portion is connected to the terminal VDD through one end of the capacitor C1 and the resistor R1. The other end of the capacitor C1 is grounded.

Battery protection circuit 1 in the above connected state
The terminal voltage of each battery Abat, Bbat in
With the comparators COMP1 to COMP4, the reference voltage value E
1, E (± 1.5V) and ladder resistance group (R14, R1
5, R11, R17, R18, R19) to detect the overcharge or overdischarge. That is,
The comparators COMP1 and COMP3 input the positive reference voltages E1 and E2 (+ 1.5V) to the plus side input terminals to be the reference, and the comparators COMP2 and COMP4 subtract the positive reference voltages E1 and E2 (+ 1.5V) from the minus. It is input to the side input terminal and is used as a reference, and is compared with the detected voltage value obtained by dividing the terminal voltage of the batteries Abat and Bbat.

Here, resistors R14 and R1 connected in series are connected.
The ladder resistor group consisting of 1, R17, R18 and R19 is
At the time of overcharge and overdischarge voltage, the reference voltages E1 and E2
This is a resistor group that divides voltage so that it can be compared with 1.5 V). Further, the comparator COMP5 has a reference voltage value E3 (+
0.4 V) and the voltage value of the negative terminal (Eb−) are compared and used for detecting an overcurrent.

Next, the second embodiment according to the present invention will be described with reference to FIG.
As shown in FIG. 3, a balance circuit for both overcharge and overdischarge is added, and a balance circuit is newly added to the overcharge and overdischarge detection circuit shown in FIG. 3 of the first embodiment. is there. The connection state of the added elements will be described below, and the other connection states are the same as those in FIG. 3, so detailed description will be omitted.

The output terminal of the comparator COMP1 is
It is connected to the input terminals of the AND gate 11, the NOT gate G12, and the OR gate G2.

The output terminal of the comparator COMP2 is
It is connected to the input terminals of the OR gate G14 and the NOR gate G8.

The output terminal of the comparator COMP3 is
It is connected to the input terminals of the OR gate G2 and the NOT gate G15.

The output terminal of the comparator COMP4 is
It is connected to the input terminals of NOR gate G8 and NOR gate G17.

The AND gate G11 is a gate having two input terminals and one output terminal, one input terminal of which is connected to the output terminal of the comparator COMP1.
The other input terminal is connected to the output terminal of the comparator COMP3, and the output terminal is connected to the input terminal of the NAND gate G4.

The input terminal of the NOT gate G12 is connected to the output terminal of the comparator COMP1, and the output terminal is connected to the input terminal of the AND gate G13.

The AND gate G13 is a gate having two input terminals and one output terminal, one input terminal is connected to the output terminal of the knot gate G12, and the other input terminal is the comparator COMP3. Is connected to the output terminal of the OR gate G14, and the output terminal is connected to the input terminal of the OR gate G14.

The OR gate G14 has two input terminals and one
A gate having a plurality of output terminals, one input terminal is connected to the output terminal of the AND gate G13, the other input terminal is connected to the output terminal of the comparator COMP2, and the output terminal is the gate of the NMOS transistor Q14. It is connected to the terminal.

The input terminal of the knot gate G15 is connected to the output terminal of the comparator COMP3, and the output terminal is connected to the input terminal of the AND gate G16.

The AND gate G16 is a gate having two input terminals and one output terminal, one input terminal of which is connected to the output terminal of the comparator COMP1.
The other input terminal is connected to the output terminal of the NOT gate G15, and the output terminal is connected to the input terminal of the NOR gate G17.

The NOR gate G17 has two input terminals and one
One output terminal is connected to the output terminal of the AND gate G16, the other input terminal is connected to the output terminal of the comparator COMP4, and the output terminal is the gate of the MOS transistor Q2. It is connected to the terminal.

The NMOS transistor Q14 is a transistor having a source, a gate and a drain terminal. The source terminal is connected to the terminal VC, the gate terminal is connected to the output terminal of the OR gate G14, and the drain terminal is connected via the resistor R12. It is connected to the terminal CPU.

The PMOS transistor Q15 is a transistor having a source, a gate and a drain terminal, the source terminal is connected to the terminal VC, the gate terminal is connected to the output terminal of the NOR gate G17, and the drain terminal is connected via the resistor R12. It is connected to the terminal CPD.

By making such a connection, the operational difference from the first embodiment is that the comparator CO
A circuit for maintaining a balanced state due to over-discharge detection by MP1 and COMP3 is added. Therefore, the battery Ab
The power-down mode can be entered when both at and Bbat are in the overdischarge state (input condition of the AND gate G4).

When the power down mode is actually entered, a power down switch (PDSW) is provided on the negative side (ground) of the comparators COMP1 to 5, the ladder resistance group and the reference voltage to cut off the power supply. . Since it is substantially the same as that of the first embodiment, it should be understood by the following explanation of the operation in the first embodiment.

Next, the operation of the battery protection circuit based on such a reference voltage value will be described item by item. (1) In the case of charging and overcharging. In the case of charging, from the positive side terminal (Eb +), which is a connection terminal with an external charger or a discharge load terminal, through the secondary batteries Abat, Bbat, the power NMOS transistors QD, QC, the negative side terminal (Eb-). Charge current flows to.

In the case of the battery Abat, this charging current is constantly monitored by the overcharge detection circuit centered on the comparator COMP2 for an overcharge voltage (eg, 4.4 V). Lator CO
An H level signal is output from the output terminal of MP2.

The H level signal from the comparator COMP2 is input to the input section of the GND level shift section 27 of the charging logic via the NOR gate G8 to be ground level shifted (described later), and its output section. Sends an H level signal.

On the other hand, the activation unit 28, as shown in FIG.
When the battery charger equipped with the battery protection circuit 1 of the present invention is set, the button 24, which is constantly mechanically pushed outward by the spring 26, is pushed inward to connect the contacts 25, 25. ing.

Therefore, since it is in the set state during charging, the L level signal which is the signal from the terminal VM is input to the input terminal of the knot gate G7 of the charging circuit logic,
The output terminal becomes an H level signal. Therefore, the input condition of the AND gate G10 is satisfied, and its output terminal is L
When the signal becomes a level signal, the PMOS transistor Q9 is turned on and the NMOS transistor Q10 is turned off, so that the power NMOS transistor QC is turned off and the charging current is cut off.

At this time, the signal from the hysteresis input terminal of the comparator COMP2 is the signal from the output terminal of the comparator COMP5 unless an overcurrent is detected.
Since it is an L level signal, the signal at the output terminal of the AND gate G1 is an L level signal. Therefore, the hysteresis width voltage (for example, 0.2
By giving the margin of V), it is possible to avoid the operation of immediately starting charging again.

At the same time, the H-level signal from the output terminal of the comparator COMP2 turns on the NMOS transistor Q14 to discharge the overcharge overflow current and protect the battery Abat which is a battery. That is, when the NMOS transistor Q14 is turned on, the terminal CP connected to the positive side of the battery Abat
A current flows through the resistor R11 via U and discharges to a voltage lower than the hysteresis width (for example, 4.2 V). Battery B
Comparator COMP4 and PM used in bat
The OS transistor Q15 and the like also have the same function, and thus the description thereof is omitted.

That is, the battery (battery Abat, Bbat) can be protected by activating a circuit having hysteresis so as not to charge immediately after the charging current is cut off and discharging the overcharge overflow current. .

(2) In the case of over discharge. By connecting a load to the terminal (Eb +) and the terminal (Eb-), the battery (battery Abat and battery Bbat) is in a discharged state.
This discharge state is constantly monitored by the over-discharge detection circuit centered on the comparators COMP1 and COMP3. Hereinafter, the comparator COMP1 that detects the over-discharged state of the battery Abat will be mainly described. That is, when the discharge state continues and the voltage of the battery Abat becomes the over-discharge voltage (for example, 2.4 V), it is compared with the reference voltage value E1 (+1.5 V), and the comparator COM
An H level signal is output from the output terminal of P1.

The H level signal from the output terminal of the comparator COMP1 is input to the NOT gate G3 and the NOR gate G9 via the NOR gate G2, the output signal of the NOR gate G9 becomes L level, and the power NMOS transistor QD is turned on. Turn off to interrupt the discharge current.

On the other hand, the L level signal (power down signal) from the NAND gate G4 is input to the NAND gate G6 of the power down latch circuit, and the NAND gates G5 and G5.
The latch state is set at 6, and by holding this state, the power down signal becomes L level, and the power down mode is set.

The power-down signal at the L level shuts off the power supply of the reference voltage values E1, E2, E3. At the same time, by opening the power down switch PDSW1 connected to the terminal VDD, the comparators COMP1, COMP2, COMP3, COMP4,
Turn off the power of COMP5.

Then, the signals from the output terminals of the comparators COMP2 and 4, that is, the output signals from the overcharge detection circuit are set to L level signals, and the comparators COMP1 and CO2.
The circuit is switched so that the overdischarge output side of MP3 becomes H level, and the overcurrent detection signal of the comparator COMP5 becomes H level, and the power NMOS transistor QD,
QC turns off.

Further, the power-down signal at L level is supplied to the power-down switch P connected to the terminal VC.
The power down switch PDSW3 connected to the DSW2 and the terminal VSS is opened to cut off the power supplied to the ladder resistance group (resistors R14, R15, R11, R17, R18, R19).

(3) In case of overcurrent detection. The detection of overcurrent is configured by a circuit centered on the comparator COMP5, and is detected by comparing with the reference voltage value E3 (+ 0.4V). That is, when the potential difference caused by the voltage drop due to the ON resistance of the power NMOS transistor QD and the power NMOS transistor QC (for example, 100 mΩ in total) exceeds the reference voltage value E3 (+0.4 V), the signal at the output terminal of the comparator COMP5 is It becomes H level.

The H level signal from the output terminal of the comparator COMP5 is supplied to the power source via the NOR gate G9 after a lapse of a time zone (for example, about 1.8 msec) generated from the time constant CR composed of the resistor R4 and the capacitor C2. The NMOS transistor QD is turned off to cut off the discharge current. In this state, that is, when the power NMOS transistor QD is turned off, the plus side terminal (Eb +)
The high voltage of the terminal (Eb +) becomes the voltage value of the terminal VM via the load connected to the negative terminal (Eb−). Therefore, the high voltage value generated at the terminal VM becomes a value close to the voltage value generated at the terminal (Eb +), and the overcurrent detection signal on the output side of the comparator COMP5 can be held at the H level.

Here, when the load connected between the positive side terminal (Eb +) and the negative side terminal (Eb-) is removed, the voltage of the terminal VM is reduced to about 0V through the NMOS transistor Q13 and the resistor R5. By pulling down, the overcurrent detection signal at the output terminal of the comparator COMP5 becomes L level, and it is possible to recover from the overcurrent state.

The time constant CR consisting of the resistor R4 and the capacitor C2 is a predetermined time (for example, about 1.8 msec).
The above time is given. This is provided so as not to turn off the power NMOS transistor QD when a momentary large current flows due to a capacitor load or the like.

When the balance of the battery consisting of the batteries Abat and Bbat is extremely different and one battery is in an overcharged state (for example, after charging and during overflow discharge),
Even if the other battery is over-discharged, the NAND gate G4 prohibits the power-down mode. Therefore,
If the battery is turned off during the overflow discharge, the battery can be protected by preventing the battery from being left in the over discharge state.

(4) Hysteresis release signal (output signal of AND gate G1). Overcharged state (eg immediately after charging)
The discharge current flows to the parasitic diode D2 because the power NMOS transistor QC is turned off, and the forward voltage (eg, about 0.7) of the parasitic diode D2 is discharged.
V) raises the voltage of the terminal VM, and the overcurrent detection circuit operates to prevent discharge.

Therefore, when the signal at the output terminal of the comparator COMP5 of the overcurrent detection circuit becomes H level, the H level signal is input to the hysteresis input terminals of the comparators COMP2 and COMP4 to force the hysteresis. To release. When the hysteresis is released, the overcharge detection returns to the normal state, so that the power NMOS transistor QD turns on and discharge becomes possible.

When either the battery Abat or the battery Bbat is in the over-discharged state, cancellation of hysteresis is prohibited by the AND gate G1. In the over-discharged state, the discharge current cannot flow, but if the hysteresis is released, the power-down mode is set, and the overflow current of the battery Abat or the battery Bbat in the over-charged state is turned off and remains in the over-charged state. This is to protect the battery by avoiding accidental loss. It should be noted that it is a very rare case that one side is overcharged and the other side is overdischarged.

(5) Charging from the power down mode.
If a charger is connected between the positive side terminal (Eb +) and the negative side terminal (Eb-), a charging voltage will be applied between both terminals and the charging voltage will be higher than the battery voltage (battery Abat, Bbat voltage), so the negative side terminal The voltage of (Eb−) becomes lower than the negative voltage (GND) of the battery Bbat.
In the power down mode, the power NMO is set as described above.
Both the S transistor QD and the power NMOS transistor QC are off.

In this state, the SW of the starting unit 28 is turned on, the input of the knot gate G7 becomes L level, and the knot gate G7 and the NAND gate G10 turn on the PMOS transistor Q9 and turn off the NMOS transistor Q10 (see FIG. 9 described later). (See the above), the potential of the terminal OV becomes the potential of the plus side terminal (Eb +) via the terminal VDD, the power NMOS transistor QC is turned on, charging is started, and a charging current can flow.

Here, the power NMOS transistor Q
When C turns on, the voltage at the negative terminal (Eb−) rises and becomes a voltage slightly lower than GND. This voltage is battery A
The situation changes depending on the holding voltage of bat and Bbat. That is, when the holding voltage of the batteries Abat and Bbat is 0V, the voltage between the drain terminal and the source terminal of the power NMOS transistor QC becomes equal to the cutoff voltage Vgsof between the gate terminal and the source terminal of the power NMOS transistor QC.
It does not fall below f (for example, 2V).

As a result, the power NMOS transistor QC is turned on when the gate voltage is 0 V and the source voltage, that is, the voltage of the terminal VM is negative, and the charging current flows.
At this time, since the power NMOS transistor QD is off, the charging current will flow through the parasitic diode D1 of the power NMOS transistor QD. Since the GND level of the charging logic is the potential of the terminal VM, the voltage drop due to the charging generated in the power MOS transistors QD and QC serves as the voltage source for the operation of the charging logic.

As the battery is charged a little and the holding voltage of the battery rises, the gate voltage of the power NMOS transistor QC also rises, and the minus voltage of the terminal VM decreases. When the charging is further advanced and the power down mode is exited, the power NMOS transistor QD is turned on and the voltage of the terminal VM becomes approximately 0V.

When the voltages of the batteries Abat and Bbat both become over discharge voltage or more, the comparators COMP1 and C
Both signals at the output terminals of the OMP2 become L level signals, signals at the output terminals of the NOR gate G2 become H level signals, and signals at the input terminals of the NAND gate G6 become H level signals. On the other hand, since the signal at the input terminal of the NAND gate G5 is an L level signal, the output of the NAND gate G5 becomes an H level signal, and the two inputs of the NAND gate G6 become an H level signal. Get out of down mode.

(6) Return from power down mode. When returning from the power down mode, the power down signal is L
It is possible to recover by going from the level to the H level.

The reference voltage values E1, E2, E3 are shown in FIG.
, The reference voltage 20k is the battery voltage 20d, 20
A desired reference voltage value can be easily obtained by raising the voltage with l and 20 m so that the voltage becomes constant.

As for the voltage for which this reference voltage value can be secured, if the reference voltage value is 1.5 V, the voltage of 3 V (reference voltage E1 + E2) is required at the minimum, and the detection range of the voltage value is
It may be 3V (reference voltage E1 + E2) to 4V (a value slightly lower than the overcharge voltage).

(7) Charging logic. When charging starts,
An H-level signal is input to the NOR gate G7 from the start-up unit, outputs an H-level signal, and is set as one input condition of the NAND gate G10, and the other input condition is an overcharge unless the H-level signal is passed through the ground level shift. Therefore, all the input conditions of the NAND gate G10 are satisfied,
The L level signal is output, and the PMOS transistor Q9
Is turned on and the NMOS transistor Q10 is turned off, the signal at the terminal OV becomes H level and the power N
The MOS transistor QC is turned on, and the charging current flows.

Then, the H level signal from the starting section is
Since it is a mechanically transmitted signal as shown in FIG. 5,
Since the signal at the terminal CO maintains the H level, charging continues.

In the state where the above-mentioned charging is continued, if the state of overcharging is reached, the signal from overcharging becomes L level and is shifted to the ground level (described later) and input to the NAND gate G10 to satisfy the input condition. The output terminal becomes an H level signal, the terminal CO signal becomes an L level signal, the power NMOS transistor QC is turned off, and the charging current is cut off.

(8) Description of ground level shift. The ground level shift will be described with reference to FIGS. 7 and 8. This ground level shift is the power NM that is the discharge side ground (potential of the battery ground terminal VSS).
The source potential of the OS transistor QD and the potential of the source terminal of the power NMOS transistor QC, which is the charging side ground (potential of the terminal VM), are shifted to the same potential. 7 is the same as FIG. 3 described above.
A charging / discharging circuit centering on a power NMOS transistor QD and a power NMOS transistor QC in the entire circuit diagram shown in (FIG. 4 in the second embodiment), in which the power NMOS transistor QC to be charged and the power to be discharged are The NMOS transistor QD cannot be completely turned off unless it is set to 0V with respect to the potential of the terminal VM and the potential of the terminal VSS, respectively.

In order to solve this inconvenience, a resistor is provided in the charging logic to add a so-called ground level shift function. This ground level shift will be described in detail with reference to FIG. 8. FIG. 9 shows the QP of the MOS transistor of the charge logic of FIG. 3 (or FIG. 4) described above.
And QN, and is represented by resistance R.

That is, when the potential of the terminal VSS at the point x is a signal of L level and the potential of the terminal VM is the same as the potential of the terminal VSS, the MOS transistor QP turns on and the MOS transistor QN turns off. As a result, the OUT signal becomes H level, and there is no problem. However, if the potential of the terminal VM becomes low without the resistance R interposed (which is always the case during charging), the MOS transistor QN also turns on, and both the MOS transistor QP and the MOS transistor QN turn on. In other words, the H level state of the OUT signal becomes an uncertain state level because of the short circuit state, and further, a short circuit current flows between the MOS transistor QP and the MOS transistor QN.

Therefore, as shown in FIG. 8, a resistor R is provided between the MOS transistor QP and the MOS transistor QN.
The MOS transistor QN
Is turned on, the y point only goes to L level, and
The H level state of the UT signal is secured. Since a short-circuit current will flow through this resistor R, it is necessary to set the resistance value to several K ohms to several M ohms. This short current flows only during charging. Also, when point x is at H level,
The OUT signal becomes L level (that is, the potential of the terminal VM) regardless of whether the potential of the terminal VM is low or high.

(9) Circuit in power down mode. When the power down mode is entered, the output of each comparator is cut off, and each is in the required signal state. That is, the overcharge detection output signal is at L level, the overdischarge detection output signal is at H level, the overcurrent detection output signal is at L level,
It can be controlled by a power down signal by appropriately incorporating a MOS transistor or the like. Further, the NMOS transistor Q13 of the constant current circuit is a circuit for setting the voltage of the terminal VM to 0V when there is no load, and is naturally turned off in the power down mode.

In addition, terminals VDD, CPU, CPD,
Resistors R10, R11, R1 attached to VSS, VM
2, R13 and R22 are for protection, and basically no potential difference due to resistance occurs.

The third embodiment according to the present invention is shown in FIGS.
As shown in, for example, when the charging terminal is the plus terminal side (Eb +) and the minus side terminal (Eb-), the discharging terminal is the plus side terminal (Eb +) and the minus side terminal (Eb-). As described above, the charging terminal and the discharging terminal are physically separated to eliminate the obstacles during charging and discharging.

[0127]

As described above, the battery protection circuit of the present invention has the following effects. (1) By switching to the power-down mode during over-discharge, the current consumed by the circuit can be extremely reduced, so that the maintenance period due to the remaining capacity can be made extremely long and the battery over-discharge state can be maintained. It can be suppressed to prevent performance deterioration.

(2) By providing the power-down canceling means for returning from the power-down mode, it is possible to automatically return to the normal state, which makes the handling extremely simple.

(3) In the case of secondary batteries connected in series, one or all of the secondary batteries are appropriately selected to detect the over-discharge state and the power-down mode is set to consider the balance state of each battery. By setting the power down mode, it is possible to prevent the performance deterioration of each battery and extend the battery life.

(4) Even if the secondary battery is at 0V in the power down mode, the charging means is provided so that the battery can be automatically charged by the charging operation even if it is left for a long time.

(5) The provision of the power-down prohibiting means under a certain condition can minimize the interaction between the batteries, and thus the performance deterioration of each battery can be suppressed to the minimum.

(6) By preventing entry into the power down mode due to a momentary large current, malfunctions due to load variations and momentary variations from the outside due to so-called short circuits are avoided, and continuous use is performed. be able to.

(7) The life of the entire battery can be extended by balancing the overcharging and discharging of each battery.

(8) By separating the charging terminal and the discharging terminal, it is possible to prevent troubles during charging and discharging.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a battery protection circuit according to the present invention.

FIG. 2 is an explanatory diagram showing a battery discharge characteristic in the same manner.

FIG. 3 is an overall circuit diagram of the battery protection circuit.

FIG. 4 is an overall circuit diagram of the battery protection circuit of the second embodiment.

FIG. 5 is a schematic explanatory view of a starting unit of the same.

FIG. 6 is a graph showing a case where the reference voltage rises together with the battery voltage and becomes a constant voltage in the relationship of the reference voltage and the overcharge / overdischarge detection.

FIG. 7 is an explanatory diagram showing a state of the ground (GND) of the power MOS transistor.

8 is a block diagram showing an example of so-called ground level shift in which the ground (GND) shown in FIG. 7 is shifted to have the same potential.

[Explanation of symbols]

1 Battery Protection Circuit 2 Detecting Section 3 Control Section 4 Restoring Section 5 Power Down SW Section 6 Charge / Discharge Switch Section 7 Battery Voltage Detection Section 8 Overcurrent Detection Section 9 Discharge System Control Logic Section 10 Discharge SW Control Section 11 GND Level Shift Section 12 Charging system control logic section 13 Charging SW control section 14 Power down control section 15 Starting circuit charge detection section 16 Discharge curve 17 Over discharge voltage value 18 Over discharge area 19 Remaining capacity 20, 21 Discharging direction 23 Fuse 24 Button 25 Contact 26 Spring 27 GND level shift unit 28 Start-up unit 29 Overcharge region 30 Battery voltage 31 Change of reference voltage 32, 33 Comparative voltage Abat, Bbat Battery COMP1-COMP5 Comparator C2 Capacitor C3 Smoothing capacitor D1, D2 Parasitic diode Eb + Positive side terminal Eb Negative side terminal G2, G8, G9, G17 NOR gate G3, G7, G12, G15 NOT gate G1, G11, G13, G16 AND gate G4, G5, G6, G10 NAND gate G14 OR gate PDSW1-3 power down switch Q1 to Q15 MOS transistor. QC, QD Power MOS transistor CPU, VDD, VC, CPD, VSS, DO, OV,
VM terminal

Front page continued (72) Inventor Kanji Murano 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Inventor Hitoshi Okada 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation Shares In the company

Claims (7)

[Claims] 1. A secondary battery, and state detection means for detecting the voltage of the battery and comparing the detected voltage with a reference voltage to detect an over-discharged state or an overcharged state of the secondary battery. First and second switch means for interrupting the discharge current or the charge current, and control means for controlling conduction and non-conduction of the first and second switch means based on the detection result of the state detection means In a battery protection circuit including: a power down switch means for cutting off at least the power supplied to the state detection means, and the power down switch means is non-conducted when an overdischarge state is detected by the state detection means. A battery protection circuit comprising a power-down means for bringing the battery into a state. 2. The power down release means for returning the power down switch means from the non-conducting state to the conducting state when charging is started again from the over-discharged state. Battery protection circuit. 3. In a battery protection circuit in which a plurality of the secondary batteries are connected in series, the power down means detects one or all of the secondary batteries by the state detecting means. The battery protection circuit according to claim 2, wherein the power down switch means is turned off. 4. The power down prohibition means for preventing the power down switch means from being in a non-conductive state when any one of the secondary batteries is in an overcharged state. Battery protection circuit described. 5. A voltage for preventing the detection terminal voltage of the battery voltage from becoming equal to or lower than the over-discharge detection voltage so that the power down switch means does not become non-conductive when a large current instantaneously flows. The battery protection circuit according to claim 1 or 3, further comprising a fall prevention means. 6. A battery balancing means for overcharging / discharging a plurality of the secondary batteries is provided.
Battery protection circuit described in. 7. The battery protection circuit according to claim 1, wherein the charging terminal and the discharging terminal are separated from each other.