JPH06105297A - Encoder - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by limiting the input value of a code length calculator which calculates a code length after encoding within a prescribed range. CONSTITUTION:Whether a quantized value inputted from an input terminal 1 is '0' or not is judged by a zero detector 2. When the quantized value is 0, the zero detector 2 outputs '1', and when the quantized value is not 0, the zero detector 2 outputs '0', and the zero detector 2 controls a zero run counter 3 and a cumulative adder 7. The zero run counter 3 counts the number of clocks while the zero detector 2 outputs '1', and the quantized value and the count value are rounded by limiters 4 and 5. Then, the code length is calculated by a code length calculator 6 by using the outputs of the limiters 4 and 5. The calculated code length is computed by the cumulative adder 7 synchronously with the clock when the output of the zero detector 2 is '0'. After the cumulative addition of one DCT block is ended, the cumulative added result is stored in a register 8. A cumulative adder 9 operates the cumulative addition processing to the output value of the register 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device for variable length coding image information and audio information.

[0002]

2. Description of the Related Art In recent years, with the digitization of image signals, high efficiency coding technology has become important. Orthogonal transform coding is typical as an effective means of high-efficiency coding, and has recently started to be widely used. Orthogonal transformation is a component that orthogonalizes the input time-series signal (eg, frequency component)
Fourier transform, discrete cosine transform (hereinafter referred to as DCT), Hadamard transform and the like are well known. In particular, DCT is drawing attention as an orthogonal transform suitable for image information.

An example of this encoding device is shown in the block diagram of FIG. In the figure, 10 is a small block conversion unit, 11 is a large block conversion unit, 12 is an orthogonal transformer, 13 is a data amount estimation unit, 14 is a quantizer determination unit, 1
5 is a data buffer, 16 is a quantizer, 17 is a variable length encoder, and 18 is a transmitter.

The small block forming unit 10 divides the input image signal into small blocks of a two-dimensional block having a total of 64 pixels of horizontal 8 pixels and vertical 8 pixels (this small block is the minimum unit for the subsequent signal processing). To do. The small blocks are grouped into one large block by the large block converting unit 11 for each set of 30 small blocks. FIG. 3 is a block diagram of a large-blocking section, in which 19 is a luminance (Y) signal input section and 20 is a color difference signal R-.
Y (C _R) input unit, 21 color difference signal _B-Y (C B) input unit, 22 frame memory, 23 an address controller. Luminance (Y) signal input unit 19, color difference signal RY
(C _R ) input unit 20, color difference signal BY (C _B ) input unit 21
The input sample value for each small block is once stored in the frame memory 22, and is output to the orthogonal transformer 12 for each large block consisting of 30 small blocks according to the address controller 23.

Here, the shaded blocks in FIG. 4 indicate small blocks, and 30 small blocks at various positions on the screen are shuffled together to form one large block. Since the amount of information on the screen is dispersed by such shuffling, the amount of information included in each large block becomes approximately equal. Therefore, even if the amount of information is biased depending on the location on the screen, the information can be efficiently compressed.

The orthogonal transformer 12 performs a two-dimensional orthogonal transformation on the input small-block sample value by discrete cosine transform (DCT) for each unit. In the orthogonal transformer 12, first, DCT is performed in the horizontal direction of the small block.
The orthogonal component that has been subjected to DCT in the horizontal direction next is a horizontal / vertical rearrangement unit (not shown) built in the orthogonal transformer 12.
After being rearranged in the vertical direction, DCT is performed in the vertical direction. FIG. 5 shows such two-dimensional orthogonal transformations, which are arranged in order from the lowest frequency component. In FIG. 5, the upper left corresponds to the lowest frequency component both in the horizontal and vertical directions, the orthogonal component indicating the higher frequency in the horizontal direction is arranged on the right side, and the orthogonal component indicating the lower frequency in the horizontal direction is arranged on the left side. The numbers in FIG. 5 indicate the output numbers of the orthogonal components arranged as described above. Therefore, the orthogonal components of each of the small blocks (hereinafter referred to as DCT blocks) subjected to the two-dimensional DCT in this manner are sequentially supplied to the buffer 15 and the data amount estimation unit 13 in the large blocks in the horizontal and vertical directions from the orthogonal component representing the low frequency band. Entered in units.

The data estimating unit 13 calculates the amount of data after variable length coding in small block units for the 16 quantizers prepared in advance, and based on the result, the quantizer determining unit 14 Then, the quantizer for each small block is determined so that the total amount of data of all small blocks does not exceed the total amount of data that can be transmitted. At the same time, the orthogonal components input to the buffer 15 are delayed until the quantizer is determined. The quadrature component output from the buffer 15 is quantized by the quantizer 16 using the quantizer determined (selected) by the quantizer determination unit 14.

By the way, since human vision is generally sensitive to distortion of low-frequency components and is insensitive to distortion of high-frequency components, visual deterioration is caused by performing quantization with a larger quantization width for higher-frequency components. It is possible to improve the compression ratio while reducing Therefore, the quantizer 1 including 16 kinds of quantizers
In FIG. 6, the orthogonal component of the (8 × 8) DCT block is divided into four bands (the numbers in the figure indicate the numbers of the respective bands) except for the DC component (hatched portion), as shown in FIG. There is a fixed relationship between this band and the quantization in the 16 quantizers. Table 1 shows the relationship between the band and the quantization.

[0009]

[Table 1]

In Table 1, the vertical direction indicates a quantizer No (quantization No) and the horizontal direction indicates four bands. That is, each quantizer is configured by a combination of quantizations for the four bands shown in FIG. In addition, the fractions in the table indicate multipliers of multiplications performed by the quantizer and the quantization for the band.

Next, the data quantized by the quantizer 16 is variable-length coded by the variable-length encoder 17 and then output via the transmitter 18.

FIG. 7 shows the transmission order of the large block DCT blocks. Each DCT block DCTNo order shown, _{i.e., Y → Y → C R →} Y → Y → C B → Y → Y → C R → Y → Y → C B
→… Transmitted in order. Here, Y is DCT block of the luminance signal, the C _R DCT block of R-Y signal, the C _B is a DCT block of B-Y signal.

Further, in consideration of the error correction at the time of reproduction of a large block (when a large error occurs, the block having an error is replaced with the previous block data for each block shown below), the transmission unit is considered. In 18 as shown in the figure, the data is divided into two blocks (the first block is called the first half 15DCT block and the second block is called the second half 15DCT block) and transmitted.

[0014]

In the encoding device configured as described above, the data amount is estimated as follows.

FIG. 8 shows a block diagram of the calculation circuit of the data amount estimation unit. In addition, the variable length coding used in this coding apparatus is such that, for a quantized value having a value of zero, the number of consecutive quantized values of zero (zero run) after the quantized value (zero run length) and , And the following two types of quantized data are combined and encoded into one codeword. In this way, by encoding the length of consecutive zeros and the non-zero quantized value together into one codeword, it is possible to efficiently code the quantized value of the orthogonal component having a high occurrence probability of zero. .

In FIG. 8, reference numeral 24 denotes an input terminal to which the quantized values quantized by the 16 kinds of quantizers shown in Table 1 are input, and 25 outputs "1" if the quantized value is 0, A zero detector for controlling a zero run counter 26 and a cumulative adder 28, which will be described later, based on the signal, 26 is a zero detector 25.
Is a zero-run counter that counts clocks for a period of "1" when it is output and resets it when it is "0". That is, it means that the number of consecutive quantized values of zero is counted.
27 is a code length calculator for calculating the code length after encoding, 28
Is a cumulative adder configured to perform calculation if the output of the zero detector 25 is '0', and 29 is a DC output of the cumulative adder 28.
A register that stores the total code length in T blocks, 3
0 is a cumulative adder for cumulatively adding the output value of the register 29, which is the sum of the code lengths in DCT block units.

FIG. 9 shows the timing for explaining the operation of the calculation circuit of the data amount estimation unit. In the figure, (a) is the system clock, (b) is a start signal indicating the first quantized value in DCT block units, (c)
Is the quantized value input from the input terminal 24, (d) is the output of the zero detector 25, (e) is the output of the zero run counter 26, (f) is the output of the code length calculator 27, and (g) is This is the calculation result of the cumulative adder 28. As an example, consider a case where the following quantized values are sequentially input from the input terminal 24 as 10 → 0 → 0 → 16 → 3 → 0 → 9 → .... Here, the encoding is
Zero run and the quantized value following it are represented by (i, j) (where i: zero run length, j: quantized value),
This is performed in units of (i, j). In the above case, encoding is performed in the following order.

(0,10) → (2,16) → (0,3) → (1,9)
→ ... The operation will be described below with reference to FIGS. 8 and 9.

A start signal is output from a start flag generator (not shown) of the small block, and the start signal is "1".
At the same time, the first quantized value 10 in small block units is input from the input terminal 24 in synchronization with the clock, and at the same time, the zero-run counter 26 and the cumulative addition 28 are reset to 0 in synchronization with the clock. The time at this time is t ₀ . The code length calculator 27 calculates the code length according to Table 2.

[0020]

[Table 2]

Table 2 is a table showing the code length of the codeword corresponding to the zero run length and the quantized value that follows it. The vertical axis represents the output value from the zero-run counter 26, the horizontal axis represents the quantized value input from the input terminal 24, and the intersection thereof represents the code length of the code word. In this case, since the output value from the zero run counter 26 is 0 and the quantized value is 10 from the input terminal 24 (0, 10), the code length of the code word is 8. Since the output of the zero detector 25 is “0” at the rising time t ₁ of the next clock, the cumulative adder 28 calculates (0 + 8 = 8). At the same time, input terminal 2
The next quantized value 0 is input from 4. In this case, since the quantized value is 0, the zero detector 25 outputs "1". Further, (0, 0) is input to the code length calculator 27 and the code length corresponding to it is output, but in this case, it is not the original code (variable length coding used here is zero run). Encode length and subsequent quantized values into a single codeword). Therefore, the code length calculator 27
The output value of "(x" in the figure indicates indefinite) is indefinite.
At the rising time t ₂ of the next clock, the zero detector 25
Output is '1', the zero run counter 26 is set to 1
However, the cumulative adder 28 is not operated and the time t
The state of ₁ is retained. Next, at time t ₃ , the quantized value 16 is input. Since the zero detector 25 still outputs "1" at this time, the zero run counter 26 is counted up to 2, but the cumulative adder 28 is still t _1.
Holds the state of. (2, 16) is input to the code length calculator 27 between times t ₃ and t ₄ , the code length 21 is calculated, and the cumulative adder 28 is updated to 29 at time t ₄ . Similarly, at time t ₅ , the cumulative adder 28 updates to 34.

The circuit operated at the timing described above stores the total code length of the code words of the quantized value of the DCT block in the register 29. Further, at time t ₆₄ when the quantized value of the next DCT block is input from the input terminal 24,
The cumulative adder 30 performs cumulative addition with the output value of the register 29. Such operation is repeated for 30 DCT blocks, 3
The sum of the code lengths of the large blocks with the 0DCT block as one block is calculated.

Therefore, as described above, the zero run length and the subsequent quantized value are collectively encoded into one codeword, and the code length corresponding to the codeword can be calculated, and the data amount can be estimated. it can.

By the way, in this encoding device, the maximum value of the quantized value after being quantized by the quantizer 16 is 255, and the input signal by the small blocker 10 is 8 pixels horizontally and 8 pixels vertically. Since it consists of pixels, the continuous quantization value 0
Is 63 at maximum (1 in FIG. 5 is a DC component, and the rest are AC components. Only the AC component is quantized by the quantization unit 16).

Therefore, the quantized value (8 bits) and the zero run counter (6 bits) are input to the code length calculator 27 as two input signals. Also, in this encoding device,
16 code length calculators 27 are required to estimate the data amount in each quantizer. However, when integrated into an IC, the scale of the calculation circuit of the data amount estimation unit in the above device becomes large, and it is necessary to reduce the circuit.

The present invention is to solve the above-mentioned conventional problems, and provides an encoding apparatus for reducing the circuit scale in the calculation circuit of the data amount estimation unit.

[0027]

Blocking means for collecting sampled values of an input signal into blocks for each of m × n pixels, orthogonal transforming means for orthogonally transforming each of the blocked blocks, and the orthogonal transforming. In an encoding device provided with a variable length encoding means for performing variable length encoding on the orthogonal component obtained by the means, or for performing variable length encoding on the quantized value after quantizing the orthogonal component, A limiter means for limiting the value of the orthogonal component or the quantized value to a predetermined range, and a code length for calculating a code length corresponding to a variable length code word obtained by the variable length coding means by the output of the limiter means. An encoding device comprising: a calculating unit.

[0028]

According to the present invention, with the above configuration, the calculation of the code length corresponding to the code word after the variable length coding is provided with the orthogonal component or the limiter for limiting the quantized value of the orthogonal component to a predetermined range, The code length is calculated using the output value.

[0029]

1 is a block diagram of a data amount estimating unit of an encoding apparatus according to an embodiment of the present invention. In the present embodiment, the configuration is almost the same as that of the above-described conventional device except for the data amount estimating unit, and therefore, the blocks having the same functions are designated by the same reference numerals.

In FIG. 1, 1 is an input terminal to which the quantized values quantized by the 16 kinds of quantizers shown in Table 1 are input, and 2 is 1 if the quantized value is 0. The zero detector, which outputs the signal and controls the zero-run counter 3 and the cumulative adder 7 which will be described later based on the signal, counts the period clock when the output of the zero detector 2 is "1", and if it is "0". Zero-run counter for resetting, 4 is a limiter for limiting the quantized value within a predetermined range, 5 is a limiter for limiting the count value within a predetermined range, 6 is a code length calculator for calculating the code length after encoding, and 7 is zero. If the output of the detector 2 is "0", calculation is performed to calculate the code length of the DCT block unit, 8 is a register that stores the code length of the DCT block unit that is the output of the cumulative adder 7, 9 Is the total code length of DCT block unit The output value is the cumulative adder for cumulative addition.

By the way, looking closely at the table showing the code lengths of the code words shown in Table 2, when the quantization value becomes 20 or more, the code lengths of the code words depend only on the output value of the zero run counter, If the output value of the zero run counter is 15 or more,
It can be seen that it depends only on the quantized value. Therefore, if the quantized value is 20 or more, the quantized value is set to 20, and if the output value of the zero run counter is 15 or more, even if the output value of the zero run counter is rounded to 15, the code length can be calculated. Turns out to be fine. That is, it is possible to limit the quantized value or the zero run counter to a predetermined range. Therefore, Table 2 can be changed to Table 3.

[0032]

[Table 3]

That is, as shown in FIG. 1, if the quantized value of the limiter 4 is 20 or more, it is rounded to 20, and the output value of the zero run counter 3 is 15 or more (zero run length is 15 or more) by the limiter 5. If rounded to 15, the signal input to the code length calculator 6 has a quantized value of 5 bits and a zero run counter output value of 4 bits. In other words, when comparing the conventional quantized value of 8 bits and the code length calculator 27 with the input of the output value of the zero run counter of 6 bits, it is possible to reduce the number by about 100 gates (16 × about 100 gates in this encoding device). .

Therefore, when the code lengths of the quantized values output from several kinds of quantizers are simultaneously calculated,
The circuit of the calculation circuit of the data amount estimation unit in the encoding device can be made smaller than the conventional circuit.

By the way, the code length calculator 6 can be realized by a ROM or a logic.

In the present embodiment, the quantized value and the zero run length are two-dimensionally the zero run length and the subsequent quantized value.
However, it is needless to say that the present invention is applicable and effective even when the rounded value is changed. Further, in the present embodiment, the zero run length and the quantized value following the zero run length are handled as two dimensions, but it is needless to say that the present invention is applicable and effective even if handled as one dimension. Although the value quantized by the quantizer is input from the input terminal 1, the present invention can be applied and is effective even if the value of the orthogonal component is directly input from the input terminal 1 without being quantized. Needless to say.

[0037]

By using the present invention, the circuit scale of the code length estimating unit can be made smaller than the conventional one,
The effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a data amount estimation unit of an encoding device according to an embodiment of the present invention.

FIG. 2 is a block diagram for explaining an entire conventional encoding device.

FIG. 3 is a block diagram of a conventional large block portion.

FIG. 4 is a schematic diagram showing a relationship between one frame of a conventional image signal and a DCT block.

FIG. 5 is a schematic diagram showing output numbers of orthogonal components of a conventional small block forming unit.

FIG. 6 is a schematic diagram showing the relationship between the quantization of a conventional DCT component and the band.

FIG. 7 is an explanatory diagram showing how to arrange each DCT block in the related art.

FIG. 8 is a block diagram of a conventional data amount estimation unit.

FIG. 9 is a diagram showing the operation timing of the circuit of the conventional data amount estimation unit.

[Explanation of symbols]

 1 Input Terminal 2 Zero Detector 3 Zero Run Counter 4 Limiter 5 Limiter 6 Code Length Calculator 7 Cumulative Adder 8 Register 9 Cumulative Adder 10 Small Blocking Part 11 Large Blocking Part 12 Orthogonal Transformer 13 Data Quantity Estimating Part 14 Quantizer determination unit 15 Data buffer 16 Quantization unit 17 Variable length encoder 18 Transmission unit 19 Luminance signal input unit 20 Color difference signal RY input unit 21 Color difference signal BY input unit 22 Frame memory 23 Address controller 24 Input Terminal 25 Zero detector 26 Zero run counter 27 Code length calculator 28 Cumulative adder 29 Register 30 Cumulative adder

Claims (2)

[Claims] 1. A block forming means for collecting sampled values of an input signal and forming a block for each of m × n pixels, an orthogonal transforming means for orthogonally transforming each of the blocked blocks, and an orthogonal transforming means. In a coding device including variable length coding means for performing variable length coding on an orthogonal component, or for quantizing the orthogonal component and then performing variable length coding on the quantized value, A value, or limiter means for limiting the quantized value to a predetermined range, and code length calculation means for calculating the code length corresponding to the variable length code word obtained by the variable length coding means by the output of the limiter means. An encoding device provided with. 2. An encoding apparatus according to claim 1, further comprising a limiting means for limiting a value of a zero run length in a quadrature component or a value after quantization and a value following the zero run to a predetermined range. .