JPH06104404A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent an effect by a change in threshold voltage at low-voltage driving and stabilize circuit operation, by changing a threshold voltage of a first inverter in accordance with an MOS transistor in an electronic switch and compensating a delay in writing time caused by a voltage change corresponding to the threshold voltage. CONSTITUTION:In a semiconductor device, a signal holding means 3 for holding a signal from a switch means 2 includes a p-channel transistor P1 and an n- channel transistor N1. The p-channel transistor P1 has a gate length Lp and a gate width Wp while the n-channel transistor N1 has a gate length Ln and a gate width Wn. Then, an expression I is satisfied, wherein BP and BN are current-drive performance in the transistors P1 and N1, VDD is a high power- supply voltage, and Vth is a threshold voltage. Since the threshold level is changed from a conventional level VDD/2 to (VDD-Vth)/2, a delay time (th) caused by a loss in voltage corresponding to the threshold voltage can be compensated. Consequently, an output signal during L to H writing time is provided to a next-stage circuit without delay, and stable operation is ensured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for use in the field of semiconductor memory, for example, for speeding up an operation after data writing to a latch circuit. [Background of the Invention] In recent years, along with the reduction in power consumption of semiconductor devices, it is possible to operate at a low voltage, such as a RAM (Random Acc
Many semiconductor memory devices such as ess memory) have been developed.

As a semiconductor memory device, for example, in a semiconductor memory such as a RAM, the wiring width and the wiring interval are reduced due to the miniaturization of the design rule accompanying the high integration, which prevents the occurrence of electromigration. From the viewpoint of power consumption reduction, the drive voltage has been reduced from the conventional 5 V drive to 3.3 V drive or even lower voltage drive.

However, in the process of lowering the driving voltage, the phenomenon of voltage drop (or voltage increase) corresponding to the threshold voltage, which was not a problem during high voltage driving, caused a write to the latch circuit during low voltage driving. The loading time is delayed, and this delay adversely affects the circuit at the next stage. Therefore, it is required to suppress the influence of the voltage drop (or voltage increase) corresponding to the threshold voltage at the time of driving at a low voltage and obtain a stable circuit operation.

[0004]

2. Description of the Related Art Conventional semiconductor memory devices of this type include, for example, those shown in FIGS.
FIG. 9 is a circuit diagram showing a configuration of a main part of a conventional example, and FIG. 9 is a plan view showing a main part of FIG. This semiconductor memory device is roughly classified into
It is composed of a buffer circuit 101, an electronic switch 102, and a latch circuit 103.

The buffer circuit 101 is a P channel MOS.
The inverter is composed of a transistor PP1 and an N-channel MOS transistor NN1 and outputs an inverted signal of an input signal. The electronic switch 102 is
The N-channel MOS transistor NN2 has one end connected to the buffer circuit 101, the other end connected to the latch circuit 103, and the gate G receiving a signal of a predetermined potential.

The latch circuit 103 includes a P-channel MOS transistor P11 between the high potential power line and the low potential power line.
And an N-channel MOS transistor N11 connected in series, and similarly, a P-channel MOS transistor P1 is provided between the high potential power line and the low potential power line.
2 and an N-channel MOS transistor N12 connected in series, and an inverter 105. The input and output of each of the inverters 104 and 105 are cross-connected to each other to form a flip-flop.

The threshold voltage V _th1 of the inverter 104 in FIG. 9 is defined as V _DD / 2. As shown in FIG. 9, the gate length of the P channel MOS transistor P11 in the inverter 104 is L _P1 and the gate width is W _P1 ,
The current driving capability is β _P1 , similarly, the gate length of the N-channel MOS transistor N11 is L _N1 , the gate width is W _N1 , the current driving capability is β _N1 , the high potential power supply voltage is V _DD , and the threshold voltage is V _th1 . In such a case, the gate lengths L _P1 and L _N1 and the gate width W of the P-channel MOS transistor P11 and the N-channel MOS transistor N11 in the inverter 104 are
The ratio of _P1 and W _N1 is

[0008]

[Equation 3]

[0009] In the above configuration, the predetermined input signal is inverted and output by the buffer circuit 101, and the inverted output signal is output via the electronic switch 102 to the latch circuit 1.
Held at 03. That is, in the latch circuit 103,
Until new writing from the buffer circuit 101,
The inverted output signal from the buffer circuit 101 is held and output to the outside.

[0010]

However, in such a conventional semiconductor memory device, the buffer circuit 1 is used.
The output signal from 01 constitutes N which constitutes the electronic switch 102.
Since it is configured to be held in the latch circuit 103 via the channel MOS transistor NN2, there are the following problems.

That is, since writing to the latch circuit 103 is performed through the N-channel MOS transistor NN2, the writing voltage drops by the threshold voltage of the N-channel MOS transistor NN2 as shown in FIG.
The writing time from “L” to “H” is delayed by the time t _n as compared with the writing from “L” to “L”, “H” to “H”, and “H” to “L”. .

When the drive voltage is high, the ratio of the threshold voltage to the drive voltage is small, so that the influence of the voltage drop corresponding to the threshold voltage is small. However, the lower the drive voltage is, the larger the ratio of the threshold voltage to the drive voltage is. Become. Therefore, in the process of lowering the driving voltage, the phenomenon of voltage drop corresponding to the threshold voltage, which was not a problem during high voltage driving, delays the writing time to the latch circuit during low voltage driving. It will adversely affect the circuit in the next stage.

When a P-channel MOS transistor PP2 is used as the electronic switch 102, FIG.
As shown in, the write time from "H" to "L" is delayed by the time t _p due to the voltage increase of the threshold voltage of the P-channel MOS transistor PP2. Therefore, similar to the case of the N-channel MOS transistor NN2 described above. The problem will occur.

[Object] Therefore, it is an object of the present invention to provide a semiconductor memory device which suppresses the influence of a voltage fluctuation corresponding to a threshold voltage during low voltage driving and obtains stable circuit operation.

[0015]

A semiconductor memory according to the present invention.
In order to achieve the above purpose, the device is shown in the principle diagram in Fig. 1.
The input signal input from the input end to the output end
Switch means 2 for switching whether or not to perform, and the switch
A signal holding means 3 for holding the output signal from the means 2.
In this semiconductor memory device, the signal holding means 3 is
A P channel MOS is provided between the high potential power line and the low potential power line.
Transistors P1 and P2 and N-channel MOS transistor
A first inverter 4 formed by connecting the stars N1 and N2 in series and
And each input and output of the second inverter 5 are cross-connected,
The switch means 2 uses the source S as an input end.
The drain D as an output terminal and the gate G receives a predetermined signal.
N-channel MOS transistor NN2
P-channel MOS transistor in one inverter 4
Set the gate length of P1 to L_P, The gate width is W_P, Current drive capacity
Β_P, Similarly, the N-channel MOS transistor N1
Gate length is L_N, The gate width is W_N, Current drive capacity β_N
And the high potential power supply voltage is V_DD, The threshold voltage is V _thWhen
, The P-channel MOS transistor in the first inverter 4
Of the transistor P1 and the N-channel MOS transistor N1
Gate length L_P, L_NAnd gate width W_P, W_NThe ratio of

[0016]

[Equation 4]

It is configured as represented by. Further, the switch means 2 uses the source S as an input end, and
In the case of the P-channel MOS transistor PP2 having the drain D as an output terminal and the gate G receiving a predetermined signal,
The ratio of the gate lengths L _P and L _N and the gate widths W _P and W _N of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 in the first inverter 4 is

[0018]

[Equation 5]

It is configured as represented by.

[0020]

According to the present invention, the threshold voltage of the first inverter, which has been conventionally defined by V _DD / 2, is set to (V _DD ± V _th ) / 2, so that the voltage variation corresponding to the threshold voltage in the switch means is caused. The writing time delay is corrected. That is, the influence of the voltage fluctuation corresponding to the threshold voltage during low voltage driving is suppressed, and stable circuit operation is obtained.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 2 and 3 are diagrams showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is a circuit diagram showing a configuration of a main part of this embodiment,
FIG. 3 is a plan view showing a main part of FIG. First, the configuration will be described.

2 and 3, the same numbers as the numbers given to the principle diagram shown in FIG. 1 indicate the same parts. The semiconductor memory device of this embodiment is roughly classified into a buffer circuit 1,
It is composed of an electronic switch 2 which is a switch means and a latch circuit 3 which is a signal holding means. Buffer circuit 1
Is similar to that of the conventional example shown in FIG. 8, the P channel MOS transistor PP1 and the N channel MOS transistor NN.
The inverter is composed of 1 and outputs an inverted signal of an input signal.

The electronic switch 2 is composed of an N-channel MOS transistor NN2 having a source S connected to the buffer circuit 1, a drain D connected to the latch circuit 3, and a gate G receiving a signal of a predetermined potential. The latch circuit 3 includes a first inverter 4 including a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected in series between a high potential power line and a low potential power line,
Similarly, a second inverter 5 including a P-channel MOS transistor P2 and an N-channel MOS transistor N2 connected in series between a high-potential power supply line and a low-potential power supply line, and Are cross-connected to each other to form a flip-flop.

The first inverter 4 in this embodiment is
Threshold voltage V _thA is defined as (V _DD −V _th ) / 2, and as shown in FIG. 3, the gate length of the P-channel MOS transistor P1 in the first inverter 4 is L _P and the gate width is W _P. , The current driving capability is β _P , similarly, the gate length of the N-channel MOS transistor N1 is L _N , the gate width is W _N , the current driving capability is β _N , the high potential power supply voltage is V _DD , and the threshold voltage is V _th. In such a case, the ratio of the gate lengths L _P and L _N and the gate widths W _P and W _N of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 in the first inverter 4 is

[0025]

[Equation 6]

It is set as represented by. Specifically, in the present embodiment, first, when adjusting the gate width without changing the gate length, (V _DD −V _th ) / V _DD times on the P-channel MOS transistor P1 side and (V _DD −V _th ) / V _{DD on} the N-channel MOS transistor N1 side. V _DD + V _th ) / V _DD times, and using the gate width W _P1 of the P-channel MOS transistor P11 and the gate width W _N1 of the N-channel MOS transistor N11 in FIG.

[0027]

[Equation 7]

The gate widths W _P and W _N represented by are set. Further, in the case of adjusting the gate length without changing the gate width, V _DD /
(V _DD −V _th ) times, N-channel MOS transistor N1
On the side, it is adjusted to be V _DD / (V _DD + V _th ) times, and the P-channel MOS transistor P11 in FIG.
Gate length L _P1 , N channel MOS transistor N11
Using the gate length L _N1 of

[0029]

[Equation 8]

The gate lengths L _P and L _N represented by are set. In addition to the above, it is also possible to adjust by changing both the gate length and the gate width. Next, the operation will be described. FIG. 4 is a waveform diagram for explaining an operation example of the present embodiment. In the figure, (A) shows a conventional threshold voltage and (B) shows a threshold voltage in this embodiment.

That is, in this embodiment, the threshold level is V
_{By setting DD} / 2 to (V _DD −V _th ) / 2, conventionally, the delay time t _n due to the voltage drop corresponding to the threshold voltage is corrected, and the delay occurs when writing from “L” to “H”. Without doing so, the output signal is output to the next stage circuit. Therefore, adverse effects due to the voltage drop corresponding to the threshold voltage during low voltage driving are prevented, and stable circuit operation can be obtained.

5 and 6 are views showing another embodiment of the semiconductor memory device according to the present invention. FIG. 5 is a circuit diagram showing the configuration of the main part of this embodiment, and FIG. 6 is the main part of FIG. FIG. First, the configuration will be described. In FIGS. 5 and 6, the same numbers as those used in the embodiments shown in FIGS. 2 and 3 indicate the same parts.

In the electronic switch 2 of this embodiment, the source S is
Connect to the buffer circuit 1 and connect the drain D
Circuit 3 and receives a signal of a predetermined potential at the gate G
Comprised of a P-channel MOS transistor PP2
It Therefore, the threshold of the first inverter 4 in this embodiment is
Value voltage V_thBIs (V_DD+ V _th) / 2 is defined as
As shown in FIG. 6, the P channel in the first inverter 4 is
The gate length of the MOS transistor P1 to L_P, Gate width
W_P, Current drive capacity β_P, Similarly N channel MO
Set the gate length of the S transistor N1 to L_N, Gate width
W_N, Current drive capacity β_NAnd the high potential power supply voltage
V_DD, The threshold voltage is V_thIn case of,
P-channel MOS transistor P1 and N channel in
Gate length L of the MOS transistor N1_P, L_NAnd
Width W_P, W _NThe ratio of

[0034]

[Equation 9]

It is set as represented by. Sanawa
Then, like the above-mentioned embodiment, first, without changing the gate length,
When adjusting with the gate width, P-channel MOS transistor
On the P1 side (V_DD+ V_th) / V_DDDouble, N channel MO
On the S transistor N1 side (V_DD-V_th) / V_DDDouble
P channel MOS in FIG.
Gate width W of transistor P11 _P1, N-channel MOS
Gate width W of transistor N11_N1With,

[0036]

[Equation 10]

The gate widths W _P and W _N represented by are set. Further, in the case of adjusting the gate length without changing the gate width, V _DD /
(V _DD + V _th ) times, N-channel MOS transistor N1
On the side, it is adjusted to be V _DD / (V _DD −V _th ) times, and the P channel MOS transistor P11 in FIG.
Gate length L _P1 , N channel MOS transistor N11
Using the gate length L _N1 of

[0038]

[Equation 11]

The gate lengths L _P and L _N represented by are set. In addition to the above, it is also possible to adjust by changing both the gate length and the gate width. Next, the operation will be described. FIG. 7 is a waveform diagram for explaining an operation example of the present embodiment, in which (C) shows the conventional threshold voltage and (D) shows the threshold voltage in the present embodiment.

That is, in this embodiment, the threshold level is V
_{By setting DD} / 2 to (V _DD + V _th ) / 2, the delay time t _p due to the voltage drop corresponding to the threshold voltage is conventionally corrected, and a delay occurs when writing from “H” to “L”. The output signal is output to the next-stage circuit without any operation. Therefore, the adverse effect due to the voltage increase of the threshold voltage during low voltage driving is prevented, and stable circuit operation can be obtained.

As described above, in the present embodiment, the threshold voltage of the first inverter, which is conventionally defined by V _DD / 2, is set to (V _DD ±
By setting V _th ) / 2, the delay of the writing time due to the voltage fluctuation of the threshold voltage in the switch means can be corrected,
It is possible to improve the rising and falling characteristics of the input signal.

Therefore, it is possible to suppress the influence of the voltage fluctuation corresponding to the threshold voltage during the low voltage driving, and it is possible to obtain a stable circuit operation during the low voltage driving.

[0043]

According to the present invention, the threshold voltage of the first inverter, which is conventionally defined by V _DD / 2, is (V _DD ± V _th ) / 2.
By doing so, it is possible to correct the delay of the writing time due to the voltage fluctuation corresponding to the threshold voltage in the switch means. Therefore, it is possible to suppress the influence of the voltage fluctuation corresponding to the threshold voltage during low voltage driving, obtain stable circuit operation, and reduce power consumption.

[Brief description of drawings]

FIG. 1 is a principle diagram of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing a main configuration of the present embodiment.

FIG. 3 is a plan view showing a main part of FIG.

FIG. 4 is a waveform diagram for explaining an operation example of the present embodiment.

FIG. 5 is a circuit diagram showing a main part configuration of another embodiment of the present invention.

FIG. 6 is a plan view showing a main part of FIG.

FIG. 7 is a waveform diagram for explaining an operation example of another embodiment.

FIG. 8 is a circuit diagram showing a configuration of a main part of a conventional example.

FIG. 9 is a plan view showing a main part of FIG.

FIG. 10 is a waveform diagram for explaining an operation example of a conventional example.

FIG. 11 is a waveform chart for explaining an operation example of another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 buffer circuit 2 electronic switch (switch means) 3 latch circuit (signal holding means) 4 first inverter 5 second inverter PP1, PP2 P channel MOS transistor NN1, NN2 N channel MOS transistor P1, P2 P channel MOS transistor N1, N2 N-channel MOS transistor S source D drain G gate

Claims (2)

[Claims] 1. A semiconductor memory device comprising: switch means for switching whether or not an input signal input from an input terminal is output from an output terminal; and signal holding means for holding an output signal from the switch means. The signal holding means includes a P-channel MOS transistor and an N-channel MO between the high potential power line and the low potential power line.
The input and output of a first inverter and a second inverter formed by connecting S transistors in series are cross-connected to each other, and the switch means has a source as an input end, and
An N-channel MOS transistor having a drain as an output terminal and a gate receiving a predetermined signal. The gate length of the P-channel MOS transistor in the first inverter is L _P , the gate width is W _P , and the current driving capability is β _P. , The gate length of the N-channel MOS transistor is L _N , the gate width is W _N , and the current drive capability is β _N ,
When the high potential power supply voltage is V _DD and the threshold voltage is V _th , the gate length L _P of the P-channel MOS transistor and the N-channel MOS transistor in the first inverter,
The ratio of L _N and gate width W _P , W _N is A semiconductor memory device represented by: 2. The switch means is a P-channel MOS transistor having a source as an input end, a drain as an output end, and a gate receiving a predetermined signal, and a gate length of the P-channel MOS transistor in the first inverter is set. L _P , gate width W _P , current driving capability β _P , similarly, N-channel MOS transistor gate length L _N , gate width W _N , current driving capability β _N , high potential power supply voltage V _{When DD} and the threshold voltage are V _th , the gate length L _P of the P-channel MOS transistor and the N-channel MOS transistor in the first inverter,
The ratio of L _N and gate width W _P , W _N is The semiconductor memory device according to claim 1, wherein