JPH06103751A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To find mispackage of the semiconductor storage device as a 5V operating version in its test before shipment for a 3V operating version of the semiconductor storage device by making the device unoperatable when its power source voltage is 5V in discrimination of 3V from 5V in power source voltage. CONSTITUTION:In the 3V operating version, when the power source voltage is 3V, a voltage level at a node N is lower than a logical threshold value of an inverter 4 to be 'L', and hence a reset enable signal RE is 'L'. In this time, the device is operated by an internal row address strobe signal RAS 6 which is an output of a NOR circuit 5. When the power source is 5V, the voltage level at the node N is higher than the logical threshold value of the inverter 4 to be 'H', and hence the reset enable signal RE is 'H'. In this time, the output of the NOR circuit 5 is 'L' to be constant, and the operation of the device is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating as a low voltage operating version.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been reduced in power supply voltage in order to reduce power consumption and improve reliability due to miniaturization of transistors and the like. As a result, even if semiconductor memory devices with the same memory capacity are used,
There are two types: a 5V operating version that operates at V and a 3V operating version as a low voltage operating version that operates at a power supply voltage of 3V, which has become widespread in recent years.

The 3V operation version normally operates even when the power supply voltage is 5V because of a voltage operation margin. Therefore, if 5
If the 3V operation version is mistakenly installed as the V operation version, the reliability may be deteriorated and a problem may occur in the market.

[0004]

In the conventional semiconductor memory device, since the 3V operating version operates even when the power supply voltage is 5V due to the voltage operating margin, the reliability is deteriorated if it is mounted by mistake as the 5V operating version. , There was a problem that it could cause troubles in the market.

The present invention has been made to solve such a problem, and in the 3V operating version, a semiconductor memory which distinguishes between 3V and 5V of the power supply voltage and does not operate when the power supply voltage is 5V. The purpose is to obtain the device.

[0006]

A semiconductor memory device according to the present invention outputs a control signal indicating whether to operate or stop depending on whether a voltage level according to a power supply voltage level is higher or lower than a reference voltage. The power supply voltage level detector circuit is provided.

[0007]

According to the present invention, the power supply voltage level detector circuit outputs a control signal indicating whether to operate or stop depending on whether the voltage level according to the power supply voltage level is higher or lower than the reference voltage.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. 1 is a circuit diagram showing a first embodiment of the present invention, in which FIG. 1 (a) shows a reset enable signal generating circuit,
FIG. 3B shows an external input signal disable circuit.
In FIG. 1A, 1 is a power supply line for supplying a power supply voltage V _CC , 2 is an n-channel transistor connected to the power supply line 1, for example, two n-channel transistors, and 3 is connected to an n-channel transistor 2. A resistor 4 having a high resistance value, the other end of which is grounded, is, for example, two inverters connected in series and connected to the node N between the n-channel transistor 2 and the resistor 3.

Further, in FIG. 1B, reference numeral 5 is a NOR circuit, which serves as a reset enable signal RE output from the reset enable signal generating circuit in FIG. 1A and a control signal for operating the semiconductor memory device. The internal row address strobe signal RAS is output in response to the external row address strobe signal EXT bar RAS.

The reset enable signal generating circuit of FIG. 1A and the external input signal disable circuit of FIG. 1B constitute a power supply voltage level detector circuit.
This power supply voltage level detector circuit is provided for the 3V operation version of the semiconductor memory device.

Next, the operation of the above configuration will be described. Although the node N is grounded via the resistor 3, since the resistor 3 has a high resistance value and is not capable of flowing much current, the voltage level of the node N is V _CC -2V _th (V _th is The threshold voltage of the n-channel transistor 2).

Here, the operation when the power supply voltage V _CC is 3 V will be described. Since the threshold value V _th of the n-channel transistor 2 is set to, for example, about 1V, the voltage level of the node N is about 3V-2 × 1V = 1V.
Since the logic threshold value of the inverter 4 is set to, for example, 2V, the level of 1V of the node N, which is smaller than the logic threshold value 2V of the inverter 4, is low level (hereinafter, "L"
Will be written).

Therefore, the output of the first-stage inverter 4 becomes high level (hereinafter referred to as "H"), and the reset enable signal RE which is the output of the second-stage inverter 4 becomes "L". When the reset enable signal RE is "L", the NOR circuit 5 becomes equivalent to an inverter and the internal row address strobe signal RA synchronized with the external row address strobe signal EXT bar RAS which is an external control signal.
Generate S. This internal row address strobe signal R
The semiconductor memory device operates by the AS.

Next, the operation when the power supply voltage V _CC is 5V will be described. Since n- threshold V _th channel transistor 2 is likewise e.g., about 1V and if the power supply voltage V _CC as described above is 3V, the voltage level of the node N 5
It becomes about V−2 × 1V = 3V. The logic threshold value of the inverter 4 is 2 as in the case where the power supply voltage V _CC is 3V described above.
Since it is about V, the level of 3V at the node N is higher than the logic threshold value 2V of the inverter 4 and therefore becomes "H".

Therefore, the output of the first-stage inverter 4 becomes "L", and the reset enable signal RE which is the output of the second-stage inverter 4 becomes high level (hereinafter referred to as "H"). When the reset enable signal RE is "H", the internal row address strobe signal RAS which is the output of the NOR circuit 5 becomes "L" regardless of the state of the external row address strobe signal EXT bar RAS.
Therefore, the operation of the semiconductor memory device is stopped.

Next, the operation of the 3V operation version of the semiconductor memory device based on the above operation will be described with reference to the timing chart of FIG. In FIG. 2, the solid line indicates that the power supply voltage V _CC is 3
The operation of the semiconductor memory device when V or 5V is shown, and the broken line shows the operation of the semiconductor memory device when the power supply voltage V _CC is only 3V.

Further, EXT bar RAS is an external row address strobe signal as a control signal for operating the semiconductor memory device as described above, and determines a row address. EXT bar CAS is an external column address strobe signal as a control signal for determining a column address of the semiconductor memory device, EXT bar WE is an external write enable signal for controlling reading or writing, EX
TA _dd is a row address signal or a column address signal,
D _out is read data.

First, the operation when the power supply voltage V _CC is 3V will be described. Since the reset enable signal RE output from the reset enable generation circuit of FIG. 1A becomes "L" as shown by the broken line, the NOR circuit 5 of the external input signal disable circuit of FIG. The internal row address strobe signal RAS synchronized with the input external row address strobe signal EXT bar RAS is output.

When the external row address strobe signal EXT bar RAS becomes "L", the NOR circuit 5
Internal row address strobe signal RAS output from
Becomes "H" indicated by a broken line and the external column address strobe signal bar CAS becomes "L", the address Y of the row address signal or the column address signal EXTA _dd is selected. Thereafter, the mechanism data of the address signal Y is output as the read data D _{out under the} control of the write enable signal EXT bar WE.

Next, the operation when the power supply voltage V _CC is 5 V will be described. Since the reset enable signal RE output from the reset enable signal generation circuit of FIG. 1A becomes “H” as shown by the solid line, the output of the NOR circuit 5 of the external input signal disable circuit of FIG. 1B is output. The internal row address strobe signal RAS is constant at "L" as shown by the solid line even if the external row address strobe signal EXT bar RAS becomes "L". Therefore, the row address cannot be selected and the operation stops.

In the first embodiment, as described above, in the 3V operation version, the node N corresponding to the level of the power supply voltage V _CC is used.
When the voltage level of the inverter 4 is lower than the logic threshold voltage of the inverter 4, the reset enable signal RE is set to "L" to operate the device, and the voltage level of the node N changes to the inverter 4
By stopping the operation of to the equipment to "H" reset enable signal RE when higher than the logic threshold voltage of the operation when operating with a power supply voltage V _CC when the power supply voltage V _{C C} is 3V is 5V Since the power supply is stopped, the power supply voltage of 3V and 5V can be distinguished.

Example 2. Second Embodiment FIG. 3 is a circuit diagram showing a reset enable signal generating circuit according to a second embodiment of the present invention.
The node N is connected to the power supply line 1 via the resistor 6 and grounded via the resistor 3 having a high resistance value, and the voltage level of the node N is the level of the power supply voltage V _CC and the resistors 3 and 6. And the resistance value of. Further, as in FIG. 1, for example, two inverters 4 connected in series are connected to the node N.

Also in the second embodiment, the resistors 3 and 6 are used.
By setting the resistance value of and the logical threshold value of the inverter 4,
As in the first embodiment, when the power supply voltage V _CC is 3V, the node N is “L”, that is, the reset enable signal RE is “L”, and when the power supply voltage V _CC is 5V, the node N is “L”.
Is "H", that is, the reset enable signal RE is "H". As a result, as described in the first embodiment, when the power supply voltage V _CC is 3V, the operation is performed and the power supply voltage V _CC is 5V.
In the case of, the operation stops.

Example 3. Fourth Embodiment FIG. 4 is a circuit diagram showing a reset enable signal generating circuit according to a third embodiment of the present invention.
In the figure, the node N is a p-channel transistor 7
Is connected to the power supply line 1 via the n-channel transistor 8 and is grounded. The gate of p-channel transistor 7 is grounded and the gate of n-channel transistor 8 is connected to power supply line 1, so that both p-channel transistor 7 and n-channel transistor 8 are on. Therefore, the p-channel transistor 7 and the n-channel transistor 8 become a resistance component. That is, the third embodiment operates similarly to the second embodiment, and the description thereof will be omitted here.

Example 4. FIG. 5 is a circuit diagram showing an external input signal disable circuit according to the fourth embodiment of the present invention.
In the figure, a bar OEM signal is input to the NOR circuit 5 in place of the external row address strobe signal EXT bar RAS of FIG. This bar OEM signal is used to output the data written in the semiconductor memory device, and when it is "L", that is, the output of the NOR circuit 5 is O.
When the EM signal is "H", the data written in the semiconductor memory device is output.

When the power supply voltage V _CC is 3 V, the reset enable signal RE is "L" as described in the first embodiment.
Therefore, the NOR circuit 5 is equivalent to an inverter. Therefore, the OEM signal operates in synchronization with the bar OEM signal,
When the bar OEM signal becomes "L" and the OEM signal becomes "H", the output of the data written in the semiconductor memory device is enabled and the normal operation is performed.

When the power supply voltage V _CC is 5 V, the reset enable signal RE is "H" as described in the first embodiment.
Therefore, the OEM signal output from the NOR circuit 5 is constant at "L" regardless of the bar OEM signal, so that the output of the read data written in the semiconductor memory device is disabled.

The difference between the fourth embodiment and the first to third embodiments is that in the first to third embodiments, when the power supply voltage V _CC is 5 V, the external row address strobe signal EXT for operating the semiconductor memory device is used. While the operation of the semiconductor memory device is stopped by disabling the bar RAS, in the fourth embodiment, when the power supply voltage V _CC is 5 V, the external row address strobe signal EXT bar RAS is left as it is and the semiconductor memory device is stopped. It is to operate inside the device and disable the output of read data.

According to the fourth embodiment, since it is configured as described above, it operates in the semiconductor memory device.
Compared to the first to third embodiments, since the stress can be applied to the internal circuit in the voltage acceleration test such as burn-in, the burn-in test can be performed.

Example 5. 6 is a circuit diagram showing a reset enable signal generating circuit according to a fifth embodiment of the present invention.
In the figure, 1 to 4 are the same as those in FIG. 1, and 9 is a NOR circuit which receives the output of the inverter 4 as one input and generates the reset enable signal RE with the reset disable signal RD as the other input.

The reset disable signal RD is controlled to "H" or "L" by timing control of an external input signal of the semiconductor memory device or application of a high voltage (a voltage out of spec) to the external input terminal, and the semiconductor internal Is a signal generated in.

Next, the operation of the above configuration will be described. When the reset disable signal RD is "L", the NOR circuit 9
Is equivalent to an inverter, and its output becomes an inverted signal of the output of the inverter 4, that is, the input signal of the inverter 4. That is, when the reset disable signal RD is "L", the reset enable signal generation circuit operates as in the first embodiment.
Works the same as.

Briefly explaining the operation, when the power supply voltage V _CC is 3V, the voltage level of the node N is "L" because it is lower than the logic threshold value of the inverter 4, and therefore the reset enable signal RE is "L". Becomes In this case,
The internal row address strobe signal RAS synchronized with the external row address strobe signal EXT bar RAS is generated from the external input signal disable circuit of (b), and the semiconductor memory device operates.

When the power supply voltage V _CC is 5V, the voltage level of the node N is higher than the logic threshold value of the inverter 4 and therefore becomes "H", so that the reset enable signal RE becomes "H". In this case, if the external input signal disable circuit of FIG. 1B is used, the internal row address strobe signal RAS generated from the external input signal disable circuit becomes "L" constant, so that the operation of the semiconductor memory device is performed. Will stop. If the external input signal disable circuit of FIG. 5 is used, the semiconductor memory device operates, but the stored read data is disabled and not output.

As described above, if the semiconductor memory device is not operated or the read data is not output when the power supply voltage V _CC is 5 V, the power supply voltage margin test performed before shipping in-house cannot be performed. In order to avoid this, at the time of a power supply voltage margin test or the like, the reset disable signal RD signal is set to "H" as described above and the reset enable signal RE is kept at "L" regardless of the voltage level of the node N. As a result, the semiconductor memory device is operated.

Example 6. 7 is a circuit diagram showing a reset enable signal generating circuit according to a sixth embodiment of the present invention.
In the figure, 1, 3, 4 and 6 are the same as those in FIG.
As in the case of FIG. 6, a NOR circuit 9 that receives the output of the inverter 4 and the reset disable signal RD is provided.

In the sixth embodiment, the input level of the inverter 4 is determined in the same manner as in the second embodiment, and thereafter the same operation as in the fifth embodiment is performed. That is, when the reset disable signal RD is "L", the input level of the inverter is output, and the reset disable signal RD is "H".
When the reset enable signal RE is
The output is constant at "L" regardless of the output, and the same effect as that of the fifth embodiment can be obtained.

Example 7. FIG. 8 is a circuit diagram showing a reset enable signal generating circuit according to a seventh embodiment of the present invention.
In the figure, 1, 4, 7 and 8 are the same as those in FIG.
As in the case of FIG. 6, a NOR circuit 9 that receives the output of the inverter 4 and the reset disable signal RD is provided.

In the seventh embodiment, the same operation as in the third embodiment is performed to determine the input level of the inverter, and thereafter the same operation as in the fifth embodiment is performed. That is, when the reset disable signal RD is "L", the input level of the inverter is output, and when the reset disable signal RD is "H", the reset enable signal RE becomes "L" constant, and thus the fifth embodiment described above. The same effect as can be obtained.

[0040]

As described above, according to the present invention, the power supply voltage for outputting the control signal indicating whether to operate or stop depending on whether the voltage level according to the power supply voltage level is higher or lower than the reference voltage. Due to the provision of the level detector circuit, in the 3V operation version, the power supply voltage is 3V and 5V.
When the power supply voltage is 3V, the operation is performed, and when the power supply voltage is 5V, the operation is stopped.
Even if it is erroneously mounted as the V-operation version, it is possible to make it defective in the rough test after mounting, and there is an effect that it is not erroneously mounted and not shipped.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a reset enable signal generating circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a reset enable signal generating circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an external input signal disable circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a reset enable signal generating circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a reset enable signal generating circuit according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a reset enable signal generating circuit according to a seventh embodiment of the present invention.

[Explanation of symbols]

 1 Power Line 2 n-Channel Transistor 3 Resistor 4 Inverter 5 NOR Circuit 6 Resistor 7 p-Channel Transistor 8 n-Channel Transistor 9 NOR Circuit

Claims (1)

[Claims] 1. A power supply voltage level detector circuit for outputting a control signal indicating whether to perform an operation or stop depending on whether a voltage level according to a power supply voltage level is higher or lower than a reference voltage. Semiconductor memory device.